diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2017-03-23 19:22:39 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-03-30 10:12:28 +0200 |
| commit | 78c138fb573e95333d612a9481cc7b4c1a8c176f (patch) | |
| tree | 28a88783f0b4e4bb461851b5ca47b209461aa10b /board/toradex/colibri_imx6 | |
| parent | b173fdcd3cd8581cdc9c350099ddb02fb60e3258 (diff) | |
common: apalis/colibri imx6: spl: add config to silence console output
This adds a Kconfig SPL_SILENCE_CONSOLE which allows to suppress any
console output which in the normal program flow is printed in the SPL.
Error messages and the likes will still be printed.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'board/toradex/colibri_imx6')
| -rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 1fa0bf6252..8bf4046e7d 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1062,10 +1062,14 @@ static void spl_dram_init(void) case TEMP_COMMERCIAL: case TEMP_EXTCOMMERCIAL: if (is_cpu_type(MXC_CPU_MX6DL)) { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n"); +#endif ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); +#endif ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1073,9 +1077,14 @@ static void spl_dram_init(void) case TEMP_AUTOMOTIVE: default: if (is_cpu_type(MXC_CPU_MX6DL)) { +#ifndef CONFIG_SPL_SILENT_CONSOLE + puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n"); +#endif ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); +#endif ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; |