diff options
| author | Wolfgang Denk <wd@denx.de> | 2011-12-07 09:09:58 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-12-07 09:09:58 +0100 |
| commit | c786f54b9ace5d7b20a0404a7deb1bae683cd4e8 (patch) | |
| tree | 8c612b0abb45c0b1bb1ca39df97620a0ab026797 /board | |
| parent | 99dee4b2ef570f289e2b1f105df0fdb8ad57ebd1 (diff) | |
| parent | 15422043c4a213dc5d7d59a337be1ab34c9b2e7f (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
davinci: Remove unwanted memsize.c from hawkboard's nand spl build
devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss
da850evm: pass board revision info to kernel
arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings
arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
MX35: flea3: changes due to hardware revision B
MX: serial_mxc: cleanup removing nasty #ifdef
M28: Fix OB1 bug in GPIO driver
MXS: Add static annotations to dma driver
apbh_dma: return error value on timeout
Efika: Configure additional regulators for HDMI output
mx5: Correct a warning in clock.c
MC13892: Add REGMODE0 bits definitions
mx51evk: Configure the pins as GPIOs prior to using gpio_get_value
mx53smd: Configure the pins as GPIOs prior to using gpio_get_value
mx53evk: Configure the pins as GPIOs prior to using gpio_get_value
mx53ard: Configure the pins as GPIOs prior to using gpio_get_value
mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
OMAP3: Add SPL_BOARD_INIT hook
AM3517 CraneBoard: Add SPL support
AM3517: Add SPL support
OMAP3: Add SPL support to omap3_evm
OMAP3: Add SPL support to Beagleboard
OMAP3 SPL: Add identify_nand_chip function
OMAP3 SPL: Rework memory initalization and devkit8000 support
OMAP3: Suffix all Micron memory timing parts with their speed
OMAP3: Add optimal SDRC autorefresh control values
omap3: mem: Add MCFG helper macro
OMAP3: Remove get_mem_type prototype
OMAP3: Change mem_ok to clear again after reading back
OMAP3: Add a helper function to set timings in SDRC
OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
omap3: mem: Comment enable_gpmc_cs_config more
ARM: davici_emac: Fix condition for number of phy detects
arm: printf() is not available in some SPL configurations
arm, davinci: add support for am1808 based enbw_cmc board
arm, davinci: move misc function in arch tree
arm, board/davinci/common/misc.c: Codingstyle cleanup
arm, davinci, da850: add uart1 tx rx pinmux config
arm, davinci: move davinci_rtc struct to hardware.h
arm, davinci: Remove duplication of pinmux configuration code
arm, hawkboard: Use the pinmux configurations defined in the arch tree
arm, da850evm: Use the pinmux configurations defined in the arch tree
arm, da850: Add pinmux configurations to the arch tree
arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes
arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins
arm, davinci: Move pinmux functions from board to arch tree
arm, arm926ejs: always do cpu critical inits
omap_gpmc: use SOFTECC in SPL if it's enabled
nand_spl_simple: add support for software ECC
AM3517: move AM3517 specific mux defines to generic header
AM35xx: add EMAC support
davinci_emac: hardcode 100Mbps for AM35xx and RMII
davinci_emac: fix for running with dcache enabled
arm926ejs: add noop implementation for dcache ops
davinci_emac: conditionally compile specific PHY support
davinci_emac: use internal addresses in buffer descriptors
davinci_emac: move arch-independent defines to separate header
BeagleBoard: config: Really switch to ttyO2
ARM: davinci_dm6467Tevm: Fix build breakage
ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused
ARM: OMAP3: Remove unused define SDRC_R_C_B
ARM: OMAP3: Remove unused define CONFIG_OMAP3430
omap4: fix IO setting
omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses
omap4460: add ES1.1 identification
omap4: emif: fix error in driver
omap: remove I2C from SPL
omap4460: fix TPS initialization
omap: fix cache line size for omap3/omap4 boards
omap4: ttyO2 instead of ttyS2 in default bootargs
omap: Improve PLL parameter calculation tool
start.S: remove omap3 specific code from start.S
armv7: setup vector
armv7: include armv7/cpu.c in SPL build
armv7: disable L2 cache in cleanup_before_linux()
arm, arm926ejs: Fix clear bss loop for zero length bss
PXA: Move colibri_pxa270 to board/toradex/
PXA: Flip colibri_pxa27x to pxa-common.h
PXA: Introduce common configuration header for PXA
PXA: Rename pxa_dram_init to pxa2xx_dram_init
PXA: Squash extern pxa_dram_init()
PXA: Export cpu_is_ and pxa_dram_init functions
PXA: Cleanup Colibri PXA270
PXA: Replace timer driver
PXA: Add cpuinfo display for PXA2xx
PXA: Separate PXA2xx CPU init
PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X
PXA: Unify vpac270 environment size
PXA: Enable command line editing for vpac270
PXA: Adapt Voipac PXA270 to OneNAND SPL
PXA: Drop Voipac PXA270 OneNAND IPL
PXA: Fixup PXA25x boards after start.S update
PXA: Re-add the Dcache locking as RAM for pxa250
PXA: Rework start.S to be closer to other ARMs
PXA: Drop XM250 board
PXA: Drop PLEB2 board
PXA: Drop CRADLE board
PXA: Drop CERF250 board
Fix regression in SMDK6400
nand: Add common functions to linux/mtd/nand.h
Ethernut 5 board support
net: Armada100: Fix compilation warnings
ARM: remove duplicated code for LaCie boards
ARM: add support for LaCie 2Big Network v2
mvsata: fix ide_preinit for missing disks
netspace_v2: Read Ethernet MAC address from EEPROM
omap3evm: Add support for EFI partitions
part_efi: Fix compile errors
Diffstat (limited to 'board')
69 files changed, 2160 insertions, 3546 deletions
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index 64f4b57f1b..34ede87ff4 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -160,7 +160,7 @@ static void board_setup_sdram(void) writel(0x2000, &esdc->esdctl0); writel(0x2000, &esdc->esdctl1); - board_setup_sdram_bank(CSD1_BASE_ADDR); + board_setup_sdram_bank(CSD0_BASE_ADDR); } static void setup_iomux_uart3(void) @@ -229,7 +229,7 @@ int board_early_init_f(void) (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ - mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c new file mode 100644 index 0000000000..dc5350dc28 --- /dev/null +++ b/board/LaCie/common/common.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) + +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +void mv_phy_88e1116_init(const char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac_addr) +{ + int ret; + ushort version; + + /* I2C-0 for on-board EEPROM */ + i2c_set_bus_num(0); + + /* Check layout version for EEPROM data */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &version, 2); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + version = be16_to_cpu(version); + if (version < 1 || version > 3) { + printf("Error: unknown version %d for EEPROM data\n", + version); + return -1; + } + + /* Read Ethernet MAC address from EEPROM */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6); + if (ret != 0) + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; +} +#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h new file mode 100644 index 0000000000..82a9522236 --- /dev/null +++ b/board/LaCie/common/common.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef _LACIE_COMMON_H +#define _LACIE_COMMON_H + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +void mv_phy_88e1116_init(const char *name); +#endif +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac); +#endif + +#endif /* _LACIE_COMMON_H */ diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index 00a255d5f5..c8d45f46fe 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -26,10 +26,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := edminiv2.o +COBJS := edminiv2.o ../common/common.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index ee26893328..c1a01bc613 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,7 +27,6 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> -#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -96,33 +95,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); + mv_phy_88e1116_init("egiga0"); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/pleb2/Makefile b/board/LaCie/net2big_v2/Makefile index bc296107bf..fbae48ef24 100644 --- a/board/pleb2/Makefile +++ b/board/LaCie/net2big_v2/Makefile @@ -1,7 +1,10 @@ - # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> # # See file CREDITS for list of people who contributed to this # project. @@ -13,26 +16,31 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := pleb2.o flash.o +COBJS := $(BOARD).o ../common/common.o -SRCS := $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +distclean: clean + rm -f $(LIB) core *.bak .depend ######################################################################### diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg new file mode 100644 index 0000000000..8d9f15328d --- /dev/null +++ b/board/LaCie/net2big_v2/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000C30 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38743000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A32 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000662 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000044 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c new file mode 100644 index 0000000000..d0b4adffc0 --- /dev/null +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "net2big_v2.h" +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* GPIO configuration */ + kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse alarm */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA HDD1 power */ + MPP17_GPIO, /* SATA HDD2 power */ + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP24_GPIO, /* USB mode select */ + MPP26_GPIO, /* USB device vbus */ + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* GPIO extension ALE */ + MPP34_GPIO, /* Rear Push button 0=on 1=off */ + MPP35_GPIO, /* Inhibit switch power-off */ + MPP36_GPIO, /* SATA HDD1 presence */ + MPP37_GPIO, /* SATA HDD2 presence */ + MPP40_GPIO, /* eSATA presence */ + MPP44_GPIO, /* GPIO extension (data 0) */ + MPP45_GPIO, /* GPIO extension (data 1) */ + MPP46_GPIO, /* GPIO extension (data 2) */ + MPP47_GPIO, /* GPIO extension (addr 0) */ + MPP48_GPIO, /* GPIO extension (addr 1) */ + MPP49_GPIO, /* GPIO extension (addr 2) */ + 0 + }; + + kirkwood_mpp_conf(kwmpp_config); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1116_init("egiga0"); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO push button status */ +static int +do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_push_button, + "Return GPIO push button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/net2big_v2/net2big_v2.h index 88e62b229c..f9778f4f0c 100644 --- a/board/LaCie/edminiv2/edminiv2.h +++ b/board/LaCie/net2big_v2/net2big_v2.h @@ -1,9 +1,7 @@ /* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> * - * Based on sheevaplug.h: + * Based on Kirkwood support: * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Written-by: Prafulla Wadaskar <prafulla@marvell.com> @@ -20,22 +18,18 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA */ -#ifndef __EDMINIV2_BASE_H -#define __EDMINIV2_BASE_H +#ifndef NET2BIG_V2_H +#define NET2BIG_V2_H + +/* GPIO configuration */ +#define NET2BIG_V2_OE_LOW 0x0600E000 +#define NET2BIG_V2_OE_HIGH 0x00000134 +#define NET2BIG_V2_OE_VAL_LOW 0x10030000 +#define NET2BIG_V2_OE_VAL_HIGH 0x00000000 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +/* Buttons */ +#define NET2BIG_V2_GPIO_PUSH_BUTTON 34 -#endif /* __EDMINIV2_BASE_H */ +#endif /* NET2BIG_V2_H */ diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile index d4a613fb6d..b43c3d3bfe 100644 --- a/board/LaCie/netspace_v2/Makefile +++ b/board/LaCie/netspace_v2/Makefile @@ -21,10 +21,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := netspace_v2.o +COBJS := $(BOARD).o ../common/common.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 7c4b15ec47..fbf020fde1 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -21,14 +21,14 @@ */ #include <common.h> -#include <miiphy.h> -#include <netdev.h> #include <command.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> + #include "netspace_v2.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -89,49 +89,29 @@ int board_init(void) return 0; } -void mv_phy_88e1116_init(char *name) +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) { - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __func__); - return; - } - if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __func__); - return; - } - - debug("88E1116 Initialized on %s\n", name); +#endif + return 0; } +#endif +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) /* Configure and initialize PHY */ void reset_phy(void) { mv_phy_88e1116_init("egiga0"); } +#endif +#if defined(CONFIG_KIRKWOOD_GPIO) /* Return GPIO button status */ static int do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -141,3 +121,4 @@ do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(button, 1, 1, do_read_button, "Return GPIO button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h index 3f3d51ccd7..34e492c77e 100644 --- a/board/LaCie/netspace_v2/netspace_v2.h +++ b/board/LaCie/netspace_v2/netspace_v2.h @@ -31,12 +31,4 @@ #define NETSPACE_V2_GPIO_BUTTON 32 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - #endif /* NETSPACE_V2_H */ diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 1351358298..f438c150a3 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -36,21 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - static struct davinci_timer *timer = (struct davinci_timer *)DAVINCI_TIMER3_BASE; diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 26e34e99d7..f360323c9b 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/pxa.h> #include <serial.h> #include <asm/io.h> #include <spartan3.h> @@ -57,10 +58,9 @@ struct serial_device *default_serial_console(void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile deleted file mode 100644 index cf4742ee17..0000000000 --- a/board/cerf250/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cerf250.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c deleted file mode 100644 index 043afea265..0000000000 --- a/board/cerf250/cerf250.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of cerf PXA Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c deleted file mode 100644 index e1e7807bc1..0000000000 --- a/board/cerf250/flash.c +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c deleted file mode 100644 index 2bbf2d532d..0000000000 --- a/board/cradle/cradle.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/pxa-regs.h> -#include <common.h> -#include <netdev.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ -void set_led (int led, int color); -void error_code_halt (int code); -int init_sio (int led, unsigned long base); -inline void cradle_outb (unsigned short val, unsigned long base, - unsigned long reg); -inline unsigned char cradle_inb (unsigned long base, unsigned long reg); -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -void -/**********************************************************/ -error_code_halt (int code) -/**********************************************************/ -{ - while (1) { - led_code (code, RED); - sleep (1); - led_code (0, OFF); - sleep (1); - } -} - -void -/**********************************************************/ -led_code (int code, int color) -/**********************************************************/ -{ - int i; - - code &= 0xf; /* only 4 leds */ - - for (i = 0; i < 4; i++) { - if (code & (1 << i)) { - set_led (i, color); - } else { - set_led (i, OFF); - } - } -} - -void -/**********************************************************/ -set_led (int led, int color) -/**********************************************************/ -{ - int shift = led * 2; - unsigned long mask = 0x3 << shift; - - writel(mask, GPCR2); /* clear bits */ - writel((color << shift), GPSR2); /* set bits */ - udelay (5000); -} - -inline void -/**********************************************************/ -cradle_outb (unsigned short val, unsigned long base, unsigned long reg) -/**********************************************************/ -{ - *(volatile unsigned short *) (base + (reg * 2)) = val; -} - -inline unsigned char -/**********************************************************/ -cradle_inb (unsigned long base, unsigned long reg) -/**********************************************************/ -{ - unsigned short val; - - val = *(volatile unsigned short *) (base + (reg * 2)); - return (val & 0xff); -} - -int -/**********************************************************/ -init_sio (int led, unsigned long base) -/**********************************************************/ -{ - unsigned char val; - - set_led (led, YELLOW); - val = cradle_inb (base, CRADLE_SIO_INDEX); - val = cradle_inb (base, CRADLE_SIO_INDEX); - if (val != 0) { - set_led (led, RED); - return -1; - } - - /* map SCC2 to COM1 */ - cradle_outb (0x01, base, CRADLE_SIO_INDEX); - cradle_outb (0x00, base, CRADLE_SIO_DATA); - - /* enable SCC2 extended regs */ - cradle_outb (0x40, base, CRADLE_SIO_INDEX); - cradle_outb (0xa0, base, CRADLE_SIO_DATA); - - /* enable SCC2 clock multiplier */ - cradle_outb (0x51, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* enable SCC2 */ - cradle_outb (0x00, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* map SCC2 DMA to channel 0 */ - cradle_outb (0x4f, base, CRADLE_SIO_INDEX); - cradle_outb (0x09, base, CRADLE_SIO_DATA); - - /* read ID from SIO to check operation */ - cradle_outb (0xe4, base, 0x3f8 + 0x3); - val = cradle_inb (base, 0x3f8 + 0x0); - if ((val & 0xf0) != 0x20) { - set_led (led, RED); - /* disable SCC2 */ - cradle_outb (0, base, CRADLE_SIO_INDEX); - cradle_outb (0, base, CRADLE_SIO_DATA); - return -1; - } - /* set back to bank 0 */ - cradle_outb (0, base, 0x3f8 + 0x3); - set_led (led, GREEN); - return 0; -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_late_init (void) -/**********************************************************/ -{ - return (0); -} - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - led_code (0xf, YELLOW); - - /* arch number of HHP Cradle */ - gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Init SIOs to enable SCC2 */ - udelay (100000); /* delay makes it look neat */ - init_sio (0, CRADLE_SIO1_PHYS); - udelay (100000); - init_sio (1, CRADLE_SIO2_PHYS); - udelay (100000); - init_sio (2, CRADLE_SIO3_PHYS); - udelay (100000); - set_led (3, GREEN); - - return 1; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cradle/flash.c b/board/cradle/flash.c deleted file mode 100644 index 160178207d..0000000000 --- a/board/cradle/flash.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define FLASH_BANK_SIZE 0x400000 -#define MAIN_SECT_SIZE 0x20000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i, j; - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): - printf ("28F320J3A (32Mbit)\n"); - break; - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while ((*addr & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((val = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; - goto outahere; - } - } - - if (val & 0x1A) { /* check for error */ - printf ("\nFlash write error %02x at address %08lx\n", - (int) val, (unsigned long) dest); - if (val & (1 << 3)) { - printf ("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (val & (1 << 1)) { - printf ("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if (val & (1 << 4)) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0xFF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/davinci/common/davinci_pinmux.c b/board/davinci/common/davinci_pinmux.c deleted file mode 100644 index ce58f71886..0000000000 --- a/board/davinci/common/davinci_pinmux.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * DaVinci pinmux functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> - -/* - * Change the setting of a pin multiplexer field. - * - * Takes an array of pinmux settings similar to: - * - * struct pinmux_config uart_pins[] = { - * { &davinci_syscfg_regs->pinmux[8], 2, 7 }, - * { &davinci_syscfg_regs->pinmux[9], 2, 0 } - * }; - * - * Stepping through the array, each pinmux[n] register has the given value - * set in the pin mux field specified. - * - * The number of pins in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Returns 0 if all field numbers and values are in the correct range, - * else returns -1. - */ -int davinci_configure_pin_mux(const struct pinmux_config *pins, - const int n_pins) -{ - int i; - - /* check for invalid pinmux values */ - for (i = 0; i < n_pins; i++) { - if (pins[i].field >= PIN_MUX_NUM_FIELDS || - (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0) - return -1; - } - - /* configure the pinmuxes */ - for (i = 0; i < n_pins; i++) { - const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; - const unsigned int value = pins[i].value << offset; - const unsigned int mask = PIN_MUX_FIELD_MASK << offset; - const dv_reg *mux = pins[i].mux; - - writel(value | (readl(mux) & (~mask)), mux); - } - - return 0; -} - -/* - * Configure multiple pinmux resources. - * - * Takes an pinmux_resource array of pinmux_config and pin counts: - * - * const struct pinmux_resource pinmuxes[] = { - * PINMUX_ITEM(uart_pins), - * PINMUX_ITEM(i2c_pins), - * }; - * - * The number of items in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Each item entry is configured in the defined order. If configuration - * of any item fails, -1 is returned and none of the following items are - * configured. On success, 0 is returned. - */ -int davinci_configure_pin_mux_items(const struct pinmux_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) { - if (davinci_configure_pin_mux(item[i].pins, - item[i].n_pins) != 0) - return -1; - } - - return 0; -} diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c deleted file mode 100644 index 5aa7605f00..0000000000 --- a/board/davinci/common/misc.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Miscelaneous DaVinci functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} -#endif - -#ifdef CONFIG_DRIVER_TI_EMAC - -/* Read ethernet MAC address from EEPROM for DVEVM compatible boards. - * Returns 1 if found, 0 otherwise. - */ -int dvevm_read_mac_address(uint8_t *buf) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uint8_t *) &buf[0], 6)) - goto i2cerr; - - /* Check that MAC address is valid. */ - if (!is_valid_ether_addr(buf)) - goto err; - - return 1; /* Found */ - -i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); -err: -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ - - return 0; -} - -/* - * Set the mii mode as MII or RMII - */ -#if defined(CONFIG_SOC_DA8XX) -void davinci_emac_mii_mode_sel(int mode_sel) -{ - int val; - - val = readl(&davinci_syscfg_regs->cfgchip3); - if (mode_sel == 0) - val &= ~(1 << 8); - else - val |= (1 << 8); - writel(val, &davinci_syscfg_regs->cfgchip3); -} -#endif -/* - * If there is no MAC address in the environment, then it will be initialized - * (silently) from the value in the EEPROM. - */ -void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) -{ - uint8_t env_enetaddr[6]; - - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { - /* There is no MAC address in the environment, so we initialize - * it from the value in the EEPROM. */ - debug("### Setting environment from EEPROM MAC address = " - "\"%pM\"\n", - env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); - } -} - -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#if defined(CONFIG_SOC_DA8XX) -#ifndef CONFIG_USE_IRQ -void irq_init(void) -{ - /* - * Mask all IRQs by clearing the global enable and setting - * the enable clear for all the 90 interrupts. - */ - - writel(0, &davinci_aintc_regs->ger); - - writel(0, &davinci_aintc_regs->hier); - - writel(0xffffffff, &davinci_aintc_regs->ecr1); - writel(0xffffffff, &davinci_aintc_regs->ecr2); - writel(0xffffffff, &davinci_aintc_regs->ecr3); -} -#endif - -/* - * Enable PSC for various peripherals. - */ -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) - lpsc_on(item[i].lpsc_no); - - return 0; -} -#endif diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 2021e73242..c45c94b4c0 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -46,8 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - /* SPI0 pin muxer settings */ static const struct pinmux_config spi0_pins[] = { { pinmux(7), 1, 3 }, diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e0a3bbefcf..9c0eadea90 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -28,137 +28,14 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> #include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi1_pins[] = { - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 5 } -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - #ifdef CONFIG_DRIVER_TI_EMAC -static const struct pinmux_config emac_pins[] = { -#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII - { pinmux(14), 8, 2 }, - { pinmux(14), 8, 3 }, - { pinmux(14), 8, 4 }, - { pinmux(14), 8, 5 }, - { pinmux(14), 8, 6 }, - { pinmux(14), 8, 7 }, - { pinmux(15), 8, 1 }, -#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 }, - { pinmux(3), 8, 0 }, - { pinmux(3), 8, 1 }, - { pinmux(3), 8, 2 }, - { pinmux(3), 8, 3 }, - { pinmux(3), 8, 4 }, - { pinmux(3), 8, 5 }, - { pinmux(3), 8, 6 }, - { pinmux(3), 8, 7 }, -#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 2 }, - { pinmux(4), 2, 3 } -}; - -#ifdef CONFIG_NAND_DAVINCI -const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; -#elif defined(CONFIG_USE_NOR) -/* NOR pin muxer settings */ -const struct pinmux_config nor_pins[] = { - /* GP0[11] is required for NOR to work on Rev 3 EVMs */ - { pinmux(0), 8, 4 }, /* GP0[11] */ - { pinmux(5), 1, 6 }, - { pinmux(6), 1, 6 }, - { pinmux(7), 1, 0 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(8), 1, 0 }, - { pinmux(8), 1, 1 }, - { pinmux(8), 1, 2 }, - { pinmux(8), 1, 3 }, - { pinmux(8), 1, 4 }, - { pinmux(8), 1, 5 }, - { pinmux(8), 1, 6 }, - { pinmux(8), 1, 7 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(10), 1, 0 }, - { pinmux(10), 1, 1 }, - { pinmux(10), 1, 2 }, - { pinmux(10), 1, 3 }, - { pinmux(10), 1, 4 }, - { pinmux(10), 1, 5 }, - { pinmux(10), 1, 6 }, - { pinmux(10), 1, 7 }, - { pinmux(11), 1, 0 }, - { pinmux(11), 1, 1 }, - { pinmux(11), 1, 2 }, - { pinmux(11), 1, 3 }, - { pinmux(11), 1, 4 }, - { pinmux(11), 1, 5 }, - { pinmux(11), 1, 6 }, - { pinmux(11), 1, 7 }, - { pinmux(12), 1, 0 }, - { pinmux(12), 1, 1 }, - { pinmux(12), 1, 2 }, - { pinmux(12), 1, 3 }, - { pinmux(12), 1, 4 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 }, - { pinmux(12), 1, 7 } -}; -#endif - #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII #define HAS_RMII 1 #else @@ -224,17 +101,38 @@ int misc_init_r(void) return 0; } +static const struct pinmux_config gpio_pins[] = { +#ifdef CONFIG_USE_NOR + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif +}; + static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif #ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi1_pins), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), #endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(i2c0_pins), #ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(nand_pins), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), #elif defined(CONFIG_USE_NOR) - PINMUX_ITEM(nor_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_nor), #endif + PINMUX_ITEM(gpio_pins), }; static const struct lpsc_resource lpsc[] = { @@ -249,6 +147,8 @@ static const struct lpsc_resource lpsc[] = { #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 #endif +#define REV_AM18X_EVM 0x100 + /* * get_board_rev() - setup to pass kernel board revision information * Returns: @@ -274,7 +174,9 @@ u32 get_board_rev(void) rev = 2; else if (maxcpuclk >= 372000000) rev = 1; - +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif return rev; } @@ -346,9 +248,6 @@ int board_init(void) #endif #ifdef CONFIG_DRIVER_TI_EMAC - if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) - return 1; - davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index 32b17ce7f4..df97963f6d 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -27,63 +27,20 @@ #include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/arch/pinmux_defs.h> #include <ns16550.h> #include <nand.h> DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - -static const struct pinmux_config mii_pins[] = { - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 } -}; - -static const struct pinmux_config mdio_pins[] = { - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -static const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; - -static const struct pinmux_config uart2_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - static const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(mii_pins), - PINMUX_ITEM(mdio_pins), - PINMUX_ITEM(i2c_pins), - PINMUX_ITEM(nand_pins), - PINMUX_ITEM(uart2_pins), + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), }; static const struct lpsc_resource lpsc[] = { diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 720a3607a7..9b6c4c047d 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -40,8 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - static const struct da8xx_panel lcd_panel = { /* Casio COM57H531x */ .name = "Casio_COM57H531x", diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index b78bf6ccba..3d2cc1a7f1 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -226,7 +226,7 @@ static void power_init(void) /* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; pmic_reg_write(p, REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ @@ -260,18 +260,23 @@ static void power_init(void) (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); pmic_reg_write(p, REG_SW_5, val); - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; pmic_reg_write(p, REG_SETTING_1, val); + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; pmic_reg_write(p, REG_MODE_1, val); @@ -279,7 +284,7 @@ static void power_init(void) /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; + VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); pmic_reg_read(p, REG_POWER_CTL2, &val); diff --git a/board/cradle/Makefile b/board/egnite/ethernut5/Makefile index bdc91d89f7..8dc85d2b42 100644 --- a/board/cradle/Makefile +++ b/board/egnite/ethernut5/Makefile @@ -1,7 +1,10 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2003-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# (C) Copyright 2010 +# egnite GmbH +# # See file CREDITS for list of people who contributed to this # project. # @@ -12,7 +15,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -25,13 +28,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cradle.o flash.o +COBJS-y += $(BOARD).o +COBJS-y += $(BOARD)_pwrman.o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ######################################################################### diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c new file mode 100644 index 0000000000..e42e91e00b --- /dev/null +++ b/board/egnite/ethernut5/ethernut5.c @@ -0,0 +1,270 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * (C) Copyright 2010 + * Ole Reinhardt <ole.reinhardt@thermotemp.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 general board support + * + * Ethernut is an open source hardware and software project for + * embedded Ethernet devices. Hardware layouts and CAD files are + * freely available under BSD-like license. + * + * Ethernut 5 is the first member of the Ethernut board family + * with U-Boot and Linux support. This implementation is based + * on the original work done by Ole Reinhardt, but heavily modified + * to support additional features and the latest board revision 5.0F. + * + * Main board components are by default: + * + * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash + * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM + * 512 MBytes Micron MT29F4G08ABADA NAND Flash + * 4 MBytes Atmel AT45DB321D DataFlash + * SMSC LAN8710 Ethernet PHY + * Atmel ATmega168 MCU used for power management + * Linear Technology LTC4411 PoE controller + * + * U-Boot relevant board interfaces are: + * + * 100 Mbit Ethernet with IEEE 802.3af PoE + * RS-232 serial port + * USB host and device + * MMC/SD-Card slot + * Expansion port with I2C, SPI and more... + * + * Typically the U-Boot image is loaded from serial DataFlash into + * SDRAM by the samboot boot loader, which is located in internal + * NOR Flash and provides all essential initializations like CPU + * and peripheral clocks and, of course, the SDRAM configuration. + * + * For testing purposes it is also possibly to directly transfer + * the image into SDRAM via JTAG. A tested configuration exists + * for the Turtelizer 2 hardware dongle and the OpenOCD software. + * In this case the latter will do the basic hardware configuration + * via its reset-init script. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <spi.h> +#include <dataflash.h> +#include <mmc.h> + +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +#include "ethernut5_pwrman.h" + +DECLARE_GLOBAL_DATA_PTR; + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0} +}; + +/* + * In fact we have 7 partitions, but u-boot supports 5 only. This is + * no big deal, because the first partition is reserved for applications + * and the last one is used by Nut/OS. Both need not to be visible here. + */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" }, + { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" }, + { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" }, + { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" }, + { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" } +}; + +/* + * This is called last during early initialization. Most of the basic + * hardware interfaces are up and running. + * + * The SDRAM hardware has been configured by the first stage boot loader. + * We only need to announce its size, using u-boot's memory check. + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_CMD_NAND +static void ethernut5_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + +#ifdef CONFIG_SYS_NAND_READY_PIN + /* Ready pin is optional. */ + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +/* + * This is called first during late initialization. + */ +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + /* Set adress of boot parameters. */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Initialize UARTs and power management. */ + at91_seriald_hw_init(); + ethernut5_power_init(); +#ifdef CONFIG_CMD_NAND + ethernut5_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif + return 0; +} + +#ifdef CONFIG_MACB +/* + * This is optionally called last during late initialization. + */ +int board_eth_init(bd_t *bis) +{ + const char *devname; + unsigned short mode; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable on-chip EMAC clock. */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + /* Need to reset PHY via power management. */ + ethernut5_phy_reset(); + /* Set peripheral pins. */ + at91_macb_hw_init(); + /* Basic EMAC initialization. */ + if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID)) + return -1; + /* + * Early board revisions have a pull-down at the PHY's MODE0 + * strap pin, which forces the PHY into power down. Here we + * switch to all-capable mode. + */ + devname = miiphy_get_current_dev(); + if (miiphy_read(devname, 0, 18, &mode) == 0) { + /* Set mode[2:0] to 0b111. */ + mode |= 0x00E0; + miiphy_write(devname, 0, 18, mode); + /* Soft reset overrides strap pins. */ + miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); + } + /* Sync environment with network devices, needed for nfsroot. */ + return eth_init(gd->bd); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable MCI clock. */ + writel(1 << ATMEL_ID_MCI, &pmc->pcer); + /* Initialize MCI hardware. */ + at91_mci_hw_init(); + /* Register the device. */ + return atmel_mci_init((void *)ATMEL_BASE_MCI); +} + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + *cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; + return 0; +} +#endif + +#ifdef CONFIG_ATMEL_SPI +/* + * Note, that u-boot uses different code for SPI bus access. While + * memory routines use automatic chip select control, the serial + * flash support requires 'manual' GPIO control. Thus, we switch + * modes. + */ +void spi_cs_activate(struct spi_slave *slave) +{ + /* Enable NPCS0 in GPIO mode. This disables peripheral control. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Disable NPCS0 in GPIO mode. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + /* Switch back to peripheral chip select control. */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} +#endif diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c new file mode 100644 index 0000000000..4b00038457 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * This board may be supplied via USB, IEEE 802.3af PoE or an + * auxiliary DC input. An on-board ATmega168 microcontroller, + * the so called power management controller or PMC, is used + * to select the supply source and to switch on and off certain + * energy consuming board components. This allows to reduce the + * total stand-by consumption to less than 70mW. + * + * The main CPU communicates with the PMC via I2C. When + * CONFIG_CMD_BSP is defined in the board configuration file, + * then the board specific command 'pwrman' becomes available, + * which allows to manually deal with the PMC. + * + * Two distinct registers are provided by the PMC for enabling + * and disabling specific features. This avoids the often seen + * read-modify-write cycle or shadow register requirement. + * Additional registers are available to query the board + * status and temperature, the auxiliary voltage and to control + * the green user LED that is integrated in the reset switch. + * + * Note, that the AVR firmware of the PMC is released under BSDL. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <i2c.h> + +#include "ethernut5_pwrman.h" + +/* PMC firmware version */ +static int pwrman_major; +static int pwrman_minor; + +/* + * Enable Ethernut 5 power management. + * + * This function must be called during board initialization. + * While we are using u-boot's I2C subsystem, it may be required + * to enable the serial port before calling this function, + * in particular when debugging is enabled. + * + * If board specific commands are not available, we will activate + * all board components. + */ +void ethernut5_power_init(void) +{ + pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS); + pwrman_major = pwrman_minor >> 4; + pwrman_minor &= 15; + +#ifndef CONFIG_CMD_BSP + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major == 2) { + /* Without board specific commands we enable all features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + } +#endif +} + +/* + * Reset Ethernet PHY. + * + * This function allows the re-configure the PHY after + * changing its strap pins. + */ +void ethernut5_phy_reset(void) +{ + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major != 2) + return; + + /* + * Make sure that the Ethernet clock is enabled and the PHY reset + * is disabled for at least 100 us. + */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + udelay(100); + + /* + * LAN8710 strap pins are + * PA14 => PHY MODE0 + * PA15 => PHY MODE1 + * PA17 => PHY MODE2 => 111b all capable + * PA18 => PHY ADDR0 => 0b + */ + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); + at91_set_pio_input(AT91_PIO_PORTA, 15, 1); + at91_set_pio_input(AT91_PIO_PORTA, 17, 1); + at91_set_pio_input(AT91_PIO_PORTA, 18, 0); + + /* Activate PHY reset for 100 us. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST); + udelay(100); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); +} + +/* + * Output the firmware version we got during initialization. + */ +void ethernut5_print_version(void) +{ + printf("%u.%u\n", pwrman_major, pwrman_minor); +} + +/* + * All code below this point is optional and implements + * the 'pwrman' command. + */ +#ifdef CONFIG_CMD_BSP + +/* Human readable names of PMC features */ +char *pwrman_feat[8] = { + "board", "vbin", "vbout", "mmc", + "rs232", "ethclk", "ethrst", "wakeup" +}; + +/* + * Print all feature names, that have its related flags enabled. + */ +static void print_flagged_features(u8 flags) +{ + int i; + + for (i = 0; i < 8; i++) { + if (flags & (1 << i)) + printf("%s ", pwrman_feat[i]); + } +} + +/* + * Return flags of a given list of feature names. + * + * The function stops at the first unknown list entry and + * returns the number of detected names as a function result. + */ +static int feature_flags(char * const names[], int num, u8 *flags) +{ + int i, j; + + *flags = 0; + for (i = 0; i < num; i++) { + for (j = 0; j < 8; j++) { + if (strcmp(pwrman_feat[j], names[i]) == 0) { + *flags |= 1 << j; + break; + } + } + if (j > 7) + break; + } + return i; +} + +void ethernut5_print_power(void) +{ + u8 flags; + int i; + + flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA); + for (i = 0; i < 2; i++) { + if (flags) { + print_flagged_features(flags); + printf("%s\n", i ? "off" : "on"); + } + flags = ~flags; + } +} + +void ethernut5_print_celsius(void) +{ + int val; + + /* Read ADC value from LM50 and return Celsius degrees. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); + val *= 5000; /* 100mV/degree with 5V reference */ + val += 128; /* 8 bit resolution */ + val /= 256; + val -= 450; /* Celsius offset, still x10 */ + /* Output full degrees. */ + printf("%d\n", (val + 5) / 10); +} + +void ethernut5_print_voltage(void) +{ + int val; + + /* Read ADC value from divider and return voltage. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); + /* Resistors are 100k and 12.1k */ + val += 5; + val *= 180948; + val /= 100000; + val++; + /* Calculation was done in 0.1V units. */ + printf("%d\n", (val + 5) / 10); +} + +/* + * Process the board specific 'pwrman' command. + */ +int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 val; + int i; + + if (argc == 1) { + ethernut5_print_power(); + } else if (argc == 2 && strcmp(argv[1], "reset") == 0) { + at91_set_pio_output(AT91_PIO_PORTB, 8, 1); + udelay(100); + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); + udelay(100000); + } else if (argc == 2 && strcmp(argv[1], "temp") == 0) { + ethernut5_print_celsius(); + } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) { + ethernut5_print_voltage(); + } else if (argc == 2 && strcmp(argv[1], "version") == 0) { + ethernut5_print_version(); + } else if (strcmp(argv[1], "led") == 0) { + /* Control the green status LED. Blink frequency unit + ** is 0.1s, very roughly. */ + if (argc == 2) { + /* No more arguments, output current settings. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL); + printf("led %u %u\n", val >> 4, val & 15); + } else { + /* First argument specifies the on-time. */ + val = (u8) simple_strtoul(argv[2], NULL, 0); + val <<= 4; + if (argc > 3) { + /* Second argument specifies the off-time. */ + val |= (u8) (simple_strtoul(argv[3], NULL, 0) + & 15); + } + /* Update the LED control register. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val); + } + } else { + /* We expect a list of features followed an optional status. */ + argc--; + i = feature_flags(&argv[1], argc, &val); + if (argc == i) { + /* We got a list only, print status. */ + val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA); + if (val) { + if (i > 1) + print_flagged_features(val); + printf("active\n"); + } else { + printf("inactive\n"); + } + } else { + /* More arguments. */ + if (i == 0) { + /* No given feature, use despensibles. */ + val = PWRMAN_DISPENSIBLE; + } + if (strcmp(argv[i + 1], "on") == 0) { + /* Enable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, + val); + } else if (strcmp(argv[i + 1], "off") == 0) { + /* Disable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, + val); + } else { + printf("Bad parameter %s\n", argv[i + 1]); + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD( + pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman, + "power management", + "- print settings\n" + "pwrman feature ...\n" + " - print status\n" + "pwrman [feature ...] on|off\n" + " - enable/disable specified or all dispensible features\n" + "pwrman led [on-time [off-time]]\n" + " - print or set led blink timer\n" + "pwrman temp\n" + " - print board temperature (Celsius)\n" + "pwrman vaux\n" + " - print auxiliary input voltage\n" + "pwrman reset\n" + " - reset power management controller\n" + "pwrman version\n" + " - print firmware version\n" + "\n" + " features, (*)=dispensible:\n" + " board - 1.8V and 3.3V supply\n" + " vbin - supply via USB device connector\n" + " vbout - USB host connector supply(*)\n" + " mmc - MMC slot supply(*)\n" + " rs232 - RS232 driver\n" + " ethclk - Ethernet PHY clock(*)\n" + " ethrst - Ethernet PHY reset\n" + " wakeup - RTC alarm" +); +#endif /* CONFIG_CMD_BSP */ diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h new file mode 100644 index 0000000000..054188408a --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +/* I2C address of the PMC */ +#define PWRMAN_I2C_ADDR 0x22 + +/* PMC registers */ +#define PWRMAN_REG_VERS 0 /* Version register */ +#define PWRMAN_REG_STA 1 /* Feature status register */ +#define PWRMAN_REG_ENA 2 /* Feature enable register */ +#define PWRMAN_REG_DIS 3 /* Feature disable register */ +#define PWRMAN_REG_TEMP 4 /* Board temperature */ +#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */ +#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */ + +/* Feature flags used in status, enable and disable registers */ +#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */ +#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */ +#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */ +#define PWRMAN_MMC 0x08 /* Memory card supply */ +#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */ +#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */ +#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */ +#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */ + +/* Features, which are not essential to keep u-boot alive */ +#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK) + +/* Enable Ethernut 5 power management. */ +extern void ethernut5_power_init(void); + +/* Reset Ethernet PHY. */ +extern void ethernut5_phy_reset(void); + +extern void ethernut5_print_version(void); + +#ifdef CONFIG_CMD_BSP +extern void ethernut5_print_power(void); +extern void ethernut5_print_celsius(void); +extern void ethernut5_print_voltage(void); +#endif diff --git a/board/davinci/common/Makefile b/board/enbw/enbw_cmc/Makefile index 9d7b164238..cd1f0d4ed8 100644 --- a/board/davinci/common/Makefile +++ b/board/enbw/enbw_cmc/Makefile @@ -1,7 +1,9 @@ # -# (C) Copyright 2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# # See file CREDITS for list of people who contributed to this # project. # @@ -23,13 +25,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o +LIB = $(obj)lib$(BOARD).o -COBJS := misc.o davinci_pinmux.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c new file mode 100644 index 0000000000..5cd5357bcd --- /dev/null +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <hwconfig.h> +#include <i2c.h> +#include <malloc.h> +#include <miiphy.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/da850_lowlevel.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdmmc_defs.h> +#include <asm/arch/timer_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, + { DAVINCI_LPSC_SPI1 }, + { DAVINCI_LPSC_ARM_RAM_ROM }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_EMAC }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_GPIO }, + { DAVINCI_LPSC_DDR_EMIF }, + { DAVINCI_LPSC_UART1 }, + { DAVINCI_LPSC_UART2 }, + { DAVINCI_LPSC_MMC_SD1 }, + { DAVINCI_LPSC_USB20 }, + { DAVINCI_LPSC_USB11 }, +}; + +static const struct pinmux_config enbw_pins[] = { + { pinmux(0), 8, 0 }, + { pinmux(0), 8, 1 }, + { pinmux(0), 8, 2 }, + { pinmux(0), 8, 3 }, + { pinmux(0), 8, 4 }, + { pinmux(0), 8, 5 }, + { pinmux(1), 4, 0 }, + { pinmux(1), 8, 1 }, + { pinmux(1), 8, 2 }, + { pinmux(1), 8, 3 }, + { pinmux(1), 8, 4 }, + { pinmux(1), 8, 5 }, + { pinmux(1), 8, 6 }, + { pinmux(1), 4, 7 }, + { pinmux(2), 8, 0 }, + { pinmux(5), 1, 0 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 7 }, + { pinmux(6), 1, 0 }, + { pinmux(6), 1, 1 }, + { pinmux(6), 8, 2 }, + { pinmux(6), 8, 3 }, + { pinmux(6), 1, 4 }, + { pinmux(6), 8, 5 }, + { pinmux(6), 1, 7 }, + { pinmux(7), 8, 2 }, + { pinmux(7), 1, 3 }, + { pinmux(7), 1, 6 }, + { pinmux(7), 1, 7 }, + { pinmux(13), 8, 2 }, + { pinmux(13), 8, 3 }, + { pinmux(13), 8, 4 }, + { pinmux(13), 8, 5 }, + { pinmux(13), 8, 6 }, + { pinmux(13), 8, 7 }, + { pinmux(14), 8, 0 }, + { pinmux(14), 8, 1 }, + { pinmux(16), 8, 1 }, + { pinmux(16), 8, 2 }, + { pinmux(16), 8, 3 }, + { pinmux(16), 8, 4 }, + { pinmux(16), 8, 5 }, + { pinmux(16), 8, 6 }, + { pinmux(16), 8, 7 }, + { pinmux(17), 1, 0 }, + { pinmux(17), 1, 1 }, + { pinmux(17), 1, 2 }, + { pinmux(17), 8, 3 }, + { pinmux(17), 8, 4 }, + { pinmux(17), 8, 5 }, + { pinmux(17), 8, 6 }, + { pinmux(17), 8, 7 }, + { pinmux(18), 8, 0 }, + { pinmux(18), 8, 1 }, + { pinmux(18), 2, 2 }, + { pinmux(18), 2, 3 }, + { pinmux(18), 2, 4 }, + { pinmux(18), 8, 6 }, + { pinmux(18), 8, 7 }, + { pinmux(19), 8, 0 }, + { pinmux(19), 2, 1 }, + { pinmux(19), 2, 2 }, + { pinmux(19), 2, 3 }, + { pinmux(19), 2, 4 }, + { pinmux(19), 8, 5 }, + { pinmux(19), 8, 6 }, +}; + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(i2c0_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(emifa_pins_nor), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), + PINMUX_ITEM(uart1_pins_txrx), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(enbw_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +struct gpio_config { + char name[GPIO_NAME_SIZE]; + unsigned char bank; + unsigned char gpio; + unsigned char out; + unsigned char value; +}; + +static const struct gpio_config enbw_gpio_config[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 0 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 0 }, + { "LAN reset", 7, 15, 1, 1 }, + { "ena 11V PLC", 7, 14, 1, 0 }, + { "ena 1.5V PLC", 7, 13, 1, 0 }, + { "disable VBUS", 7, 12, 1, 1 }, + { "PLC reset", 6, 13, 1, 1 }, + { "LCM RS", 6, 12, 1, 0 }, + { "LCM R/W", 6, 11, 1, 0 }, + { "PLC pairing", 6, 10, 1, 1 }, + { "PLC MDIO CLK", 6, 9, 1, 0 }, + { "HK218", 6, 8, 1, 0 }, + { "HK218 Rx", 6, 1, 1, 1 }, + { "TPM reset", 6, 0, 1, 1 }, + { "LCM E", 2, 2, 1, 1 }, + { "PV-IF RxD ena", 0, 15, 1, 1 }, + { "LED1", 1, 15, 1, 1 }, + { "LED2", 0, 1, 1, 1 }, + { "LED3", 0, 2, 1, 1 }, + { "LED4", 0, 3, 1, 1 }, + { "LED5", 0, 4, 1, 1 }, + { "LED6", 0, 5, 1, 0 }, + { "LED7", 0, 6, 1, 0 }, + { "LED8", 0, 14, 1, 0 }, + { "USER1", 0, 12, 0, 0 }, + { "USER2", 0, 13, 0, 0 }, +}; + +#define PHY_POWER 0x0800 + +static void enbw_cmc_switch(int port, int on) +{ + const char *devname; + unsigned char phyaddr = 3; + unsigned char reg = 0; + unsigned short data; + + if (port == 1) + phyaddr = 2; + + devname = miiphy_get_current_dev(); + if (!devname) { + printf("Error: no mii device\n"); + return; + } + if (miiphy_read(devname, phyaddr, reg, &data) != 0) { + printf("Error reading from the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } + + if (on) + data &= ~PHY_POWER; + else + data |= PHY_POWER; + + if (miiphy_write(devname, phyaddr, reg, data) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } +} + +int board_init(void) +{ + int i, ret; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { + int gpio = enbw_gpio_config[i].bank * 16 + + enbw_gpio_config[i].gpio; + + ret = gpio_request(gpio, enbw_gpio_config[i].name); + if (ret) { + printf("%s: Could not get %s gpio\n", __func__, + enbw_gpio_config[i].name); + return -1; + } + + if (enbw_gpio_config[i].out) + gpio_direction_output(gpio, + enbw_gpio_config[i].value); + else + gpio_direction_input(gpio); + } + + /* setup the SUSPSRC for ARM to control emulation suspend */ + clrbits_le32(&davinci_syscfg_regs->suspsrc, + (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2)); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(0); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + if (hwconfig_subarg_cmp("switch", "lan", "on")) + /* Switch port lan on */ + enbw_cmc_switch(1, 1); + else + enbw_cmc_switch(1, 0); + + if (hwconfig_subarg_cmp("switch", "pwl", "on")) + /* Switch port pwl on */ + enbw_cmc_switch(2, 1); + else + enbw_cmc_switch(2, 0); + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#ifdef CONFIG_PREBOOT +static uchar kbd_magic_prefix[] = "key_magic_"; +static uchar kbd_command_prefix[] = "key_cmd_"; + +struct kbd_data_t { + char s1; +}; + +struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data) +{ + /* read SW1 + SW2 */ + kbd_data->s1 = gpio_get_value(12) + + (gpio_get_value(13) << 1); + return kbd_data; +} + +static int compare_magic(const struct kbd_data_t *kbd_data, char *str) +{ + char s1 = str[0]; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s1) + return -1; + + return 0; +} + +static char *key_match(const struct kbd_data_t *kbd_data) +{ + char magic[sizeof(kbd_magic_prefix) + 1]; + char *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + kbd_magic_keys = getenv("magic_keys"); + if (kbd_magic_keys == NULL) + kbd_magic_keys = ""; + + /* + * loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + + if (compare_magic(kbd_data, getenv(magic)) == 0) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + + return cmd; + } + } + + return NULL; +} +#endif /* CONFIG_PREBOOT */ + +int misc_init_r(void) +{ + char *s, buf[32]; +#ifdef CONFIG_PREBOOT + struct kbd_data_t kbd_data; + /* Decode keys */ + char *str = strdup(key_match(get_keys(&kbd_data))); + /* Set or delete definition */ + setenv("preboot", str); + free(str); +#endif /* CONFIG_PREBOOT */ + + /* count all restarts, and save this in an environment var */ + s = getenv("restartcount"); + + if (s) + sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1); + else + strcpy(buf, "1"); + + setenv("restartcount", buf); + saveenv(); + +#ifdef CONFIG_HW_WATCHDOG + davinci_hw_watchdog_enable(); +#endif + + return 0; +} + +struct cmc_led { + char name[20]; + unsigned char bank; + unsigned char gpio; +}; + +struct cmc_led led_table[] = { + {"led1", 1, 15}, + {"led2", 0, 1}, + {"led3", 0, 2}, + {"led4", 0, 3}, + {"led5", 0, 4}, + {"led6", 0, 5}, + {"led7", 0, 6}, + {"led8", 0, 14}, +}; + +static int cmc_get_led_state(struct cmc_led *led) +{ + int value; + int gpio = led->bank * 16 + led->gpio; + + value = gpio_get_value(gpio); + + return value; +} + +static int cmc_set_led_state(struct cmc_led *led, int state) +{ + int gpio = led->bank * 16 + led->gpio; + + gpio_set_value(gpio, state); + return 0; +} + +static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmc_led *led; + int found = 0; + int i = 0; + int only_print = 0; + int len = ARRAY_SIZE(led_table); + + if (argc < 2) + return cmd_usage(cmdtp); + + if (argc < 3) + only_print = 1; + + led = led_table; + while ((!found) && (i < len)) { + if (strcmp(argv[1], led->name) == 0) { + found = 1; + } else { + led++; + i++; + } + } + if (!found) + return cmd_usage(cmdtp); + + if (only_print) { + if (cmc_get_led_state(led)) + printf("on\n"); + else + printf("off\n"); + + return 0; + } + if (strcmp(argv[2], "on") == 0) + cmc_set_led_state(led, 1); + else + cmc_set_led_state(led, 0); + + return 0; +} + +U_BOOT_CMD(led, 3, 1, do_led, + "switch on/off board led", + "[name] [on/off]" +); + +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + davinci_hw_watchdog_reset(); +} +#endif + +#if defined(CONFIG_POST) +void arch_memory_failure_handle(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + int state = 1; + + /* + * if memor< failure blink with the LED 1,2 and 3 + * as we running from flash, we cannot use the gpio + * api here, so access the gpio pin direct through + * the gpio register. + */ + while (1) { + if (state) { + clrbits_le32(&gpio->out_data, 0x80000006); + state = 0; + } else { + setbits_le32(&gpio->out_data, 0x80000006); + state = 1; + } + udelay(500); + } +} +#endif + +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void bootcount_store(ulong a) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + out_be32(®->kick0r, RTC_KICK0R_WE); + out_be32(®->kick1r, RTC_KICK1R_WE); + out_be32(®->scratch0, a); + out_be32(®->scratch1, BOOTCOUNT_MAGIC); +} + +ulong bootcount_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + if (in_be32(®->scratch1) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32(®->scratch0); +} +#endif + +void board_gpio_init(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return; + + /* + * set LED (gpio Interface not usable here) + * set LED pins to output and state 0 + */ + clrbits_le32(&gpio->dir, 0x8000407e); + clrbits_le32(&gpio->out_data, 0x8000407e); + /* set LED 1 - 5 to state on */ + setbits_le32(&gpio->out_data, 0x8000001e); +} + +int board_late_init(void) +{ + cmc_set_led_state(&led_table[4], 0); + + return 0; +} + +void show_boot_progress(int val) +{ + switch (val) { + case 1: + cmc_set_led_state(&led_table[4], 1); + break; + case 4: + cmc_set_led_state(&led_table[4], 0); + break; + case 15: + cmc_set_led_state(&led_table[4], 1); + break; + } +} + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd1 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, + .input_clk = 228000000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID); + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd1); +} +#endif diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 37e6e4dbe8..e5b0929f65 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -265,6 +265,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(0); else diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index be32aee14f..e5a11429f2 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -87,6 +87,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(1); /*GPIO1_1*/ else diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 335661fd41..aa4a2c93dd 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -212,6 +212,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b4c7f33f93..3cf4195b5e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -140,6 +140,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 87fa7fa72e..55af4e480c 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -134,6 +134,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); *cd = gpio_get_value(77); /*GPIO3_13*/ return 0; diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index c0a006a7b3..0a105bf281 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -76,7 +76,7 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 3d74ef1321..68d746ccd0 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -31,46 +31,6 @@ const omap3_sysinfo sysinfo = { "AM3517EVM Board", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk deleted file mode 100644 index 71ec5d0b14..0000000000 --- a/board/logicpd/am3517evm/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Author: Vaibhav Hiremath <hvaibhav@ti.com> -# -# Based on ti/evm/config.mk -# -# Copyright (C) 2010 -# Texas Instruments Incorporated - http://www.ti.com/ -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index f791c5b904..437f944715 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -27,6 +27,7 @@ #include <common.h> #include <netdev.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,10 +57,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c index 5588fe732f..2f1ad20080 100644 --- a/board/palmld/palmld.c +++ b/board/palmld/palmld.c @@ -23,6 +23,7 @@ #include <command.h> #include <serial.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/pxa.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,10 +57,9 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index 25186aefa8..4adf152a4e 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -23,6 +23,7 @@ #include <command.h> #include <serial.h> #include <asm/io.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,10 +56,9 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c deleted file mode 100644 index 2406c5f4c0..0000000000 --- a/board/pleb2/flash.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include <environment.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static void flash_reset (flash_info_t * info); -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect (flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", - size_b); - } - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect (&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset (flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = - base + (info->size - 0x00004000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00006000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00008000) * (sizeof (FPW) / 2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MiB */ - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets ((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset (info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect (flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - start = get_timer(0); - last = 0; - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = - get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset (info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset (info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ -#ifdef CONFIG_SYS_LITTLE_ENDIAN - for (i = 0; i < sizeof (data); i++) { - data >>= 8; - if (i < bytes || i - bytes >= left) - data += (*((uchar *) addr + i)) << 24; - else - data += (*src++) << 24; - } -#else - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } -#endif - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd (info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel (info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c deleted file mode 100644 index 5a16cc76e8..0000000000 --- a/board/pleb2/pleb2.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PLEB2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 804d09c22b..877e8d9b2a 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -34,6 +34,7 @@ #include <netdev.h> #include <command.h> #include <asm/io.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -83,10 +84,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index cd5683d9be..436645a83f 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -75,7 +75,7 @@ void set_muxconf_regs(void) MUX_AM3517CRANE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h index 41db972727..71335a3fc5 100644 --- a/board/ti/am3517crane/am3517crane.h +++ b/board/ti/am3517crane/am3517crane.h @@ -30,45 +30,6 @@ const omap3_sysinfo sysinfo = { "CraneBoard", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk deleted file mode 100644 index c6a18b5106..0000000000 --- a/board/ti/am3517crane/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Author: Srinath R <srinath@mistralsolutions.com> -# -# Based on logicpd/am3517evm/config.mk -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9482c5eac7..6a457cbb5d 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -34,9 +34,11 @@ #include <status_led.h> #endif #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> @@ -135,6 +137,69 @@ int get_board_revision(void) return revision; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. If we can't identify it then + * we know it's an xM. To map the ID values please see nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_C4: + if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { + /* Beagleboard Rev C5, 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + } + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + if (pop_mfr == 0) { + /* 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } + break; + default: + /* Assume 128MB and Micron/165MHz timings to be safe */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_expansion_id * Description: This function checks for expansion board by checking I2C @@ -367,7 +432,7 @@ void set_muxconf_regs(void) MUX_BEAGLE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -476,6 +541,7 @@ int ehci_hcd_init(void) #endif /* CONFIG_USB_EHCI */ +#ifndef CONFIG_SPL_BUILD /* * This command returns the status of the user button on beagle xM * Input - none @@ -528,3 +594,4 @@ U_BOOT_CMD( "Return the status of the BeagleBoard USER button", "" ); +#endif diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk deleted file mode 100644 index cf055db623..0000000000 --- a/board/ti/beagle/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef094..0000000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, <www.ti.com> -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8c434633dd..8497aee6de 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -37,6 +37,7 @@ #include <asm/gpio.h> #include <i2c.h> #include <asm/mach-types.h> +#include <linux/mtd/nand.h> #include "evm.h" #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 @@ -119,6 +120,42 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. To map the ID values please see + * nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { + /* 256MB DDR */ + *mcfg = HYNIX_V_MCFG_200(256 << 20); + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + } else { + /* 128MB DDR */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + } + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -238,7 +275,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index c05170e336..2970ccd609 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -76,7 +76,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ }; diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index e1b853c4e9..9ae9e2c602 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -96,6 +96,13 @@ void set_muxconf_regs_non_essential(void) do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); + + if (omap_revision() < OMAP4460_ES1_0) { + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_non_essential_4430, + sizeof(wkup_padconf_array_non_essential_4430) / + sizeof(struct pad_conf_entry)); + } } #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 1c6e0eeb60..0a20968978 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -67,7 +67,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ }; @@ -275,4 +275,8 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ }; +const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { + {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ +}; + #endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff33c..b06aab6176 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. We have either one or two banks of 128MB DDR. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + + *mr = MICRON_V_MR_165; +} diff --git a/board/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile index 854b19bd99..854b19bd99 100644 --- a/board/colibri_pxa270/Makefile +++ b/board/toradex/colibri_pxa270/Makefile diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 191fb333e4..d72e5d6b5a 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -21,26 +21,20 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <asm/io.h> +#include <serial.h> DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ -extern struct serial_device serial_ffuart_device; -extern struct serial_device serial_btuart_device; -extern struct serial_device serial_stuart_device; - -struct serial_device *default_serial_console (void) +struct serial_device *default_serial_console(void) { return &serial_ffuart_device; } -int board_init (void) +int board_init(void) { /* We have RAM, disable cache */ dcache_disable(); @@ -55,20 +49,13 @@ int board_init (void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - #ifdef CONFIG_CMD_USB int usb_board_init(void) { @@ -78,7 +65,8 @@ int usb_board_init(void) writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (UHCHR & UHCHR_FSBIR) + ; writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -126,3 +114,11 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 99f665b472..129119528f 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -33,6 +33,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <asm/io.h> @@ -139,10 +140,9 @@ struct serial_device *default_serial_console (void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index b5c60fd209..5967055996 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -23,7 +23,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := vpac270.o +else +COBJS := onenand.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c new file mode 100644 index 0000000000..c2ae9a711b --- /dev/null +++ b/board/vpac270/onenand.c @@ -0,0 +1,65 @@ +/* + * Voipac PXA270 OneNAND SPL + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <onenand_uboot.h> +#include <asm/arch/pxa.h> + +void board_init_f(unsigned long unused) +{ + extern uint32_t _end; + uint32_t tmp; + + asm volatile("mov %0, pc" : "=r"(tmp)); + tmp >>= 24; + + /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */ + if (tmp == 0) { + tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE; + onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE)); + } + + /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ + arch_cpu_init(); + pxa2xx_dram_init(); + onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, + CONFIG_SPL_ONENAND_LOAD_SIZE, + (void *)CONFIG_SYS_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE)); + + for (;;) + ; +} + +void __attribute__((noreturn)) hang(void) +{ + for (;;) + ; +} + +void icache_disable(void) {} +void dcache_disable(void) {} diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds new file mode 100644 index 0000000000..1958c2fb90 --- /dev/null +++ b/board/vpac270/u-boot-spl.lds @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text.0 : + { + arch/arm/cpu/pxa/start.o (.text*) + board/vpac270/libvpac270.o (.text*) + drivers/mtd/onenand/libonenand.o (.text*) + } + + + /* Start of the rest of the SPL */ + . = CONFIG_SPL_TEXT_BASE + 0x800; + + .text.1 : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(0x800); + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index cf8e7b61db..dfdab9b6f6 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/arch/hardware.h> #include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <serial.h> #include <asm/io.h> @@ -54,10 +55,11 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); +#ifndef CONFIG_ONENAND + pxa2xx_dram_init(); +#endif gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 40b0f3b30e..a4acf6c766 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -30,6 +30,7 @@ #include <common.h> #include <netdev.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -59,10 +60,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/xm250/Makefile b/board/xm250/Makefile deleted file mode 100644 index 6a0cca0f9c..0000000000 --- a/board/xm250/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := xm250.o flash.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xm250/flash.c b/board/xm250/flash.c deleted file mode 100644 index e825abae1a..0000000000 --- a/board/xm250/flash.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - ulong start; - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - start = get_timer(0); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c deleted file mode 100644 index 3188cf2fab..0000000000 --- a/board/xm250/xm250.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/pxa-regs.h> -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* local prototypes */ - -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of MicroSys XM250 */ - gd->bd->bi_arch_number = MACH_TYPE_XM250; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 9e6a0d51c4..b093c2f51f 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -27,6 +27,7 @@ #include <command.h> #include <serial.h> #include <asm/arch/hardware.h> +#include <asm/arch/pxa.h> #include <spi.h> #include <asm/io.h> @@ -65,10 +66,9 @@ struct serial_device *default_serial_console (void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } |