diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-08-21 14:49:30 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-28 12:08:54 +0200 |
| commit | ef3a439172950c0a9e582784929559b2d5b3bf81 (patch) | |
| tree | d85b79f604b0f4272b2d63e7e73872b1d5f311aa /board | |
| parent | 87123df10ba43492e2f8d20da5d92c56057db316 (diff) | |
colibri imx6: use dynamic ddr calibration
Some Colibri iMX6 IT were found which were freezing at higher temperature.
Using the SPL to do a dynamic calibration at each boot fixes the issue.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index c4e24fcda7..f3181a0fa1 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1089,6 +1089,10 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); } +static struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 2, +}; + static void spl_dram_init(void) { int minc, maxc; @@ -1105,6 +1109,7 @@ static void spl_dram_init(void) #ifndef CONFIG_SPL_SILENT_CONSOLE puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); #endif + ddr_sysinfo.dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1120,11 +1125,15 @@ static void spl_dram_init(void) #ifndef CONFIG_SPL_SILENT_CONSOLE puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); #endif + ddr_sysinfo.dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; }; udelay(100); + /* Perform DDR DRAM calibration */ + mmdc_do_write_level_calibration(&ddr_sysinfo); + mmdc_do_dqs_calibration(&ddr_sysinfo); } static iomux_v3_cfg_t const gpio_reset_pad[] = { |