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authorBai Ping <ping.bai@nxp.com>2018-11-01 17:47:20 +0800
committerNitin Garg <nitin.garg@nxp.com>2018-11-02 20:50:11 -0500
commit048327a4f276289c76b7e4280e332f79cb6aa10e (patch)
treecf365116a7d95fd6c5ae7ee69324afd4d6dfd5b0 /board
parent86d712e35446669a018969e2ea21e9c29efc2762 (diff)
MLK-10163-01 imx8mq: Re-desine the dram_pll_init function
Change the dram_pll_init function API to make it same as i.MX8MM, so the dram init flow can use call the same API for these two different SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c2
-rw-r--r--board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c
index bc9acdee18..8471a77bba 100644
--- a/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c
+++ b/board/freescale/imx8mq_arm2/ddr/ddr3l/ddr_init.c
@@ -135,7 +135,7 @@ void ddr_init(void)
reg32setbit(0x303A00F8,5);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
- dram_pll_init(SSCG_PLL_OUT_400M);
+ dram_pll_init(DRAM_PLL_OUT_400M);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
diff --git a/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c
index 7339703207..e4f410ecaf 100644
--- a/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c
+++ b/board/freescale/imx8mq_arm2/ddr/ddr4/ddr_init.c
@@ -137,7 +137,7 @@ void ddr_init(void)
reg32setbit(0x303A00F8,5);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
- dram_pll_init(SSCG_PLL_OUT_600M);
+ dram_pll_init(DRAM_PLL_OUT_600M);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);