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authorVarun Wadekar <vwadekar@nvidia.com>2012-01-03 15:04:40 +0530
committerGerrit <chrome-bot@google.com>2012-02-08 22:08:36 -0800
commit929e867d143b66d96e6c4a8e1f69d3e8c6ca14fd (patch)
tree0c28785a6fbed4277223d5882d92c7e8ffc5db8d /board
parentf116864a29c5b29ed5b63c6aafc93442ba35f483 (diff)
arm: tegra2: split LP0 code to help future chips
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13799
Diffstat (limited to 'board')
-rw-r--r--board/nvidia/common/Makefile4
-rw-r--r--board/nvidia/common/board.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
index cd821ebb07..48d04b494d 100644
--- a/board/nvidia/common/Makefile
+++ b/board/nvidia/common/Makefile
@@ -31,8 +31,8 @@ COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-fix.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
COBJS-$(CONFIG_TEGRA_KEYBOARD) += generic_kbc.o
-COBJS-$(CONFIG_TEGRA2_LP0) += crypto/aes_ref.o
-COBJS-$(CONFIG_TEGRA2_LP0) += crypto/crypto.o
+COBJS-$(CONFIG_TEGRA_LP0) += crypto/aes_ref.o
+COBJS-$(CONFIG_TEGRA_LP0) += crypto/crypto.o
COBJS-$(CONFIG_TEGRA2_NAND) += tegra2_nand.o
COBJS := $(COBJS-y)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 4e517deda8..5cb219b4f9 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -346,7 +346,7 @@ int board_init(void)
board_emc_init();
#endif
-#ifdef CONFIG_TEGRA2_LP0
+#ifdef CONFIG_TEGRA_LP0
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif