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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2016-02-25 12:51:50 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-07-22 14:03:50 +0200 |
| commit | 1d405e207bb176c937d44f9a5f87e268022c2416 (patch) | |
| tree | 7422ff0cdad8de13369f9be8525eb9d75c82d96c /configs/xilinx_zynqmp_zcu102_defconfig | |
| parent | 211815784c0e35a274e13054a7966b21098f8a14 (diff) | |
mmc: sdhci: Disable internal clock enable bit
Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'configs/xilinx_zynqmp_zcu102_defconfig')
0 files changed, 0 insertions, 0 deletions