diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2012-12-11 11:10:36 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2012-12-11 11:10:36 -0600 |
| commit | d31df11541ea0d1a0bf1ed7463fd30a25b65f98c (patch) | |
| tree | 993a632a3ffa39be0f042fb036d1db53633aac16 /cpu | |
| parent | 07663772b10318e3d7f0aa3e410f0ff840780806 (diff) | |
ENGR00236620: Add Android fastboot and recovery reboot support
Add support for Android fastboot and recovery reboot
commands for iMX5.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index 7a6d95e6dd..83dbd4bd0e 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -1213,12 +1213,48 @@ struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = { }; #endif -#ifdef CONFIG_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +#define ANDROID_RECOVERY_BOOT (1 << 27) /* check if the recovery bit is set by kernel, it can be set by kernel + * issue a command '# reboot recovery' */ +int check_and_clean_recovery_flag(void) +{ + int flag_set = 0; + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + + flag_set = !!(reg & ANDROID_RECOVERY_BOOT); + + /* clean it in case looping infinite here.... */ + if (flag_set) { + printf("Recovery flag is set...\n"); + reg &= ~ANDROID_RECOVERY_BOOT; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); + } + + return flag_set; +} +#endif + +#ifdef CONFIG_FASTBOOT +#define ANDROID_FASTBOOT_BOOT (1 << 26) +/* check if the fastboot bit is set by kernel, it can be set by kernel * issue a command '# reboot fastboot' */ int fastboot_check_and_clean_flag(void) { - return 0; + int flag_set = 0; + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + + flag_set = !!(reg & ANDROID_FASTBOOT_BOOT); + + /* clean it in case looping infinite here.... */ + if (flag_set) { + reg &= ~ANDROID_FASTBOOT_BOOT; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); + } + + return flag_set; } #endif |