U-Boot: da850 build cleanup.

cleanup da850 build to not create seperate directory for DA850. DA850/DA830
specific code can use CONFIF_{DA830|DA850}_SOC - the preferred way would be
to use runtime check - but that facility is not present currently.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

8 files changed, 0 insertions, 2333 deletions

diff --git a/cpu/arm926ejs/da850/Makefile b/cpu/arm926ejs/da850/Makefile
deleted file mode 100644
index 49fa3111ef..0000000000
--- a/cpu/arm926ejs/da850/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= timer.o ether.o nand.o clock.o i2c.o
-SOBJS	= lowlevel_init.o reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm926ejs/da850/clock.c b/cpu/arm926ejs/da850/clock.c
deleted file mode 100644
index 7cb979bc00..0000000000
--- a/cpu/arm926ejs/da850/clock.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc.  <nsekhar@ti.com>
- * 
- * DA8xx clock module
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-dv_reg_p sysdiv[9] = {
-    PLL0_DIV1, PLL0_DIV2, PLL0_DIV3, PLL0_DIV4, PLL0_DIV5, PLL0_DIV6, 
-    PLL0_DIV7, PLL0_DIV8, PLL0_DIV9 };
-
-int clk_get(unsigned int id)
-{
-    int pre_div = (REG(PLL0_PREDIV) & 0xff) + 1;
-    int pllm = REG(PLL0_PLLM)  + 1;
-    int post_div = (REG(PLL0_POSTDIV) & 0xff) + 1;
-    int pll_out = CFG_OSCIN_FREQ;
-
-    if(id == DAVINCI_AUXCLK_CLKID) 
-        goto out;
-
-    /* Lets keep this simple. Combining operations can result in 
-     * unexpected approximations
-     */
-    pll_out /= pre_div;
-    pll_out *= pllm;
-
-    if(id == DAVINCI_PLLM_CLKID) 
-        goto out;
-    
-    pll_out /= post_div;
-	
-    if(id == DAVINCI_PLLC_CLKID) 
-        goto out;
-    
-   pll_out /= (REG(sysdiv[id - 1]) & 0xff) + 1;
-
-out:
-	return pll_out;	
-}
diff --git a/cpu/arm926ejs/da850/ether.c b/cpu/arm926ejs/da850/ether.c
deleted file mode 100644
index f128196bb9..0000000000
--- a/cpu/arm926ejs/da850/ether.c
+++ /dev/null
@@ -1,667 +0,0 @@
-/*
- * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
- * follows:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.c
- *
- * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
-
- * Modifications:
- * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
- * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
- *
- */
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-unsigned int	emac_dbg = 0;
-#define debug_emac(fmt,args...)	if (emac_dbg) printf(fmt,##args)
-
-/* Internal static functions */
-static int dm644x_eth_hw_init (void);
-static int dm644x_eth_open (void);
-static int dm644x_eth_close (void);
-static int dm644x_eth_send_packet (volatile void *packet, int length);
-static int dm644x_eth_rcv_packet (void);
-static void dm644x_eth_mdio_enable(void);
-
-static int gen_init_phy(int phy_addr);
-static int gen_is_phy_connected(int phy_addr);
-static int gen_get_link_speed(int phy_addr);
-static int gen_auto_negotiate(int phy_addr);
-
-/* Wrappers exported to the U-Boot proper */
-int eth_hw_init(void)
-{
-	return(dm644x_eth_hw_init());
-}
-
-int eth_init(bd_t * bd)
-{
-	return(dm644x_eth_open());
-}
-
-void eth_halt(void)
-{
-	dm644x_eth_close();
-}
-
-int eth_send(volatile void *packet, int length)
-{
-	return(dm644x_eth_send_packet(packet, length));
-}
-
-int eth_rx(void)
-{
-	return(dm644x_eth_rcv_packet());
-}
-
-void eth_mdio_enable(void)
-{
-	dm644x_eth_mdio_enable();
-}
-/* End of wrappers */
-
-/* dm644x_eth_mac_addr[0] goes out on the wire first */
-
-static u_int8_t dm644x_eth_mac_addr[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00 };
-
-/*
- * This function must be called before emac_open() if you want to override
- * the default mac address.
- */
-void dm644x_eth_set_mac_addr(const u_int8_t *addr)
-{
-	int i;
-
-	for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) {
-		dm644x_eth_mac_addr[i] = addr[i];
-	}
-}
-
-/* EMAC Addresses */
-static volatile emac_regs	*adap_emac = (emac_regs *)EMAC_BASE_ADDR;
-static volatile ewrap_regs	*adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
-static volatile mdio_regs	*adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
-
-/* EMAC descriptors */
-static volatile emac_desc	*emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
-static volatile emac_desc	*emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
-static volatile emac_desc	*emac_rx_active_head = 0;
-static volatile emac_desc	*emac_rx_active_tail = 0;
-static int			emac_rx_queue_active = 0;
-
-/* Receive packet buffers */
-static unsigned char		emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
-
-/* PHY address for a discovered PHY (0xff - not found) */
-static volatile u_int8_t	active_phy_addr = 0xff;
-
-static int	no_phy_init (int phy_addr) { return(1); }
-static int	no_phy_is_connected (int phy_addr) { return(1); }
-static int	no_phy_get_link_speed (int phy_addr) { return(1); }
-static int  no_phy_auto_negotiate (int phy_addr) { return(1); }
-phy_t				phy  = {
-	.init = no_phy_init,
-	.is_phy_connected = no_phy_is_connected,
-    .get_link_speed = no_phy_get_link_speed,
-    .auto_negotiate = no_phy_auto_negotiate
-};
-
-static void dm644x_eth_mdio_enable(void)
-{
-	u_int32_t	clkdiv;
-
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-
-	adap_mdio->CONTROL = (clkdiv & 0xff) |
-		MDIO_CONTROL_ENABLE |
-		MDIO_CONTROL_FAULT |
-		MDIO_CONTROL_FAULT_ENABLE;
-
-	while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;}
-}
-
-/*
- * Tries to find an active connected PHY. Returns 1 if address if found.
- * If no active PHY found returns 0. If more than one active PHY (switch)
- * returns 2
- * Sets active_phy_addr variable when returns 1.
- */
-static int dm644x_eth_phy_detect(void)
-{
-	u_int32_t	phy_act_state;
-	int		i;
-
-	active_phy_addr = 0xff;
-
-	if ((phy_act_state = adap_mdio->ALIVE) == 0)
-		return(0);				/* No active PHYs */
-
-	debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
-
-	for (i = 0; i < 32; i++) {
-		if (phy_act_state & (1 << i)) {
-			if (phy_act_state & ~(1 << i))
-				return(2);		/* More than one PHY */
-			else {
-				active_phy_addr = i;
-				return(1);
-			}
-		}
-	}
-
-	return(0);	/* Just to make GCC happy */
-}
-
-
-/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
-int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
-{
-	int	tmp;
-
-	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
-
-	adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
-				MDIO_USERACCESS0_WRITE_READ |
-				((reg_num & 0x1f) << 21) |
-				((phy_addr & 0x1f) << 16);
-
-	/* Wait for command to complete */
-	while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;}
-
-	if (tmp & MDIO_USERACCESS0_ACK) {
-		*data = tmp & 0xffff;
-		return(1);
-	}
-
-	*data = -1;
-	return(0);
-}
-
-/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
-int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
-{
-
-	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
-
-	adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
-				MDIO_USERACCESS0_WRITE_WRITE |
-				((reg_num & 0x1f) << 21) |
-				((phy_addr & 0x1f) << 16) |
-				(data & 0xffff);
-
-	/* Wait for command to complete */
-	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
-
-	return(1);
-}
-
-/* PHY functions for a generic PHY */
-static int gen_init_phy(int phy_addr)
-{
-	int	ret = 1;
-
-	if (gen_get_link_speed(phy_addr)) {
-		/* Try another time */
-		ret = gen_get_link_speed(phy_addr);
-	}
-
-	return(ret);
-}
-
-static int gen_is_phy_connected(int phy_addr)
-{
-	u_int16_t	dummy;
-
-	return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
-}
-
-static int gen_get_link_speed(int phy_addr)
-{
-	u_int16_t	tmp;
-
-	if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
-		return(1);
-
-	return(0);
-}
-
-static int gen_auto_negotiate(int phy_addr)
-{
-	u_int16_t	tmp;
-
-	if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
-		return(0);
-
-	/* Restart Auto_negotiation  */
-	tmp |= PHY_BMCR_AUTON;
-	dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp);
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
-		return(0);
-
-	if (!(tmp & PHY_BMSR_AUTN_COMP))
-		return(0);
-
-	return(gen_get_link_speed(phy_addr));
-}
-/* End of generic PHY functions */
-
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
-{
-	return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1);
-}
-
-static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
-{
-	return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1);
-}
-
-int dm644x_eth_miiphy_initialize(bd_t *bis)
-{
-	miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write);
-
-	return(1);
-}
-#endif
-
-/*
- * This function initializes the emac hardware. It does NOT initialize
- * EMAC modules power or pin multiplexors, that is done by board_init()
- * much earlier in bootup process. Returns 1 on success, 0 otherwise.
- */
-static int dm644x_eth_hw_init(void)
-{
-	u_int32_t	phy_id;
-	u_int16_t	tmp;
-	int		i, ret;
-
-    /* The RMII clock can be sources internally through the SYSCLK7
-     * or can come externally through a dedicated pin. This selection is
-     * controlled by PinMux9[21]. PinMux registers are off-limits for ARM.
-     * In short, we just assume there is a 50MHz RMII clock available.
-     */
-
-	dm644x_eth_mdio_enable();
-
-	for (i = 0; i < 256; i++) {
-		if (adap_mdio->ALIVE)
-			break;
-		udelay(1000);
-	}
-
-	if (i >= 256) {
-		printf("No ETH PHY detected!!!\n");
-		return(0);
-	}
-
-	/* Find if a PHY is connected and get it's address */
-    ret = dm644x_eth_phy_detect();
-    
-	if (ret == 2) {
-        printf("More than one PHY detected.\n");
-		return(1);
-    } else if(ret == 0)
-        return(0);
-
-	/* Get PHY ID and initialize phy_ops for a detected PHY */
-	if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
-		active_phy_addr = 0xff;
-		return(0);
-	}
-
-	phy_id = (tmp << 16) & 0xffff0000;
-
-	if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
-		active_phy_addr = 0xff;
-		return(0);
-	}
-
-	phy_id |= tmp & 0x0000ffff;
-
-	switch (phy_id) {
-		default:
-			sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
-			phy.init = gen_init_phy;
-			phy.is_phy_connected = gen_is_phy_connected;
-			phy.get_link_speed = gen_get_link_speed;
-			phy.auto_negotiate = gen_auto_negotiate;
-	}
-
-	return(1);
-}
-
-
-/* Eth device open */
-static int dm644x_eth_open(void)
-{
-	dv_reg_p		addr;
-	u_int32_t		clkdiv, cnt;
-	volatile emac_desc	*rx_desc;
-    int i;
-
-	debug_emac("+ emac_open\n");
-
-	/* Reset EMAC module and disable interrupts in wrapper */
-	adap_emac->SOFTRESET = 1;
-	while (adap_emac->SOFTRESET != 0) {;}
-	adap_ewrap->SOFTRESET = 1;
-	while (adap_ewrap->SOFTRESET != 0) {;}
-    
-    adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0;   
-    adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0;   
-    adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0;   
-   
-	rx_desc = emac_rx_desc;
-
-	adap_emac->TXCONTROL = 0x01;
-	adap_emac->RXCONTROL = 0x01;
-
-	/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
-	/* Using channel 0 only - other channels are disabled */
-    for (i = 0; i < 8; i++) {
-    	adap_emac->MACINDEX = i;
-	    adap_emac->MACADDRHI =
-		    (dm644x_eth_mac_addr[3] << 24) |				/* bits 23-16 */
-		    (dm644x_eth_mac_addr[2] << 16) |				/* bits 31-24 */
-		    (dm644x_eth_mac_addr[1] << 8)  |				/* bits 39-32 */
-		    (dm644x_eth_mac_addr[0]);						/* bits 47-40 */
-	    adap_emac->MACADDRLO =
-		    (dm644x_eth_mac_addr[5] << 8) |					  /* bits 8-0*/
-		    (dm644x_eth_mac_addr[4]) | (1 << 19) | (1 << 20); /* bits 8-0 */
-    }
-
-	adap_emac->MACHASH1 = 0;
-	adap_emac->MACHASH2 = 0;
-
-	/* Set source MAC address - REQUIRED for pause frames */
-	adap_emac->MACSRCADDRHI =
-		(dm644x_eth_mac_addr[3] << 24) |	/* bits 23-16 */
-		(dm644x_eth_mac_addr[2] << 16) |	/* bits 31-24 */
-		(dm644x_eth_mac_addr[1] << 8)  |	/* bits 39-32 */
-		(dm644x_eth_mac_addr[0]);			/* bits 47-40 */	
-	adap_emac->MACSRCADDRLO =
-		(dm644x_eth_mac_addr[5] << 8) |		/* bits 8-0  */
-		(dm644x_eth_mac_addr[4]);			/* bits 15-8 */
-
-	/* Set DMA 8 TX / 8 RX Head pointers to 0 */
-	addr = &adap_emac->TX0HDP;
-	for(cnt = 0; cnt < 16; cnt++)
-		*addr++ = 0;
-
-	addr = &adap_emac->TX0CP;
-	for(cnt = 0; cnt < 16; cnt++)
-		*addr++ = 0;
-
-	/* Clear Statistics (do this before setting MacControl register) */
-	addr = &adap_emac->RXGOODFRAMES;
-	for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
-		*addr++ = 0;
-
-	/* No multicast addressing */
-	adap_emac->MACHASH1 = 0;
-	adap_emac->MACHASH2 = 0;
-
-	/* Create RX queue and set receive process in place */
-	emac_rx_active_head = emac_rx_desc;
-	for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
-		rx_desc->next = (u_int32_t)(rx_desc + 1);
-		rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
-		rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
-		rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
-		rx_desc++;
-	}
-
-	/* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
-	rx_desc--;
-	rx_desc->next = 0;
-	emac_rx_active_tail = rx_desc;
-	emac_rx_queue_active = 1;
-
-	/* Enable TX/RX */
-	adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE;
-	adap_emac->RXBUFFEROFFSET = 0;
-
-	/* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
-	adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN;
-
-	/* Enable ch 0 only */
-	adap_emac->RXUNICASTSET = 0x01;
-
-	/* Enable MII interface and Full duplex mode */
-	adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE) | EMAC_MACCONTROL_RMIISPEED_100;
-
-	/* Init MDIO & get link state */
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-	adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT);
-
-	if (!phy.get_link_speed(active_phy_addr))
-		return(0);
-
-	/* Start receive process */
-	adap_emac->RX0HDP = (u_int32_t)emac_rx_desc;
-
-	debug_emac("- emac_open\n");
-
-	return(1);
-}
-
-/* EMAC Channel Teardown */
-static void dm644x_eth_ch_teardown(int ch)
-{
-	dv_reg		dly = 0xff;
-	dv_reg		cnt;
-
-	debug_emac("+ emac_ch_teardown\n");
-
-	if (ch == EMAC_CH_TX) {
-		/* Init TX channel teardown */
-		adap_emac->TXTEARDOWN = 1;
-		for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) {
-			/* Wait here for Tx teardown completion interrupt to occur
-			 * Note: A task delay can be called here to pend rather than
-			 * occupying CPU cycles - anyway it has been found that teardown
-			 * takes very few cpu cycles and does not affect functionality */
-			 dly--;
-			 udelay(1);
-			 if (dly == 0)
-			 	break;
-		}
-		adap_emac->TX0CP = cnt;
-		adap_emac->TX0HDP = 0;
-	} else {
-		/* Init RX channel teardown */
-		adap_emac->RXTEARDOWN = 1;
-		for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) {
-			/* Wait here for Rx teardown completion interrupt to occur
-			 * Note: A task delay can be called here to pend rather than
-			 * occupying CPU cycles - anyway it has been found that teardown
-			 * takes very few cpu cycles and does not affect functionality */
-			 dly--;
-			 udelay(1);
-			 if (dly == 0)
-			 	break;
-		}
-		adap_emac->RX0CP = cnt;
-		adap_emac->RX0HDP = 0;
-	}
-
-	debug_emac("- emac_ch_teardown\n");
-}
-
-/* Eth device close */
-static int dm644x_eth_close(void)
-{
-	debug_emac("+ emac_close\n");
-
-	dm644x_eth_ch_teardown(EMAC_CH_TX);	/* TX Channel teardown */
-	dm644x_eth_ch_teardown(EMAC_CH_RX);	/* RX Channel teardown */
-
-	/* Reset EMAC module and disable interrupts in wrapper */
-	adap_emac->SOFTRESET = 1;
-	adap_ewrap->SOFTRESET = 1;
-    
-    adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0;   
-    adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0;   
-    adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0;   
-
-	debug_emac("- emac_close\n");
-	return(1);
-}
-
-static int tx_send_loop = 0;
-
-/*
- * This function sends a single packet on the network and returns
- * positive number (number of bytes transmitted) or negative for error
- */
-static int dm644x_eth_send_packet(volatile void *packet, int length)
-{
-	int ret_status = -1;
-	tx_send_loop = 0;
-
-	/* Return error if no link */
-	if (!phy.get_link_speed(active_phy_addr))
-	{
-		printf("WARN: emac_send_packet: No link\n");
-		return (ret_status);
-	}
-
-	/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
-	if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
-	{
-		length = EMAC_MIN_ETHERNET_PKT_SIZE;
-	}
-
-	/* Populate the TX descriptor */
-	emac_tx_desc->next         = 0;
-	emac_tx_desc->buffer       = (u_int8_t *)packet;
-	emac_tx_desc->buff_off_len = (length & 0xffff);
-	emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
-			EMAC_CPPI_SOP_BIT |
-			EMAC_CPPI_OWNERSHIP_BIT |
-			EMAC_CPPI_EOP_BIT);
-	/* Send the packet */
-	adap_emac->TX0HDP = (unsigned int)emac_tx_desc;
-
-	/* Wait for packet to complete or link down */
-	while (1) {
-	        if (!phy.get_link_speed(active_phy_addr)) {
-	        	dm644x_eth_ch_teardown(EMAC_CH_TX);
-	        	return (ret_status);
-	        }
-	        if (adap_emac->TXINTSTATRAW & 0x01) {
-	        	ret_status = length;
-	        	break;
-		}
-	        tx_send_loop++;
-	}
-
-	return(ret_status);
-}
-
-/*
- * This function handles receipt of a packet from the network
- */
-static int dm644x_eth_rcv_packet(void)
-{
-	volatile emac_desc	*rx_curr_desc;
-	volatile emac_desc	*curr_desc;
-	volatile emac_desc	*tail_desc;
-	int			status, ret = -1;
-
-	rx_curr_desc = emac_rx_active_head;
-	status = rx_curr_desc->pkt_flag_len;
-	if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
-	        if (status & EMAC_CPPI_RX_ERROR_FRAME) {
-	        	/* Error in packet - discard it and requeue desc */
-	        	printf("WARN: emac_rcv_pkt: Error in packet\n");
-		} else {
-			NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff));
-			ret = rx_curr_desc->buff_off_len & 0xffff;
-	        }
-
-	        /* Ack received packet descriptor */
-	        adap_emac->RX0CP = (unsigned int)rx_curr_desc;
-	        curr_desc = rx_curr_desc;
-	        emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next;
-
-	        if (status & EMAC_CPPI_EOQ_BIT) {
-	        	if (emac_rx_active_head) {
-	        		adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
-			} else {
-				emac_rx_queue_active = 0;
-				printf("INFO:emac_rcv_packet: RX Queue not active\n");
-			}
-		}
-
-		/* Recycle RX descriptor */
-		rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
-		rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
-		rx_curr_desc->next = 0;
-
-		if (emac_rx_active_head == 0) {
-			printf("INFO: emac_rcv_pkt: active queue head = 0\n");
-			emac_rx_active_head = curr_desc;
-			emac_rx_active_tail = curr_desc;
-			if (emac_rx_queue_active != 0) {
-				adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
-				printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
-				emac_rx_queue_active = 1;
-			}
-		} else {
-			tail_desc = emac_rx_active_tail;
-			emac_rx_active_tail = curr_desc;
-			tail_desc->next = (unsigned int)curr_desc;
-			status = tail_desc->pkt_flag_len;
-			if (status & EMAC_CPPI_EOQ_BIT) {
-				adap_emac->RX0HDP = (unsigned int)curr_desc;
-				status &= ~EMAC_CPPI_EOQ_BIT;
-				tail_desc->pkt_flag_len = status;
-			}
-		}
-		return(ret);
-	}
-	return(0);
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/cpu/arm926ejs/da850/i2c.c b/cpu/arm926ejs/da850/i2c.c
deleted file mode 100644
index 7b978a855f..0000000000
--- a/cpu/arm926ejs/da850/i2c.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * TI DaVinci (TMS320DM644x) I2C driver.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/i2c_defs.h>
-
-#define CHECK_NACK() \
-	do {\
-		if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
-			REG(I2C_CON) = 0;\
-			return(1);\
-		}\
-	} while (0)
-
-
-static int wait_for_bus(void)
-{
-	int	stat, timeout;
-
-	REG(I2C_STAT) = 0xffff;
-
-	for (timeout = 0; timeout < 10; timeout++) {
-		if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
-			REG(I2C_STAT) = 0xffff;
-			return(0);
-		}
-
-		REG(I2C_STAT) = stat;
-		udelay(50000);
-	}
-
-	REG(I2C_STAT) = 0xffff;
-	return(1);
-}
-
-
-static int poll_i2c_irq(int mask)
-{
-	int	stat, timeout;
-
-	for (timeout = 0; timeout < 10; timeout++) {
-		udelay(1000);
-		stat = REG(I2C_STAT);
-		if (stat & mask) {
-			return(stat);
-		}
-	}
-
-	REG(I2C_STAT) = 0xffff;
-	return(stat | I2C_TIMEOUT);
-}
-
-
-void flush_rx(void)
-{
-	int	dummy;
-
-	while (1) {
-		if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
-			break;
-
-		dummy = REG(I2C_DRR);
-		REG(I2C_STAT) = I2C_STAT_RRDY;
-		udelay(1000);
-	}
-}
-
-
-void i2c_init(int speed, int slaveadd)
-{
-	u_int32_t	div, psc;
-
-	if (REG(I2C_CON) & I2C_CON_EN) {
-		REG(I2C_CON) = 0;
-		udelay (50000);
-	}
-
-	/* Get 1MHz into I2C internal */
-	psc = CONFIG_SYS_HZ_CLOCK/1000000;
-
-	div = CONFIG_SYS_HZ_CLOCK / (psc * speed);	/* SCLL + SCLH */
-
-	REG(I2C_PSC) = psc - 1;			/* 27MHz / (2 + 1) = 9MHz */
-	REG(I2C_SCLL) = (div * 50) / 100;	/* 50% Duty */
-	REG(I2C_SCLH) = div - REG(I2C_SCLL);
-
-	REG(I2C_OA) = slaveadd;
-	REG(I2C_CNT) = 0;
-
-	/* Interrupts must be enabled or I2C module won't work */
-	REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
-		I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
-
-	/* Now enable I2C controller (get it out of reset) */
-	REG(I2C_CON) = I2C_CON_EN;
-
-	udelay(1000);
-}
-
-
-int i2c_probe(u_int8_t chip)
-{
-	int	rc = 1;
-
-	if (chip == REG(I2C_OA)) {
-		return(rc);
-	}
-
-	REG(I2C_CON) = 0;
-	if (wait_for_bus()) {return(1);}
-
-	/* try to read one byte from current (or only) address */
-	REG(I2C_CNT) = 1;
-	REG(I2C_SA) = chip;
-	REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_FREE);
-	udelay (50000);
-
-	if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
-		rc = 0;
-		flush_rx();
-		REG(I2C_STAT) = 0xffff;
-	} else {
-		REG(I2C_STAT) = 0xffff;
-		REG(I2C_CON) |= I2C_CON_STP;
-		udelay(20000);
-		if (wait_for_bus()) {return(1);}
-	}
-
-	flush_rx();
-	REG(I2C_STAT) = 0xffff;
-	REG(I2C_CNT) = 0;
-	return(rc);
-}
-
-
-int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
-{
-	u_int32_t	tmp;
-	int		i;
-
-	if ((alen < 0) || (alen > 2)) {
-		printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
-		return(1);
-	}
-
-	if (wait_for_bus()) {return(1);}
-
-	if (alen != 0) {
-		/* Start address phase */
-		tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 
-			I2C_CON_FREE;
-		REG(I2C_CNT) = alen;
-		REG(I2C_SA) = chip;
-		REG(I2C_CON) = tmp;
-
-		tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-		CHECK_NACK();
-
-		switch (alen) {
-			case 2:
-				/* Send address MSByte */
-				if (tmp & I2C_STAT_XRDY) {
-					REG(I2C_DXR) = (addr >> 8) & 0xff;
-				} else {
-					REG(I2C_CON) = 0;
-					return(1);
-				}
-
-				tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-				CHECK_NACK();
-				/* No break, fall through */
-			case 1:
-				/* Send address LSByte */
-				if (tmp & I2C_STAT_XRDY) {
-					REG(I2C_DXR) = addr & 0xff;
-				} else {
-					REG(I2C_CON) = 0;
-					return(1);
-				}
-
-				tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
-
-				CHECK_NACK();
-
-				if (!(tmp & I2C_STAT_ARDY)) {
-					REG(I2C_CON) = 0;
-					return(1);
-				}
-		}
-	}
-
-	/* Address phase is over, now read 'len' bytes and stop */
-	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_FREE;
-	REG(I2C_CNT) = len & 0xffff;
-	REG(I2C_SA) = chip;
-	REG(I2C_CON) = tmp;
-
-	for (i = 0; i < len; i++) {
-		tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
-
-		CHECK_NACK();
-
-		if (tmp & I2C_STAT_RRDY) {
-			buf[i] = REG(I2C_DRR);
-		} else {
-			REG(I2C_CON) = 0;
-			return(1);
-		}
-	}
-
-	tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
-
-	CHECK_NACK();
-
-	if (!(tmp & I2C_STAT_SCD)) {
-		REG(I2C_CON) = 0;
-		return(1);
-	}
-
-	flush_rx();
-	REG(I2C_STAT) = 0xffff;
-	REG(I2C_CNT) = 0;
-	REG(I2C_CON) = 0;
-
-	return(0);
-}
-
-
-int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
-{
-	u_int32_t	tmp;
-	int		i;
-
-	if ((alen < 0) || (alen > 2)) {
-		printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
-		return(1);
-	}
-	if (len < 0) {
-		printf("%s(): bogus length %x\n", __FUNCTION__, len);
-		return(1);
-	}
-
-	if (wait_for_bus()) {return(1);}
-
-	/* Start address phase */
-	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
-	REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
-	REG(I2C_SA) = chip;
-	REG(I2C_CON) = tmp;
-
-	switch (alen) {
-		case 2:
-			/* Send address MSByte */
-			tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-			CHECK_NACK();
-
-			if (tmp & I2C_STAT_XRDY) {
-				REG(I2C_DXR) = (addr >> 8) & 0xff;
-			} else {
-				REG(I2C_CON) = 0;
-				return(1);
-			}
-			/* No break, fall through */
-		case 1:
-			/* Send address LSByte */
-			tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-			CHECK_NACK();
-
-			if (tmp & I2C_STAT_XRDY) {
-				REG(I2C_DXR) = addr & 0xff;
-			} else {
-				REG(I2C_CON) = 0;
-				return(1);
-			}
-	}
-
-	for (i = 0; i < len; i++) {
-		tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-		CHECK_NACK();
-
-		if (tmp & I2C_STAT_XRDY) {
-			REG(I2C_DXR) = buf[i];
-		} else {
-			return(1);
-		}
-	}
-
-	tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
-
-	CHECK_NACK();
-
-	if (!(tmp & I2C_STAT_SCD)) {
-		REG(I2C_CON) = 0;
-		return(1);
-	}
-
-	flush_rx();
-	REG(I2C_STAT) = 0xffff;
-	REG(I2C_CNT) = 0;
-	REG(I2C_CON) = 0;
-
-	return(0);
-}
-
-#if 0
-u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg)
-{
-	u_int8_t	tmp;
-
-	i2c_read(chip, reg, 1, &tmp, 1);
-	return(tmp);
-}
-
-
-void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val)
-{
-	u_int8_t	tmp;
-
-	i2c_write(chip, reg, 1, &tmp, 1);
-}
-#endif /* if 0 */
-
-#endif /* CONFIG_DRIVER_DAVINCI_I2C */
diff --git a/cpu/arm926ejs/da850/lowlevel_init.S b/cpu/arm926ejs/da850/lowlevel_init.S
deleted file mode 100644
index c36993e16e..0000000000
--- a/cpu/arm926ejs/da850/lowlevel_init.S
+++ /dev/null
@@ -1,504 +0,0 @@
-/*
- * Low-level board setup code for TI DA8xx SoC based boards.
- *
- * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
- * Sekhar Nori <nsekhar@ti.com>
- * 
- * Based on TI DaVinci low level init code. Original copyrights follow.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-
-.globl	lowlevel_init
-lowlevel_init:
-
-	nop
-	nop
-	nop
-	nop
-
-	/*
-	 * Call board-specific lowlevel init.
- 	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-#ifndef CONFIG_USE_IRQ
-	/*-------------------------------------------------------*
-	 * Mask all IRQs by clearing the global enable and setting
-     * the enable clear for all the 90 interrupts.
-	 *-------------------------------------------------------*/
-	mov	r1, $0
-	ldr	r0, INTC_GLB_EN_ADDR
-	str	r1, [r0]
-
-	ldr r0, INTC_HINT_EN_ADDR
-	str	r1, [r0]
-	add	r0, r0, $4
-	str	r1, [r0]
-	add	r0, r0, $4
-	str	r1, [r0]
-
-    mvn r1, r1  
-	ldr	r0, INTC_EN_CLR0_ADDR
-	str	r1, [r0]
-	add	r0, r0, $4
-	str	r1, [r0]
-	add	r0, r0, $4
-	str	r1, [r0]
-#endif
-
-	/*------------------------------------------------------*
-	 * PLL0 Initialization - works only in non-secure devices
-	 *------------------------------------------------------*/
-
-     /* TODO: Write the kick values and the PLL master lock bits */
-
-	/* Select OSCIN in clockmode bit in PLLCTL register. This is the only 
-     * clock mode supported on DA8xx
-     */
-	ldr	r6, PLL0_PLLCTL_ADDR
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Clear the PLLENSRC bit in PLLCTL */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-WaitPLL0Loop:
-	subs	r10, r10, $1
-	bne	WaitPLL0Loop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-   
-    /* disable PLL output */
-    mov r7, $0x10
-    orr r8, r8, r7
-    str r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-    /* Wait for the PLL stabilization time - 150us assumed */
-    mov r10, $0xE10
-PLLStableLoop:
-	subs	r10, r10, $1
-	bne PLLStableLoop
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL0_PLLM_ADDR
-	mov	r2, $0x18	/* 24 * 25 = 600MHz*/
-	str	r2, [r6]
-    
-	/* Program the POSTDIV Value */
-	ldr	r6, PLL0_POSTDIV_ADDR
-	mov	r3, $0x01
-	mov	r3, r3, lsl $15
-    orr r3, r3, $0x01
-	str	r3, [r6]
-
-    /* Program the SYSCLKx dividedrs */
-
-    /* Following defaults are good:
-     * SYSCLK1 = /1 => 300MHz GEM 
-     * SYSCLK2 = /2 => 150MHz EDMA, MMC/SD, UART1/2, SPI1 
-     * SYSCLK3 = /3 => 100MHz Possible EMIF2.5
-     * SYSCLK4 = /4 => 75MHz  INTC, PSC, EMAC, USB 1.1, I2C1
-     * SYSCLK5 = /3 => 100MHz Possible EMIF3.0 (use DIV4p5)
-     * SYSCLK6 = /1 => 300MHz ARM
-     * SYSCLK7 = /6 => 50MHz  RMII Ref Clk
-     * SYSCLK8 = /6 => 50MHz  Dont use
-     * SYSCLK9 = /6 => 50MHz  Dont use
-     * AUXCLK FIXED => 24Mhz  Timer 0/1, 12C0, McASP AuxClk
-     */
-     
-	/* Wait for PLL to Reset Properly - 128 OSCIN cycles*/
-	mov	r10, $128
-ResetPPL2Loop:
-	subs	r10, r10, $1
-	bne	ResetPPL2Loop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL0_PLLCTL_ADDR
-	ldr	r8, [r6]
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-PLL0Lock:
-	subs	r10, r10, $1
-	bne	PLL0Lock
-
-	/* Enable the PLL */
-	ldr	r6, PLL0_PLLCTL_ADDR
-	ldr	r8, [r6]
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	/*------------------------------------------------------*
-	 * Setup the pinmux for DDR2			                *
-	 *------------------------------------------------------*/	 
-
-	ldr	r0, PINMUX1_ADDR
-	ldr	r1, PINMUX1_VAL
-	str	r1, [r0]
-
-	ldr	r0, PINMUX2_ADDR
-	ldr	r1, PINMUX2_VAL
-	str	r1, [r0]
-
-	ldr	r0, PINMUX5_ADDR
-	ldr	r1, PINMUX5_VAL
-	str	r1, [r0]
-	
-	ldr	r0, PINMUX6_ADDR
-	ldr	r1, PINMUX6_VAL
-	str	r1, [r0]
-
-	ldr r8, PINMUX7_FLAG_CLEAR
-	ldr r7, PINMUX7_VAL
-	ldr r0, PINMUX7_ADDR
-	ldr r1, [r0]
-	and r1, r1, r8
-	orr r1, r1, r7
-	str r1, [r0]
-
-
-	/*------------------------------------------------------*
-	 * Get the EMIF3 out of reset			                *
-	 *------------------------------------------------------*/	 
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PSC1_PTCMD_ADDR
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop0:
-	ldr	r6, PSC1_PTSTAT_ADDR
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop0
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop0:
-	ldr	r6, MDSTAT_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop0
-
-	/*------------------------------------------------------*
-	 * Put the EMIF3 in reset			                *
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PSC1_PTCMD_ADDR
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop1:
-	ldr	r6, PSC1_PTSTAT_ADDR
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop1
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop1:
-	ldr	r6, MDSTAT_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x01
-	bne	checkDDRStatClkStop1
-
-    nop
-    nop
-    
-	/*------------------------------------------------------*
-	 * Get the EMIF3 out of reset			                *
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PSC1_PTCMD_ADDR
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-	ldr	r6, PSC1_PTSTAT_ADDR
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-	ldr	r6, MDSTAT_EMIF3
-	ldr	r7, [r6]
-	and	r7, r7, $0x1f
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop2
-
-    nop
-    nop
-
-    /*-----------------------------------------------------*
-     * Wait before programing the SDRAM timimg values      *
-     *-----------------------------------------------------*/
-
-     ldr r10, EMIF3_TIMING_WAIT_VAL
-emif3TimingWait:
-    sub r10, r10, $0x1
-    cmp r10, $0x0
-    bne emif3TimingWait
-
-	/*------------------------------------------------------*
-	 * Program EMIF3 MMRs for 133MHz SDRAM Setting			*
-	 *------------------------------------------------------*/
-
-	/* Program SDRAM Bank Config Register */
-	ldr	r6, SDCFG
-	ldr	r7, SDCFG_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-0 Config Register */
-	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-1 Config Register */
-	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program the SDRAM Bank Config Control Register */
-	ldr	r10, MASK_VAL
-	ldr	r8, SDCFG
-	ldr	r9, SDCFG_VAL
-	and	r9, r9, r10
-	str	r9, [r8]
-
-	/* Program SDRAM SDREF Config Register */
-	ldr	r6, SDREF
-	ldr	r7, SDREF_VAL
-	str	r7, [r6]
-
-	/* Issue a Dummy DDR2 read/write */
-	ldr	r8, DDR2_START_ADDR
-	ldr	r7, DUMMY_VAL
-	str	r7, [r8]
-	ldr	r7, [r8]
-
-	/*  DDR Writes and Reads */
-	ldr	r6, CFGTEST
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	nop
-	nop
-	nop
-	nop
-
-	/*
-	 * Call board-specific lowlevel init.
- 	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-.ltorg
-
-PINMUX1_ADDR:
-	.word PINMUX1
-PINMUX2_ADDR:
-	.word PINMUX2
-PINMUX5_ADDR:
-	.word PINMUX5
-PINMUX6_ADDR:
-	.word PINMUX6
-PINMUX7_ADDR:
-	.word PINMUX7
-PINMUX1_VAL:
-	.word 0x11111111
-PINMUX2_VAL:
-	.word 0x01111111
-PINMUX5_VAL:
-	.word 0x11111110
-PINMUX6_VAL:
-	.word 0x11111111
-PINMUX7_FLAG_CLEAR:
-	.word 0xFFFFF000
-PINMUX7_VAL:
-	.word 0x111
-	
-
-MDCTL_EMIF3:
-	.word	PSC1_MDCTL + 4 * 6
-MDSTAT_EMIF3:
-	.word   PSC1_MDSTAT + 4 * 6
-
-PSC1_PTCMD_ADDR:
-	.word	PSC1_PTCMD
-PSC1_PTSTAT_ADDR:
-	.word	PSC1_PTSTAT
-
-INTC_GLB_EN_ADDR:
-    .word	INTC_GLB_EN  
-INTC_EN_CLR0_ADDR:
-	.word	INTC_EN_CLR0
-INTC_HINT_EN_ADDR:
-	.word	INTC_HINT_EN		
-
-PSC_FLAG_CLEAR:
-	.word	0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-	.word	0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-SDREF:
-	.word	DAVINCI_DDR_EMIF_CTRL_BASE + 0xc
-SDREF_VAL:
-	.word	0x000005c3
-SDCFG:
-	.word	DAVINCI_DDR_EMIF_CTRL_BASE + 0x8
-SDCFG_VAL:
-#ifdef	SDRAM_4BANKS_10COLS
-	.word	0x00178622
-#elif defined SDRAM_8BANKS_10COLS
-	.word	0x00178632
-#else
-#error "Unknown SDRAM configuration!!!"
-#endif
-SDTIM0:
-	.word	DAVINCI_DDR_EMIF_CTRL_BASE + 0x10
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
-SDTIM1:
-	.word	DAVINCI_DDR_EMIF_CTRL_BASE + 0x14
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
-CFGTEST:
-	.word	DAVINCI_DDR_EMIF_DATA_BASE + 0x10000
-MASK_VAL:
-	.word	0x00000fff
-EMIF3_TIMING_WAIT_VAL:
-	.word 990000
-
-PLL_CLKSRC_MASK:
-	.word	0xfffffeff	/* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-	.word	0xffffffdf	/* Select the PLLEN source */
-PLL_BYPASS_MASK:
-	.word	0xfffffffe	/* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-	.word	0xfffffff7	/* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-	.word	0xfffffffd	/* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-	.word	0xffffffef	/* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-	.word	2000
-
-/* PLL0 MMRs */
-PLL0_PLLCTL_ADDR:
-	.word	PLL0_PLLCTL
-PLL0_PLLM_ADDR:
-	.word	PLL0_PLLM
-PLL0_POSTDIV_ADDR:
-	.word	PLL0_POSTDIV
-
-DDR2_START_ADDR:
-	.word	0xc0000000
-DUMMY_VAL:
-	.word	0xa55aa55a
diff --git a/cpu/arm926ejs/da850/nand.c b/cpu/arm926ejs/da850/nand.c
deleted file mode 100644
index 014e2b0c11..0000000000
--- a/cpu/arm926ejs/da850/nand.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * NAND driver for TI DaVinci based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
- */
-
-/*
- *
- * linux/drivers/mtd/nand/nand_davinci.c
- *
- * NAND Flash Driver
- *
- * Copyright (C) 2006 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
- *
- *  Overview:
- *   This is a device driver for the NAND flash device found on the
- *   DaVinci board which utilizes the Samsung k9k2g08 part.
- *
- Modifications:
- ver. 1.0: Feb 2005, Vinod/Sudhakar
- -
- *
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_USE_NAND
-#if !defined(CONFIG_NAND_LEGACY)
-
-#include <nand.h>
-#include <asm/arch/nand_defs.h>
-#include <asm/arch/emif_defs.h>
-
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct		nand_chip *this = mtd->priv;
-	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
-
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			IO_ADDR_W |= MASK_CLE;
-		if ( ctrl & NAND_ALE )
-			IO_ADDR_W |= MASK_ALE;
-		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-/* Set WP on deselect, write enable on select */
-static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
-{
-#define GPIO_SET_DATA01	0x01c67018
-#define GPIO_CLR_DATA01	0x01c6701c
-#define GPIO_NAND_WP	(1 << 4)
-#ifdef SONATA_BOARD_GPIOWP
-	if (chip < 0) {
-		REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
-	} else {
-		REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
-	}
-#endif
-}
-
-#ifdef CONFIG_SYS_NAND_HW_ECC
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-/* Linux-compatible ECC uses MTD defaults. */
-/* These layouts are not compatible with Linux or RBL/UBL. */
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-static struct nand_ecclayout davinci_nand_ecclayout = {
-	.eccbytes = 12,
-	.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
-	.oobfree = {
-		{.offset = 2, .length = 6},
-		{.offset = 12, .length = 12},
-		{.offset = 28, .length = 12},
-		{.offset = 44, .length = 12},
-		{.offset = 60, .length = 4}
-	}
-};
-#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
-static struct nand_ecclayout davinci_nand_ecclayout = {
-	.eccbytes = 3,
-	.eccpos = {0, 1, 2},
-	.oobfree = {
-		{.offset = 6, .length = 2},
-		{.offset = 8, .length = 8}
-	}
-};
-#else
-#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
-#endif
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-
-static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
-{
-	emifregs	emif_addr;
-	int		dummy;
-
-	emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
-	dummy = emif_addr->NANDF1ECC;
-	dummy = emif_addr->NANDF2ECC;
-	dummy = emif_addr->NANDF3ECC;
-	dummy = emif_addr->NANDF4ECC;
-
-	emif_addr->NANDFCR |= (1 << 8);
-}
-
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
-	u_int32_t	ecc = 0;
-	emifregs	emif_base_addr;
-
-	emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
-	if (region == 1)
-		ecc = emif_base_addr->NANDF1ECC;
-	else if (region == 2)
-		ecc = emif_base_addr->NANDF2ECC;
-	else if (region == 3)
-		ecc = emif_base_addr->NANDF3ECC;
-	else if (region == 4)
-		ecc = emif_base_addr->NANDF4ECC;
-
-	return(ecc);
-}
-
-static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
-{
-	u_int32_t		tmp;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-	/*
-	 * This is not how you should read ECCs on large page Davinci devices.
-	 * The region parameter gets you ECCs for flash chips on different chip
-	 * selects, not the 4x512 byte pages in a 2048 byte page.
-	 *
-	 * Preserved for backwards compatibility though.
-	 */
-
-	int			region, n;
-	struct nand_chip	*this = mtd->priv;
-
-	n = (this->ecc.size/512);
-
-	region = 1;
-	while (n--) {
-		tmp = nand_davinci_readecc(mtd, region);
-		*ecc_code++ = tmp;
-		*ecc_code++ = tmp >> 16;
-		*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
-		region++;
-	}
-#else
-	const int region = 1;
-
-	tmp = nand_davinci_readecc(mtd, region);
-
-	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
-	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
-	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
-
-	/* Invert so that erased block ECC is correct */
-	tmp = ~tmp;
-
-	*ecc_code++ = tmp;
-	*ecc_code++ = tmp >>  8;
-	*ecc_code++ = tmp >> 16;
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-	return(0);
-}
-
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
-{
-	u_int32_t	tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
-
-	ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
-	ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
-	ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
-}
-
-static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
-{
-	u_int32_t	i;
-	u_int8_t	tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
-	u_int8_t	comp0_bit[8], comp1_bit[8], comp2_bit[8];
-	u_int8_t	ecc_bit[24];
-	u_int8_t	ecc_sum = 0;
-	u_int8_t	find_bit = 0;
-	u_int32_t	find_byte = 0;
-	int		is_ecc_ff;
-
-	is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
-
-	nand_davinci_gen_true_ecc(ecc_nand);
-	nand_davinci_gen_true_ecc(ecc_calc);
-
-	for (i = 0; i <= 2; i++) {
-		*(ecc_nand + i) = ~(*(ecc_nand + i));
-		*(ecc_calc + i) = ~(*(ecc_calc + i));
-	}
-
-	for (i = 0; i < 8; i++) {
-		tmp0_bit[i] = *ecc_nand % 2;
-		*ecc_nand = *ecc_nand / 2;
-	}
-
-	for (i = 0; i < 8; i++) {
-		tmp1_bit[i] = *(ecc_nand + 1) % 2;
-		*(ecc_nand + 1) = *(ecc_nand + 1) / 2;
-	}
-
-	for (i = 0; i < 8; i++) {
-		tmp2_bit[i] = *(ecc_nand + 2) % 2;
-		*(ecc_nand + 2) = *(ecc_nand + 2) / 2;
-	}
-
-	for (i = 0; i < 8; i++) {
-		comp0_bit[i] = *ecc_calc % 2;
-		*ecc_calc = *ecc_calc / 2;
-	}
-
-	for (i = 0; i < 8; i++) {
-		comp1_bit[i] = *(ecc_calc + 1) % 2;
-		*(ecc_calc + 1) = *(ecc_calc + 1) / 2;
-	}
-
-	for (i = 0; i < 8; i++) {
-		comp2_bit[i] = *(ecc_calc + 2) % 2;
-		*(ecc_calc + 2) = *(ecc_calc + 2) / 2;
-	}
-
-	for (i = 0; i< 6; i++)
-		ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
-
-	for (i = 0; i < 8; i++)
-		ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
-
-	for (i = 0; i < 8; i++)
-		ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
-
-	ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
-	ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
-
-	for (i = 0; i < 24; i++)
-		ecc_sum += ecc_bit[i];
-
-	switch (ecc_sum) {
-		case 0:
-			/* Not reached because this function is not called if
-			   ECC values are equal */
-			return 0;
-		case 1:
-			/* Uncorrectable error */
-			MTDDEBUG (MTD_DEBUG_LEVEL0,
-			          "ECC UNCORRECTED_ERROR 1\n");
-			return(-1);
-		case 12:
-			/* Correctable error */
-			find_byte = (ecc_bit[23] << 8) +
-				(ecc_bit[21] << 7) +
-				(ecc_bit[19] << 6) +
-				(ecc_bit[17] << 5) +
-				(ecc_bit[15] << 4) +
-				(ecc_bit[13] << 3) +
-				(ecc_bit[11] << 2) +
-				(ecc_bit[9]  << 1) +
-				ecc_bit[7];
-
-			find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
-
-			MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
-			          "error at offset: %d, bit: %d\n",
-			          find_byte, find_bit);
-
-			page_data[find_byte] ^= (1 << find_bit);
-
-			return(0);
-		default:
-			if (is_ecc_ff) {
-				if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
-					return(0);
-			}
-			MTDDEBUG (MTD_DEBUG_LEVEL0,
-			          "UNCORRECTED_ERROR default\n");
-			return(-1);
-	}
-}
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-
-static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
-{
-	struct nand_chip *this = mtd->priv;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-	int			block_count = 0, i, rc;
-
-	block_count = (this->ecc.size/512);
-	for (i = 0; i < block_count; i++) {
-		if (memcmp(read_ecc, calc_ecc, 3) != 0) {
-			rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
-			if (rc < 0) {
-				return(rc);
-			}
-		}
-		read_ecc += 3;
-		calc_ecc += 3;
-		dat += 512;
-	}
-#else
-	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
-					  (read_ecc[2] << 16);
-	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
-					  (calc_ecc[2] << 16);
-	u_int32_t diff = ecc_calc ^ ecc_nand;
-
-	if (diff) {
-		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
-			/* Correctable error */
-			if ((diff >> (12 + 3)) < this->ecc.size) {
-				uint8_t find_bit = 1 << ((diff >> 12) & 7);
-				uint32_t find_byte = diff >> (12 + 3);
-
-				dat[find_byte] ^= find_bit;
-				MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
-					 "bit ECC error at offset: %d, bit: "
-					 "%d\n", find_byte, find_bit);
-				return 1;
-			} else {
-				return -1;
-			}
-		} else if (!(diff & (diff - 1))) {
-			/* Single bit ECC error in the ECC itself,
-			   nothing to fix */
-			MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
-				 "ECC.\n");
-			return 1;
-		} else {
-			/* Uncorrectable error */
-			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
-			return -1;
-		}
-	}
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-	return(0);
-}
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-
-static int nand_davinci_dev_ready(struct mtd_info *mtd)
-{
-	emifregs	emif_addr;
-
-	emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
-	return(emif_addr->NANDFSR & 0x1);
-}
-
-static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
-{
-	while(!nand_davinci_dev_ready(mtd)) {;}
-	*NAND_CE0CLE = NAND_STATUS;
-	return(*NAND_CE0DATA);
-}
-
-static void nand_flash_init(void)
-{
-	u_int32_t	acfg1 = 0x3ffffffc;
-	u_int32_t	acfg2 = 0x3ffffffc;
-	u_int32_t	acfg3 = 0x3ffffffc;
-	u_int32_t	acfg4 = 0x3ffffffc;
-	emifregs	emif_regs;
-
-	/*------------------------------------------------------------------*
-	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
-	 *                                                                  *
-	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
-	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
-	 *                                                                  *
-	 *------------------------------------------------------------------*/
-	 acfg1 = 0
-		| (0 << 31 )	/* selectStrobe */
-		| (0 << 30 )	/* extWait */
-		| (1 << 26 )	/* writeSetup	10 ns */
-		| (3 << 20 )	/* writeStrobe	40 ns */
-		| (1 << 17 )	/* writeHold	10 ns */
-		| (1 << 13 )	/* readSetup	10 ns */
-		| (5 << 7 )	/* readStrobe	60 ns */
-		| (1 << 4 )	/* readHold	10 ns */
-		| (3 << 2 )	/* turnAround	?? ns */
-		| (0 << 0 )	/* asyncSize	8-bit bus */
-		;
-
-	emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
-	emif_regs->AWCCR |= 0x10000000;
-	emif_regs->AB1CR = acfg1;	/* 0x08244128 */;
-	emif_regs->AB2CR = acfg2;
-	emif_regs->AB3CR = acfg3;
-	emif_regs->AB4CR = acfg4;
-	emif_regs->NANDFCR = 0x00000101;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	nand->IO_ADDR_R   = (void  __iomem *)NAND_CE0DATA;
-	nand->IO_ADDR_W   = (void  __iomem *)NAND_CE0DATA;
-	nand->chip_delay  = 0;
-	nand->select_chip = nand_davinci_select_chip;
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-	nand->options	  = NAND_USE_FLASH_BBT;
-#endif
-#ifdef CONFIG_SYS_NAND_HW_ECC
-	nand->ecc.mode = NAND_ECC_HW;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-	nand->ecc.layout  = &davinci_nand_ecclayout;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-	nand->ecc.size = 2048;
-	nand->ecc.bytes = 12;
-#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
-	nand->ecc.size = 512;
-	nand->ecc.bytes = 3;
-#else
-#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
-#endif
-#else
-	nand->ecc.size = 512;
-	nand->ecc.bytes = 3;
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-	nand->ecc.calculate = nand_davinci_calculate_ecc;
-	nand->ecc.correct  = nand_davinci_correct_data;
-	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
-#else
-	nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-
-	/* Set address of hardware control function */
-	nand->cmd_ctrl = nand_davinci_hwcontrol;
-
-	nand->dev_ready = nand_davinci_dev_ready;
-	nand->waitfunc = nand_davinci_waitfunc;
-
-	nand_flash_init();
-
-	return(0);
-}
-
-#else
-#error "U-Boot legacy NAND support not available for DaVinci chips"
-#endif
-#endif	/* CONFIG_SYS_USE_NAND */
diff --git a/cpu/arm926ejs/da850/reset.S b/cpu/arm926ejs/da850/reset.S
deleted file mode 100644
index a687d44035..0000000000
--- a/cpu/arm926ejs/da850/reset.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Processor reset using WDT for TI TMS320DM644x SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, WDT_TGCR
-	mov	r1, $0x08
-	str	r1, [r0]
-	ldr	r1, [r0]
-	orr	r1, r1, $0x03
-	str	r1, [r0]
-	mov	r1, $0
-	ldr	r0, WDT_TIM12
-	str	r1, [r0]
-	ldr	r0, WDT_TIM34
-	str	r1, [r0]
-	ldr	r0, WDT_PRD12
-	str	r1, [r0]
-	ldr	r0, WDT_PRD34
-	str	r1, [r0]
-	ldr	r0, WDT_TCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x40
-	str	r1, [r0]
-	ldr	r0, WDT_WDTCR
-	ldr	r1, [r0]
-	orr	r1, r1, $0x4000
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL1
-	str	r1, [r0]
-	ldr	r1, WDTCR_VAL2
-	str	r1, [r0]
-	nop
-	nop
-	nop
-	nop
-reset_cpu_loop:
-	b	reset_cpu_loop
-
-WDT_TGCR:
-	.word	0x01c21c24
-WDT_TIM12:
-	.word	0x01c21c10
-WDT_TIM34:
-	.word	0x01c21c14
-WDT_PRD12:
-	.word	0x01c21c18
-WDT_PRD34:
-	.word	0x01c21c1c
-WDT_TCR:
-	.word	0x01c21c20
-WDT_WDTCR:
-	.word	0x01c21c28
-WDTCR_VAL1:
-	.word	0xa5c64000
-WDTCR_VAL2:
-	.word	0xda7e4000
diff --git a/cpu/arm926ejs/da850/timer.c b/cpu/arm926ejs/da850/timer.c
deleted file mode 100644
index 773735a1c8..0000000000
--- a/cpu/arm926ejs/da850/timer.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm926ejs.h>
-
-typedef volatile struct {
-	u_int32_t	pid12;
-	u_int32_t	emumgt;
-	u_int32_t	na1;
-	u_int32_t	na2;
-	u_int32_t	tim12;
-	u_int32_t	tim34;
-	u_int32_t	prd12;
-	u_int32_t	prd34;
-	u_int32_t	tcr;
-	u_int32_t	tgcr;
-	u_int32_t	wdtcr;
-} davinci_timer;
-
-davinci_timer		*timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV	16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	timer->tcr = 0x0;
-	timer->tgcr = 0x0;
-	timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
-	timer->tim34 = 0x0;
-	timer->prd34 = TIMER_LOAD_VAL;
-	lastinc = 0;
-	timestamp = 0;
-	timer->tcr = 2 << 22;
-
-	return(0);
-}
-
-void reset_timer(void)
-{
-	timer->tcr = 0x0;
-	timer->tim34 = 0;
-	lastinc = 0;
-	timestamp = 0;
-	timer->tcr = 2 << 22;
-}
-
-static ulong get_timer_raw(void)
-{
-	ulong now = timer->tim34;
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
-	return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= (1000 * TIM_CLK_DIV);
-
-	endtime = get_timer_raw() + tmo;
-
-	do {
-		ulong now = get_timer_raw();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return(get_timer(0));
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}