diff options
| author | Chris Packham <judge.packham@gmail.com> | 2019-04-11 22:22:50 +1200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2019-04-12 07:04:18 +0200 |
| commit | 0d0df46ee7323506df2e38738c52d68699c2abca (patch) | |
| tree | 61ef85055d53ab675f5b1489121891bcdd68ab38 /drivers/ddr | |
| parent | 237b629e4cd8fd8ffa9664a1b71b7eda1d2f2179 (diff) | |
arm: mvebu: Add Marvell's integrated CPUs
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/axp/xor_regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/axp/xor_regs.h b/drivers/ddr/marvell/axp/xor_regs.h index db5c419673..d779e56418 100644 --- a/drivers/ddr/marvell/axp/xor_regs.h +++ b/drivers/ddr/marvell/axp/xor_regs.h @@ -13,7 +13,11 @@ #define XOR_UNIT(chan) ((chan) >> 1) #define XOR_CHAN(chan) ((chan) & 1) +#ifdef CONFIG_ARMADA_MSYS +#define MV_XOR_REGS_OFFSET(unit) (0xF0800) +#else #define MV_XOR_REGS_OFFSET(unit) (0x60900) +#endif #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) /* XOR Engine Control Register Map */ |