diff options
| author | York Sun <york.sun@nxp.com> | 2018-01-29 09:44:34 -0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-01-30 09:14:06 -0800 |
| commit | d46ec0bbaf1a38711b493266f49bb26ac9157d8a (patch) | |
| tree | 582456ba24f29df02ecb9169e343a9afbb772bae /drivers/ddr | |
| parent | 426230a65f2dd62c3b6c1509e9775d5500db20d3 (diff) | |
drivers/ddr/fsl: Fix workaround for A009803
Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index b3a27ec5a8..7df9178415 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -210,7 +210,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ ddr_out32(&ddr->ddr_sdram_rcw_2, - regs->ddr_sdram_rcw_2 & ~0x0f000000); + regs->ddr_sdram_rcw_2 & ~0xf0); } ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED); |