diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-07-13 00:25:35 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-07-19 19:52:13 +0200 |
| commit | 83fd908f28ca94baf095ba64b4b8a116dd473cb7 (patch) | |
| tree | 2bda5b82202dd8ccae1f94662ca937a9ee0a1320 /drivers/serial | |
| parent | 4beba0668890f23373863dc27230679addd20689 (diff) | |
dm: imx: serial: Support DTE mode when using driver model
The MXC UART IP can be run in DTE or DCE mode. This depends on the
board wiring and the pinmux used and hence is board specific. This
extends platform data with a new field to choose wheather DTE
mode shall be used.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/serial_mxc.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 1563bb3665..1960bbc5ae 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -76,6 +76,7 @@ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ +#define UFCR_DCEDTE (1<<6) /* DTE mode select */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -150,6 +151,7 @@ static void mxc_serial_setbrg(void) __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) | (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF); + __REG(UART_PHYS + UFCR) |= UFCR_DCEDTE; __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); @@ -269,8 +271,13 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate) struct mxc_serial_platdata *plat = dev->platdata; struct mxc_uart *const uart = plat->reg; u32 clk = imx_get_uartclk(); + u32 tmp; + + tmp = 4 << UFCR_RFDIV_SHF; + if (plat->use_dte) + tmp |= UFCR_DCEDTE; + writel(tmp, &uart->fcr); - writel(4 << 7, &uart->fcr); /* divide input clock by 2 */ writel(0xf, &uart->bir); writel(clk / (2 * baudrate), &uart->bmr); |