diff options
| author | Tom Rini <trini@konsulko.com> | 2015-11-16 08:35:38 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-11-16 08:35:38 -0500 |
| commit | 98e73c834467ef6f1d3e9a8102745e16b3128ac1 (patch) | |
| tree | a73931f3865dea561750d6a738dbd1738ba8c666 /drivers | |
| parent | 618a51e9aefe1e03f498ea48bfab70a0b2c9be39 (diff) | |
| parent | ec26c1eef735befb7011c24e08e6310ab6dc9be6 (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/video/mxsfb.c | 19 |
2 files changed, 25 insertions, 1 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 101a619558..b92da4e202 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -83,6 +83,13 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +config MXC_OCOTP + bool "Enable MXC OCOTP Driver" + help + If you say Y here, you will get support for the One Time + Programmable memory pages that are stored on the some + Freescale i.MX processors. + config PCA9551_LED bool "Enable PCA9551 LED driver" help diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 03b0f88acf..ddbb118d70 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -55,7 +55,7 @@ static void mxs_lcd_init(GraphicDevice *panel, uint8_t valid_data = 0; /* Kick in the LCDIF clock */ - mxs_set_lcdclk(PS2KHZ(mode->pixclock)); + mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); /* Restart the LCDIF block */ mxs_reset_block(®s->hw_lcdif_ctrl_reg); @@ -131,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel, writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); } +void lcdif_power_down(void) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + int timeout = 1000000; + + writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg); + writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg); + writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr); + while (--timeout) { + if (readl(®s->hw_lcdif_ctrl1_reg) & + LCDIF_CTRL1_VSYNC_EDGE_IRQ) + break; + udelay(1); + } + mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg); +} + void *video_hw_init(void) { int bpp = -1; |