diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2015-04-22 15:43:40 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2015-04-22 15:43:40 +0200 |
| commit | 0440936084e5f467b55f56d7d1fa8660732587bd (patch) | |
| tree | 1e73ad40d820f1829c1bfd5ff3b91e71105f14de /drivers | |
| parent | 226245bd56adc631d9a1d0c1297e78d819ea478f (diff) | |
video: dcu: enable pixel clock after initialization
When enabling the DCU and pixel clock, the test mode is activated
since this is the reset configuration. The test mode immediately
shows a red screen on a LCD. A moment later, the DCU gets
initialized properly.
This patch enables the pixel clock after initialization of the DCU
control register. This avoids this initial flicker on LCD screens.
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/fsl_dcu_fb.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index badd7f504a..530656e190 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -206,8 +206,6 @@ static void reset_total_layers(void) dcu_write32(®s->ctrldescl[i][10], 0); #endif } - - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); } static int layer_ctrldesc_init(int index, u32 pixel_format) @@ -261,8 +259,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); - return 0; } @@ -280,8 +276,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, memset(info.screen_base, 0, info.screen_size); reset_total_layers(); - div = dcu_set_pixel_clock(info.var.pixclock); - dcu_write32(®s->div_ratio, (div - 1)); dcu_write32(®s->disp_size, DCU_DISP_SIZE_DELTA_Y(info.var.yres) | @@ -320,6 +314,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, layer_ctrldesc_init(0, pixel_format); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(®s->div_ratio, (div - 1)); + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); + return 0; } |