diff options
| author | BJ DevOps Team <bjdevops@NXP1.onmicrosoft.com> | 2022-10-11 10:08:37 +0200 |
|---|---|---|
| committer | BJ DevOps Team <bjdevops@NXP1.onmicrosoft.com> | 2022-10-11 10:08:37 +0200 |
| commit | 04bca82019c6235214d533a420b6f4535a2f5d8b (patch) | |
| tree | 0971e667ea4b986398c4c23bd75d1a3ff1a053d8 /drivers | |
| parent | ead1e6a6c63f0dd1a51ac4b992dd26ec44d977c1 (diff) | |
| parent | c244bdfd76c524a0fbaab25138ebd86e2be033a5 (diff) | |
Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04
* origin/imx_v2022.04:
LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature
LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/imx/imx9/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/ddr/imx/imx9/ddr_init.c | 35 |
2 files changed, 41 insertions, 0 deletions
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index b1795eec35..0c2ee89c31 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -17,6 +17,12 @@ config IMX9_DRAM_PM_COUNTER help Enable DDR controller performance monitor counter for reference events. +config IMX9_DRAM_INLINE_ECC + bool "Enable DDR INLINE ECC feature" + default n + help + Select to enable DDR INLINE ECC feature + config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" help diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 7cf1142f9a..17b4b259ac 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -197,6 +197,37 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) writel(tmp_t, REG_DDR_TIMING_CFG_4); } +void update_inline_ecc_setting(void) +{ + u32 val, sa, ea; + + val = readl(REG_DDR_CS0_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS0_BNDS); + } + + val = readl(REG_DDR_CS1_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS1_BNDS); + } + + /* Enable Inline ECC */ + setbits_le32(REG_DDR_ERR_EN, BIT(31) | BIT(30)); + + /* Enable data initialization */ + setbits_le32(REG_DDR_SDRAM_CFG2, BIT(4)); +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int initial_drate; @@ -233,6 +264,10 @@ int ddr_init(struct dram_timing_info *dram_timing) update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC + update_inline_ecc_setting(); +#endif + #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif |