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| author | Ye Li <ye.li@nxp.com> | 2022-08-16 17:24:36 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-08-17 14:35:50 +0800 |
| commit | c3d1fa0d58c157351600ae736ee85192119c58d2 (patch) | |
| tree | f0d1960040339c46d2777b7e84bed020be0c2e2d /drivers | |
| parent | 81a29ec1a12e4be50428a7f30a25382be8a56ba1 (diff) | |
LFU-385 misc: s4mu: Update MU TR registers count
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/sentinel/s4mu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c index bf0f15de24..535eb33265 100644 --- a/drivers/misc/sentinel/s4mu.c +++ b/drivers/misc/sentinel/s4mu.c @@ -22,7 +22,7 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4 void mu_hal_init(ulong base) @@ -66,7 +66,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) int ret; u32 count = 10; - assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT); debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr)); |