diff options
author | Bai Ping <ping.bai@nxp.com> | 2018-09-29 14:50:25 +0800 |
---|---|---|
committer | Bai Ping <ping.bai@nxp.com> | 2018-10-01 17:25:25 +0800 |
commit | 65fed31a520edf2f19f7fd1c10ff317ce4496ce6 (patch) | |
tree | cf4466c0ace84e4974ea20b4d201ce2971cbf347 /drivers | |
parent | 4e9048d810eb92c395453a28dea2a44961e08948 (diff) |
MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow
Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ddr/imx8m/Makefile | 1 | ||||
-rw-r--r-- | drivers/ddr/imx8m/ddr4_init.c | 98 | ||||
-rw-r--r-- | drivers/ddr/imx8m/ddrphy_utils.c | 6 |
3 files changed, 105 insertions, 0 deletions
diff --git a/drivers/ddr/imx8m/Makefile b/drivers/ddr/imx8m/Makefile index 9e4a6992a1..079e143f6d 100644 --- a/drivers/ddr/imx8m/Makefile +++ b/drivers/ddr/imx8m/Makefile @@ -7,4 +7,5 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o endif diff --git a/drivers/ddr/imx8m/ddr4_init.c b/drivers/ddr/imx8m/ddr4_init.c new file mode 100644 index 0000000000..47b21441d2 --- /dev/null +++ b/drivers/ddr/imx8m/ddr4_init.c @@ -0,0 +1,98 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8m_ddr.h> +#include <asm/arch/sys_proto.h> + +void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + volatile unsigned int tmp_t; + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */ + + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */ + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */ + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + /* config the uMCTL2's registers */ + ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + /* RESET: <ctn> DEASSERTED */ + /* RESET: <a Port 0 DEASSERTED(0) */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_PWRCTL(0), 0x00000aa); + reg32_write(DDRC_SWCTL(0), 0x00000000); + + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* config the DDR PHY's registers */ + ddr_cfg_phy(dram_timing); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00020097); + } while (tmp_t != 0); + + reg32_write(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0)))) + ; + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x0000088); + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* wait SWSTAT.sw_done_ack to 1 */ + while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0)))) + ; + + /* wait STAT to normal state */ + while (0x1 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + reg32_write(DDRC_PWRCTL(0), 0x0000088); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */ + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c index e77945b1b0..c1eace23f1 100644 --- a/drivers/ddr/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -1,3 +1,9 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + #include <common.h> #include <errno.h> #include <asm/io.h> |