diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-11-01 17:50:34 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2018-11-02 20:50:11 -0500 |
| commit | cb43368096b45abb2e20d169f73d57f60fb75204 (patch) | |
| tree | 45d56b3ae02ff21906d84be49cafcd259f7c09e1 /drivers | |
| parent | 048327a4f276289c76b7e4280e332f79cb6aa10e (diff) | |
MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/imx8m/ddrphy_utils.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/imx8m/helper.c | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c index c1eace23f1..b7c314ec98 100644 --- a/drivers/ddr/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx8m/ddrphy_utils.c @@ -108,6 +108,10 @@ void wait_ddrphy_training_complete(void) void ddrphy_init_set_dfi_clk(unsigned int drate) { switch (drate) { + case 3200: + dram_pll_init(DRAM_PLL_OUT_800M); + dram_disable_bypass(); + break; case 3000: dram_pll_init(DRAM_PLL_OUT_750M); dram_disable_bypass(); @@ -120,6 +124,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(DRAM_PLL_OUT_400M); dram_disable_bypass(); break; + case 667: + dram_pll_init(DRAM_PLL_OUT_167M); + dram_disable_bypass(); + break; case 400: dram_enable_bypass(DRAM_BYPASSCLK_400M); break; diff --git a/drivers/ddr/imx8m/helper.c b/drivers/ddr/imx8m/helper.c index f5d1c37f82..dff1e2a962 100644 --- a/drivers/ddr/imx8m/helper.c +++ b/drivers/ddr/imx8m/helper.c @@ -131,6 +131,10 @@ void dram_config_save(struct dram_timing_info *timing_info, saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num; saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + cfg = (struct dram_cfg_param *)(saved_timing_base + sizeof(*timing_info)); /* save ddrc config */ |