diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2018-12-20 17:55:41 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-02-18 13:00:54 +0100 |
| commit | 7997599e2df64c8fb450bc03f2d618adbde05f6e (patch) | |
| tree | 6316acdb2f882c04b7f079424a28b061db6ff585 /drivers | |
| parent | 473f55676a65e068ba82096f54cd1e9f16ecc006 (diff) | |
mmc: dwmmc: Poll for iDMAC TX/RX interrupt
Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/dw_mmc.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 7544b84ab6..93a836eac3 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -12,6 +12,7 @@ #include <memalign.h> #include <mmc.h> #include <dwmmc.h> +#include <wait_bit.h> #define PAGE_SIZE 4096 @@ -55,6 +56,9 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); + /* Clear IDMAC interrupt */ + dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF); + data_start = (ulong)cur_idmac; dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); @@ -340,6 +344,18 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, /* only dma mode need it */ if (!host->fifo_mode) { + if (data->flags == MMC_DATA_READ) + mask = DWMCI_IDINTEN_RI; + else + mask = DWMCI_IDINTEN_TI; + ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS, + mask, true, 1000, false); + if (ret) + debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n", + __func__, mask); + /* clear interrupts */ + dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK); + ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl &= ~(DWMCI_DMA_EN); dwmci_writel(host, DWMCI_CTRL, ctrl); @@ -494,6 +510,9 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); + if (!host->fifo_mode) + dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK); + return 0; } |