diff options
| author | Simon Glass <sjg@chromium.org> | 2016-09-12 23:18:56 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-09-16 17:27:19 -0400 |
| commit | e00f76cee906a48311d0c7c59b519b2e6a5c56f8 (patch) | |
| tree | bc9288e3b496e54e0cc771d0ee4a509d44f87c9b /include/configs/P1010RDB.h | |
| parent | d1c44bd6ccc5fac168a53929469aaf281ac62e3e (diff) | |
Convert CONFIG_SPL_SERIAL_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/P1010RDB.h')
| -rw-r--r-- | include/configs/P1010RDB.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ab55428b95..882e8a5495 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -19,7 +19,6 @@ #define CONFIG_NAND_FSL_IFC #ifdef CONFIG_SDCARD -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -46,7 +45,6 @@ #define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL @@ -73,7 +71,6 @@ #ifdef CONFIG_NAND #ifdef CONFIG_SECURE_BOOT #define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -93,7 +90,6 @@ #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_NAND_INIT -#define CONFIG_TPL_SERIAL_SUPPORT #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xD0001000 @@ -104,7 +100,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) #elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TEXT_BASE 0xff800000 |