Merge branch 'master-sync' of git://git.denx.de/u-boot-arm

37 files changed, 1763 insertions, 1215 deletions

diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index ac32510a30..acf12ea7a2 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -71,10 +71,12 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_SPI_BASE			(0x01c66800)
 #define DAVINCI_GPIO_BASE			(0x01c67000)
 #define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
+#if !defined(CONFIG_SOC_DM646X)
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
+#endif
 #define DAVINCI_DDR_BASE			(0x80000000)
 
 #ifdef CONFIG_SOC_DM644X
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 2246f801e5..34bd515b05 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -34,6 +34,8 @@ void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size);
 
 void watchdog_init(void);
 void set_muxconf_regs(void);
diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h
new file mode 100644
index 0000000000..f1aa44fd25
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/clk.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+void s5pc1xx_clock_init(void);
+
+extern unsigned long (*get_pll_clk)(int pllreg);
+extern unsigned long (*get_arm_clk)(void);
+extern unsigned long (*get_pclk)(void);
+
+#endif
diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h
new file mode 100644
index 0000000000..7b4eb89905
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/clock.h
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc100_clock {
+	unsigned int	apll_lock;
+	unsigned int	mpll_lock;
+	unsigned int	epll_lock;
+	unsigned int	hpll_lock;
+	unsigned char	res1[0xf0];
+	unsigned int	apll_con;
+	unsigned int	mpll_con;
+	unsigned int	epll_con;
+	unsigned int	hpll_con;
+	unsigned char	res2[0xf0];
+	unsigned int	src0;
+	unsigned int	src1;
+	unsigned int	src2;
+	unsigned int	src3;
+	unsigned char	res3[0xf0];
+	unsigned int	div0;
+	unsigned int	div1;
+	unsigned int	div2;
+	unsigned int	div3;
+	unsigned int	div4;
+	unsigned char	res4[0x1ec];
+	unsigned int	gate_d00;
+	unsigned int	gate_d01;
+	unsigned int	gate_d02;
+	unsigned char	res5[0x54];
+	unsigned int	gate_sclk0;
+	unsigned int	gate_sclk1;
+};
+
+struct s5pc110_clock {
+	unsigned int	apll_lock;
+	unsigned char	res1[0x4];
+	unsigned int	mpll_lock;
+	unsigned char	res2[0x4];
+	unsigned int	epll_lock;
+	unsigned char	res3[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res4[0xdc];
+	unsigned int	apll_con;
+	unsigned char	res5[0x4];
+	unsigned int	mpll_con;
+	unsigned char	res6[0x4];
+	unsigned int	epll_con;
+	unsigned char	res7[0xc];
+	unsigned int	vpll_con;
+	unsigned char	res8[0xdc];
+	unsigned int	src0;
+	unsigned int	src1;
+	unsigned int	src2;
+	unsigned int	src3;
+	unsigned char	res9[0xf0];
+	unsigned int	div0;
+	unsigned int	div1;
+	unsigned int	div2;
+	unsigned int	div3;
+	unsigned int	div4;
+	unsigned char	res10[0x1ec];
+	unsigned int	gate_d00;
+	unsigned int	gate_d01;
+	unsigned int	gate_d02;
+	unsigned char	res11[0x54];
+	unsigned int	gate_sclk0;
+	unsigned int	gate_sclk1;
+};
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h
new file mode 100644
index 0000000000..90485aaff2
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/cpu.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _S5PC1XX_CPU_H
+#define _S5PC1XX_CPU_H
+
+#define S5PC1XX_ADDR_BASE	0xE0000000
+
+#define S5PC1XX_CLOCK_BASE	0xE0100000
+
+/* S5PC100 */
+#define S5PC100_GPIO_BASE	0xE0300000
+#define S5PC100_VIC0_BASE	0xE4000000
+#define S5PC100_VIC1_BASE	0xE4100000
+#define S5PC100_VIC2_BASE	0xE4200000
+#define S5PC100_DMC_BASE	0xE6000000
+#define S5PC100_SROMC_BASE	0xE7000000
+#define S5PC100_ONENAND_BASE	0xE7100000
+#define S5PC100_PWMTIMER_BASE	0xEA000000
+#define S5PC100_WATCHDOG_BASE	0xEA200000
+#define S5PC100_UART_BASE	0xEC000000
+
+/* S5PC110 */
+#define S5PC110_GPIO_BASE	0xE0200000
+#define S5PC110_PWMTIMER_BASE	0xE2500000
+#define S5PC110_WATCHDOG_BASE	0xE2700000
+#define S5PC110_UART_BASE	0xE2900000
+#define S5PC110_SROMC_BASE	0xE8000000
+#define S5PC110_DMC0_BASE	0xF0000000
+#define S5PC110_DMC1_BASE	0xF1400000
+#define S5PC110_VIC0_BASE	0xF2000000
+#define S5PC110_VIC1_BASE	0xF2100000
+#define S5PC110_VIC2_BASE	0xF2200000
+#define S5PC110_VIC3_BASE	0xF2300000
+
+/* Chip ID */
+#define S5PC1XX_PRO_ID		0xE0000000
+
+#ifndef __ASSEMBLY__
+/* CPU detection macros */
+extern unsigned int s5pc1xx_cpu_id;
+
+#define IS_SAMSUNG_TYPE(type, id)			\
+static inline int cpu_is_##type(void)			\
+{							\
+	return s5pc1xx_cpu_id == id ? 1 : 0;		\
+}
+
+IS_SAMSUNG_TYPE(s5pc100, 0xc100)
+IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+#endif
+
+#endif	/* _S5PC1XX_CPU_H */
diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h
new file mode 100644
index 0000000000..afbc7ea5ae
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/gpio.h
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_gpio_bank {
+	unsigned int	con;
+	unsigned int	dat;
+	unsigned int	pull;
+	unsigned int	drv;
+	unsigned int	pdn_con;
+	unsigned int	pdn_pull;
+	unsigned char	res1[8];
+};
+
+struct s5pc100_gpio {
+	struct s5pc1xx_gpio_bank gpio_a0;
+	struct s5pc1xx_gpio_bank gpio_a1;
+	struct s5pc1xx_gpio_bank gpio_b;
+	struct s5pc1xx_gpio_bank gpio_c;
+	struct s5pc1xx_gpio_bank gpio_d;
+	struct s5pc1xx_gpio_bank gpio_e0;
+	struct s5pc1xx_gpio_bank gpio_e1;
+	struct s5pc1xx_gpio_bank gpio_f0;
+	struct s5pc1xx_gpio_bank gpio_f1;
+	struct s5pc1xx_gpio_bank gpio_f2;
+	struct s5pc1xx_gpio_bank gpio_f3;
+	struct s5pc1xx_gpio_bank gpio_g0;
+	struct s5pc1xx_gpio_bank gpio_g1;
+	struct s5pc1xx_gpio_bank gpio_g2;
+	struct s5pc1xx_gpio_bank gpio_g3;
+	struct s5pc1xx_gpio_bank gpio_i;
+	struct s5pc1xx_gpio_bank gpio_j0;
+	struct s5pc1xx_gpio_bank gpio_j1;
+	struct s5pc1xx_gpio_bank gpio_j2;
+	struct s5pc1xx_gpio_bank gpio_j3;
+	struct s5pc1xx_gpio_bank gpio_j4;
+	struct s5pc1xx_gpio_bank gpio_k0;
+	struct s5pc1xx_gpio_bank gpio_k1;
+	struct s5pc1xx_gpio_bank gpio_k2;
+	struct s5pc1xx_gpio_bank gpio_k3;
+	struct s5pc1xx_gpio_bank gpio_l0;
+	struct s5pc1xx_gpio_bank gpio_l1;
+	struct s5pc1xx_gpio_bank gpio_l2;
+	struct s5pc1xx_gpio_bank gpio_l3;
+	struct s5pc1xx_gpio_bank gpio_l4;
+	struct s5pc1xx_gpio_bank gpio_h0;
+	struct s5pc1xx_gpio_bank gpio_h1;
+	struct s5pc1xx_gpio_bank gpio_h2;
+	struct s5pc1xx_gpio_bank gpio_h3;
+};
+
+struct s5pc110_gpio {
+	struct s5pc1xx_gpio_bank gpio_a0;
+	struct s5pc1xx_gpio_bank gpio_a1;
+	struct s5pc1xx_gpio_bank gpio_b;
+	struct s5pc1xx_gpio_bank gpio_c0;
+	struct s5pc1xx_gpio_bank gpio_c1;
+	struct s5pc1xx_gpio_bank gpio_d0;
+	struct s5pc1xx_gpio_bank gpio_d1;
+	struct s5pc1xx_gpio_bank gpio_e0;
+	struct s5pc1xx_gpio_bank gpio_e1;
+	struct s5pc1xx_gpio_bank gpio_f0;
+	struct s5pc1xx_gpio_bank gpio_f1;
+	struct s5pc1xx_gpio_bank gpio_f2;
+	struct s5pc1xx_gpio_bank gpio_f3;
+	struct s5pc1xx_gpio_bank gpio_g0;
+	struct s5pc1xx_gpio_bank gpio_g1;
+	struct s5pc1xx_gpio_bank gpio_g2;
+	struct s5pc1xx_gpio_bank gpio_g3;
+	struct s5pc1xx_gpio_bank gpio_i;
+	struct s5pc1xx_gpio_bank gpio_j0;
+	struct s5pc1xx_gpio_bank gpio_j1;
+	struct s5pc1xx_gpio_bank gpio_j2;
+	struct s5pc1xx_gpio_bank gpio_j3;
+	struct s5pc1xx_gpio_bank gpio_j4;
+	struct s5pc1xx_gpio_bank gpio_mp0_1;
+	struct s5pc1xx_gpio_bank gpio_mp0_2;
+	struct s5pc1xx_gpio_bank gpio_mp0_3;
+	struct s5pc1xx_gpio_bank gpio_mp0_4;
+	struct s5pc1xx_gpio_bank gpio_mp0_5;
+	struct s5pc1xx_gpio_bank gpio_mp0_6;
+	struct s5pc1xx_gpio_bank gpio_mp0_7;
+	struct s5pc1xx_gpio_bank gpio_mp1_0;
+	struct s5pc1xx_gpio_bank gpio_mp1_1;
+	struct s5pc1xx_gpio_bank gpio_mp1_2;
+	struct s5pc1xx_gpio_bank gpio_mp1_3;
+	struct s5pc1xx_gpio_bank gpio_mp1_4;
+	struct s5pc1xx_gpio_bank gpio_mp1_5;
+	struct s5pc1xx_gpio_bank gpio_mp1_6;
+	struct s5pc1xx_gpio_bank gpio_mp1_7;
+	struct s5pc1xx_gpio_bank gpio_mp1_8;
+	struct s5pc1xx_gpio_bank gpio_mp2_0;
+	struct s5pc1xx_gpio_bank gpio_mp2_1;
+	struct s5pc1xx_gpio_bank gpio_mp2_2;
+	struct s5pc1xx_gpio_bank gpio_mp2_3;
+	struct s5pc1xx_gpio_bank gpio_mp2_4;
+	struct s5pc1xx_gpio_bank gpio_mp2_5;
+	struct s5pc1xx_gpio_bank gpio_mp2_6;
+	struct s5pc1xx_gpio_bank gpio_mp2_7;
+	struct s5pc1xx_gpio_bank gpio_mp2_8;
+	struct s5pc1xx_gpio_bank res1[48];
+	struct s5pc1xx_gpio_bank gpio_h0;
+	struct s5pc1xx_gpio_bank gpio_h1;
+	struct s5pc1xx_gpio_bank gpio_h2;
+	struct s5pc1xx_gpio_bank gpio_h3;
+};
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h
new file mode 100644
index 0000000000..57e2a2ba19
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/power.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+/*
+ * Power control
+ */
+#define S5PC100_OTHERS			0xE0108200
+#define S5PC100_RST_STAT		0xE0108300
+#define S5PC100_SLEEP_WAKEUP		(1 << 3)
+#define S5PC100_WAKEUP_STAT		0xE0108304
+#define S5PC100_INFORM0			0xE0108400
+
+#define S5PC110_RST_STAT		0xE010A000
+#define S5PC110_SLEEP_WAKEUP		(1 << 3)
+#define S5PC110_WAKEUP_STAT		0xE010C200
+#define S5PC110_OTHERS			0xE010E000
+#define S5PC110_USB_PHY_CON		0xE010E80C
+#define S5PC110_INFORM0			0xE010F000
+
+#endif
diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h
new file mode 100644
index 0000000000..e02a8d8fb3
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/pwm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+/* PWM timer addressing */
+#define S5PC100_TIMER_BASE	S5PC100_PWMTIMER_BASE
+#define S5PC110_TIMER_BASE	S5PC110_PWMTIMER_BASE
+
+/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define S5PC1XX_TCON4_AUTO_RELOAD	(1 << 22)
+/* Update TCNTB4 */
+#define S5PC1XX_TCON4_UPDATE		(1 << 21)
+/* start bit of PWM Timer 4 */
+#define S5PC1XX_TCON4_START		(1 << 20)
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_timer {
+	unsigned int	tcfg0;
+	unsigned int	tcfg1;
+	unsigned int	tcon;
+	unsigned int	tcntb0;
+	unsigned int	tcmpb0;
+	unsigned int	tcnto0;
+	unsigned int	tcntb1;
+	unsigned int	tcmpb1;
+	unsigned int	tcnto1;
+	unsigned int	tcntb2;
+	unsigned int	tcmpb2;
+	unsigned int	tcnto2;
+	unsigned int	tcntb3;
+	unsigned int	res1;
+	unsigned int	tcnto3;
+	unsigned int	tcntb4;
+	unsigned int	tcnto4;
+	unsigned int	tintcstat;
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h
new file mode 100644
index 0000000000..140dbdc45f
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/uart.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_uart {
+	unsigned int	ulcon;
+	unsigned int	ucon;
+	unsigned int	ufcon;
+	unsigned int	umcon;
+	unsigned int	utrstat;
+	unsigned int	uerstat;
+	unsigned int	ufstat;
+	unsigned int	umstat;
+	unsigned char	utxh;
+	unsigned char	res1[3];
+	unsigned char	urxh;
+	unsigned char	res2[3];
+	unsigned int	ubrdiv;
+	unsigned short	udivslot;
+	unsigned char	res3[2];
+	unsigned char	res4[0x3d0];
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index 4ef8566ea2..de8cfb7c60 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -295,6 +295,7 @@
 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 0d3acf61ae..8746f702da 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -189,8 +189,8 @@
 #define CONFIG_SILENT_CONSOLE		1
 
 #define CONFIG_AUTOBOOT_KEYED		1
-#define CONFIG_AUTOBOOT_PROMPT 		\
-	"Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot\n"
 #define CONFIG_AUTOBOOT_STOP_STR	" "
 #define CONFIG_AUTOBOOT_DELAY_STR	"d"
 
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index d092fb8325..ea40df0bed 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -69,6 +69,7 @@
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
new file mode 100644
index 0000000000..5db720e9d6
--- /dev/null
+++ b/include/configs/davinci_dm355leopard.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DAVINCI_DM355LEOPARD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_DISPLAY_CPUINFO
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM355				/* DM355 based board */
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Ethernet:  external DM9000 */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x04000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 16)
+#define CONFIG_NET_MULTI
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x10
+
+/* NAND */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_HW_ECC
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM355 LEOPARD # "
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x3C0000
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#endif
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"dhcp;bootm"
+#define CONFIG_BOOTARGS		\
+			"console=ttyS0,115200n8 " \
+			"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#define PART_BOOT		"2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT		"512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index 2797f827e9..53a105bf6d 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2009 Texas Instruments Incorporated
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -76,6 +77,7 @@
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
new file mode 100644
index 0000000000..2a4cb79f88
--- /dev/null
+++ b/include/configs/davinci_dm6467evm.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM6467 EVM board */
+#define DAVINCI_DM6467EVM
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM646X
+
+/* EEPROM definitions for EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* initial data */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+#define PHYS_SDRAM_1			0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* DDR size 256MB */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
+
+/* Serial Driver info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* I2C Configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		10
+
+/* Flash & Environment */
+#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+#define CONFIG_SYS_NAND_BASE_LIST	{0x42000000, }
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_ENV_OFFSET		0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(4 << 10)	/* 4 KiB */
+#endif
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM6467 EVM > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTCOMMAND		"source 0x82080000; dhcp; bootm"
+#define CONFIG_BOOTARGS			\
+					"mem=120M console=ttyS0,115200n8 " \
+					"root=/dev/hda1 rw noinitrd ip=dhcp"
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#endif /* __CONFIG_H */
+
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index f7d23990c4..b045e80ae6 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -138,6 +138,7 @@
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #define DEF_BOOTM		""
 #elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 5a55c569dd..9138b2b90a 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -125,6 +125,7 @@
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #define DEF_BOOTM		""
 #elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index a8ac786c64..bd5037e910 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -30,7 +30,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /* High Level Configuration Options */
 #define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
@@ -59,9 +58,9 @@
 #define CONFIG_REVISION_TAG		1
 
 /* Size of malloc() pool */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
@@ -271,16 +270,16 @@
 #define CONFIG_SYS_HZ			1000
 
 /* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE		SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ		SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ		SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE		SZ_128M	/* at least 128 meg */
+#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* at least 128 MiB */
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -289,7 +288,7 @@
 /* NAND and environment organization  */
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 55eeb947fe..19a5ec92ec 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -27,7 +27,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -62,9 +61,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
@@ -165,16 +164,27 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
-	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
-	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=jffs2\0" \
 	"mmcargs=setenv bootargs console=${console} " \
-		"video=${videospec},mode:${videomode} " \
-		"root=/dev/mmcblk0p2 rw " \
-		"rootfstype=ext3 rootwait\0" \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
 	"nandargs=setenv bootargs console=${console} " \
-		"video=${videospec},mode:${videomode} " \
-		"root=/dev/mtdblock4 rw " \
-		"rootfstype=jffs2\0" \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
@@ -239,10 +249,10 @@
  *
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -250,7 +260,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -269,7 +279,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
 						/* one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 72e9626963..a5514aeb9b 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -32,7 +32,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -67,9 +66,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /*
@@ -231,10 +230,10 @@
  *
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -242,7 +241,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -261,7 +260,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
 						/* on one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 1a9192135e..ffb515d322 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -19,7 +19,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -54,9 +53,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
@@ -151,16 +150,27 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
-	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
-	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=jffs2\0" \
 	"mmcargs=setenv bootargs console=${console} " \
-		"video=${videospec},mode:${videomode} " \
-		"root=/dev/mmcblk0p2 rw " \
-		"rootfstype=ext3 rootwait\0" \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
 	"nandargs=setenv bootargs console=${console} " \
-		"video=${videospec},mode:${videomode} " \
-		"root=/dev/mtdblock4 rw " \
-		"rootfstype=jffs2\0" \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
@@ -224,10 +234,10 @@
  *
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -235,7 +245,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -254,7 +264,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
 						/* one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 064c0bc690..6f21af3d13 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -22,7 +22,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -57,9 +56,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
@@ -228,10 +227,10 @@
  *
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -239,7 +238,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -258,7 +257,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
 						/* one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
new file mode 100644
index 0000000000..229dc5e644
--- /dev/null
+++ b/include/configs/omap3_sdp3430.h
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2006-2009
+ * Texas Instruments Incorporated.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the 3430 TI SDP3430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* TODO: REMOVE THE FOLLOWING
+ * Retained the following till size.h is removed in u-boot
+ */
+#include <asm/sizes.h>
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * NOTE:  these #defines presume standard SDP jumper settings.
+ * In particular:
+ *  - 26 MHz clock (not 19.2 or 38.4 MHz)
+ *  - Boot from 128MB NOR, not NAND or OneNAND
+ *
+ * At this writing, OMAP3 U-Boot support doesn't permit concurrent
+ * support for all the flash types the board supports.
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ			/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
+ * swapped with UART2 via jumpering.  Downsides of using J8:  it doesn't
+ * support UART boot (that's only for UART3); it prevents sharing a Linux
+ * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
+ *
+ * UART boot uses UART3 on J9, and the SDP user's guide says to use
+ * that for console.  Downsides of using J9:  you can't use IRDA too;
+ * since UART3 isn't in the CORE power domain, it may be a bit less
+ * usable in certain PM-sensitive debug scenarios.
+ */
+#undef CONSOLE_J9			/* else J8/UART1 (innermost) */
+
+#ifdef CONSOLE_J9
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+#else
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/*
+ * I2C for power management setup
+ */
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/* OMITTED:  single 1 Gbit MT29F1G NAND flash */
+
+/*
+ * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_FLASH_CFI_DRIVER		1	/* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_CFI		1	/* use CFI geometry data */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* ~10x faster writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware sector protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	/* flinfo 'E' for empty */
+#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS      1	/* max number of flash banks */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	2
+#define PHYS_FLASH_SIZE			(128 << 20)
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors on one chip */
+
+/* timeout values are in milliseconds */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* OMITTED:  single 2 Gbit KFM2G16 OneNAND flash */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_SYS_ENV_SECT_SIZE	(256 << 10)
+#define CONFIG_ENV_OFFSET		CONFIG_SYS_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
+/*--------------------------------------------------------------------------*/
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NET
+
+/* Disabled commands */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+/*--------------------------------------------------------------------------*/
+/*
+ * MMC boot support
+ */
+
+#if defined(CONFIG_CMD_MMC)
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+#endif
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE	DEBUG_BASE
+#define CONFIG_LAN91C96_EXT_PHY
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/*
+ * BOOTP fields
+ */
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * Environment setup
+ *
+ * Default boot order:  mmc bootscript, MMC uImage, NOR image.
+ * Network booting environment must be configured at site.
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS0,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"norargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock3 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from MMC/SD ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from MMC/SD ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"norboot=echo Booting from NOR ...; " \
+		"run norargs; " \
+		"bootm 0x80000\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run norboot; " \
+			"fi; " \
+		"fi; " \
+	"else run norboot; fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"OMAP34XX SDP # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
+ * a basic sanity check ONLY
+ * IF you would like to increase coverage, increase the end address
+ * or run the test with custom options
+ */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x01000000)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20) /* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * NOR FLASH usage ... default nCS0:
+ *  - one 256KB sector for U-Boot
+ *  - one 256KB sector for its parameters (not all used)
+ *  - eight sectors (2 MB) for kernel
+ *  - rest for JFFS2
+ */
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/*
+ * NAND FLASH usage ... default nCS1:
+ *  - four 128KB sectors for X-Loader
+ *  - four 128KB sectors for U-Boot
+ *  - two 128KB sector for its parameters
+ *  - 32 sectors (4 MB) for kernel
+ *  - rest for filesystem
+ */
+
+/*
+ * OneNAND FLASH usage ... default nCS2:
+ *  - four 128KB sectors for X-Loader
+ *  - two 128KB sectors for U-Boot
+ *  - one 128KB sector for its parameters
+ *  - sixteen sectors (2 MB) for kernel
+ *  - rest for filesystem
+ */
+
+/*--------------------------------------------------------------------------*/
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index b55b8f0222..da4b677f93 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -28,7 +28,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -63,9 +62,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
@@ -236,10 +235,10 @@
  *
  * The stack sizes are set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -247,7 +246,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -266,7 +265,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
 						/* one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 75ab98098c..32cd6fdb14 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -29,7 +29,6 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-#include <asm/sizes.h>
 
 /*
  * High Level Configuration Options
@@ -64,9 +63,9 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /*
@@ -201,10 +200,10 @@
  *
  * The stack sizes are set up in start.S using these settings
  */
-#define CONFIG_STACKSIZE	SZ_128K
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	SZ_4K
-#define CONFIG_STACKSIZE_FIQ	SZ_4K
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -212,7 +211,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */
@@ -231,7 +230,7 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
 						/* one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
 
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index f2ea926f92..e6886cf7f6 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -139,9 +139,7 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/
 
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CONFIG_SYS_HZ			1562500
+#define	CONFIG_SYS_HZ			1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index c234177767..a1beb65d0e 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -141,9 +141,7 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x0cf00000	/* default load address	*/
 
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CONFIG_SYS_HZ			1562500
+#define	CONFIG_SYS_HZ			1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index d340098d0b..c57751bf90 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -124,9 +124,7 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/
 
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define	CONFIG_SYS_HZ			1562500
+#define	CONFIG_SYS_HZ			1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
new file mode 100644
index 0000000000..8c472aff47
--- /dev/null
+++ b/include/configs/smdkc100.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
+#define CONFIG_S5PC100		1	/* which is in a S5PC100 */
+#define CONFIG_SMDKC100		1	/* working with SMDKC100 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_L2_OFF
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
+						/* initial data */
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0			1	/* use SERIAL 0 on SMDKC100 */
+#define CONFIG_SERIAL_MULTI		1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT		"onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=s3c-onenand:256k(bootloader)"\
+				",128k@0x40000(params)"\
+				",3m@0x60000(kernel)"\
+				",16m@0x360000(test)"\
+				",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+				" console=ttySAC0,115200n8" \
+				" mem=128M"
+
+#define CONFIG_COMMON_BOOT	"console=ttySAC0,115200n8" \
+				" mem=128M " \
+				" " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock5 ubi.mtd=4" \
+			" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x40000;" \
+			" onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0x60000 0x300000;" \
+		"onenand write 0x31008000 0x60000 0x300000\0" \
+	"updateu=" \
+		"onenand erase block 147-4095;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0x60000 0x300000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype} " \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+		"run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"android=" \
+		"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+		"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+		"nfsroot=${nfsroot},nolock " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"rootfstype=cramfs\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"meminfo=mem=128M\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=5\0" \
+	"ubiblock=4\0" \
+	"ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"SMDKC100 # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(256 << 10)	/* 256 KiB */
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	(128 << 20)	/* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH		1
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+#define CONFIG_IDENT_STRING		" for SMDKC100"
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR			(256 << 10)	/* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET		(256 << 10)	/* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xE7100000
+
+#define CONFIG_DOS_PARTITION		1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 43c191b435..97f30cea75 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -320,17 +320,7 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x0CF00000	/* default load address	*/
 
-#ifdef CONFIG_TRAB_50MHZ
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define	CONFIG_SYS_HZ			1562500
-#else
-/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
-/* it to wrap 100 times (total 1039000) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define	CONFIG_SYS_HZ			1039000
-#endif
+#define	CONFIG_SYS_HZ			1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 06f7bafeae..9a6f31752e 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -135,6 +135,7 @@ struct onenand_chip {
 #define ONENAND_HAS_CONT_LOCK		(0x0001)
 #define ONENAND_HAS_UNLOCK_ALL		(0x0002)
 #define ONENAND_HAS_2PLANE		(0x0004)
+#define ONENAND_RUNTIME_BADBLOCK_CHECK	(0x0200)
 #define ONENAND_PAGEBUF_ALLOC		(0x1000)
 #define ONENAND_OOBBUF_ALLOC		(0x2000)
 
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index fc63380d92..07fed1c60f 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -121,6 +121,8 @@
 #define ONENAND_CMD_LOCK_TIGHT		(0x2C)
 #define ONENAND_CMD_UNLOCK_ALL		(0x27)
 #define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_MULTIBLOCK_ERASE	(0x95)
+#define ONENAND_CMD_ERASE_VERIFY	(0x71)
 #define ONENAND_CMD_RESET		(0xF0)
 #define ONENAND_CMD_READID		(0x90)
 
@@ -184,7 +186,9 @@
  * ECC Status Reigser FF00h (R)
  */
 #define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_1BIT_ALL		(0x5555)
 #define ONENAND_ECC_2BIT		(1 << 1)
 #define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+#define ONENAND_ECC_4BIT_UNCORRECTABLE	(0x1010)
 
 #endif				/* __ONENAND_REG_H */
diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h
new file mode 100644
index 0000000000..021fa27f7d
--- /dev/null
+++ b/include/linux/mtd/samsung_onenand.h
@@ -0,0 +1,131 @@
+/*
+ *  Copyright (C) 2005-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SAMSUNG_ONENAND_H__
+#define __SAMSUNG_ONENAND_H__
+
+/*
+ * OneNAND Controller
+ */
+
+#ifndef __ASSEMBLY__
+struct samsung_onenand {
+	unsigned int	mem_cfg;	/* 0x0000 */
+	unsigned char	res1[0xc];
+	unsigned int	burst_len;	/* 0x0010 */
+	unsigned char	res2[0xc];
+	unsigned int	mem_reset;	/* 0x0020 */
+	unsigned char	res3[0xc];
+	unsigned int	int_err_stat;	/* 0x0030 */
+	unsigned char	res4[0xc];
+	unsigned int	int_err_mask;	/* 0x0040 */
+	unsigned char	res5[0xc];
+	unsigned int	int_err_ack;	/* 0x0050 */
+	unsigned char	res6[0xc];
+	unsigned int	ecc_err_stat;	/* 0x0060 */
+	unsigned char	res7[0xc];
+	unsigned int	manufact_id;	/* 0x0070 */
+	unsigned char	res8[0xc];
+	unsigned int	device_id;	/* 0x0080 */
+	unsigned char	res9[0xc];
+	unsigned int	data_buf_size;	/* 0x0090 */
+	unsigned char	res10[0xc];
+	unsigned int	boot_buf_size;	/* 0x00A0 */
+	unsigned char	res11[0xc];
+	unsigned int	buf_amount;	/* 0x00B0 */
+	unsigned char	res12[0xc];
+	unsigned int	tech;		/* 0x00C0 */
+	unsigned char	res13[0xc];
+	unsigned int	fba;		/* 0x00D0 */
+	unsigned char	res14[0xc];
+	unsigned int	fpa;		/* 0x00E0 */
+	unsigned char	res15[0xc];
+	unsigned int	fsa;		/* 0x00F0 */
+	unsigned char	res16[0x3c];
+	unsigned int	sync_mode;	/* 0x0130 */
+	unsigned char	res17[0xc];
+	unsigned int	trans_spare;	/* 0x0140 */
+	unsigned char	res18[0x3c];
+	unsigned int	err_page_addr;	/* 0x0180 */
+	unsigned char	res19[0x1c];
+	unsigned int	int_pin_en;	/* 0x01A0 */
+	unsigned char	res20[0x1c];
+	unsigned int	acc_clock;	/* 0x01C0 */
+	unsigned char	res21[0x1c];
+	unsigned int	err_blk_addr;	/* 0x01E0 */
+	unsigned char	res22[0xc];
+	unsigned int	flash_ver_id;	/* 0x01F0 */
+	unsigned char	res23[0x6c];
+	unsigned int	watchdog_cnt_low;	/* 0x0260 */
+	unsigned char	res24[0xc];
+	unsigned int	watchdog_cnt_hi;	/* 0x0270 */
+	unsigned char	res25[0xc];
+	unsigned int	sync_write;	/* 0x0280 */
+	unsigned char	res26[0x1c];
+	unsigned int	cold_reset;	/* 0x02A0 */
+	unsigned char	res27[0xc];
+	unsigned int	ddp_device;	/* 0x02B0 */
+	unsigned char	res28[0xc];
+	unsigned int	multi_plane;	/* 0x02C0 */
+	unsigned char	res29[0x1c];
+	unsigned int	trans_mode;	/* 0x02E0 */
+	unsigned char	res30[0x1c];
+	unsigned int	ecc_err_stat2;	/* 0x0300 */
+	unsigned char	res31[0xc];
+	unsigned int	ecc_err_stat3;	/* 0x0310 */
+	unsigned char	res32[0xc];
+	unsigned int	ecc_err_stat4;	/* 0x0320 */
+	unsigned char	res33[0x1c];
+	unsigned int	dev_page_size;	/* 0x0340 */
+	unsigned char	res34[0x4c];
+	unsigned int	int_mon_status;	/* 0x0390 */
+};
+#endif
+
+#define ONENAND_MEM_RESET_HOT	0x3
+#define ONENAND_MEM_RESET_COLD	0x2
+#define ONENAND_MEM_RESET_WARM	0x1
+
+#define INT_ERR_ALL	0x3fff
+#define CACHE_OP_ERR    (1 << 13)
+#define RST_CMP         (1 << 12)
+#define RDY_ACT         (1 << 11)
+#define INT_ACT         (1 << 10)
+#define UNSUP_CMD       (1 << 9)
+#define LOCKED_BLK      (1 << 8)
+#define BLK_RW_CMP      (1 << 7)
+#define ERS_CMP         (1 << 6)
+#define PGM_CMP         (1 << 5)
+#define LOAD_CMP        (1 << 4)
+#define ERS_FAIL        (1 << 3)
+#define PGM_FAIL        (1 << 2)
+#define INT_TO          (1 << 1)
+#define LD_FAIL_ECC_ERR (1 << 0)
+
+#define TSRF		(1 << 0)
+
+/* common initialize function */
+extern void s3c_onenand_init(struct mtd_info *);
+
+#endif
diff --git a/include/s3c2400.h b/include/s3c2400.h
index 4fdc62ec11..062259d102 100644
--- a/include/s3c2400.h
+++ b/include/s3c2400.h
@@ -35,12 +35,12 @@
 #define S3C24X0_SPI_CHANNELS	1
 #define PALETTE			(0x14A00400)	/* SJS */
 
-typedef enum {
+enum s3c24x0_uarts_nr {
 	S3C24X0_UART0,
 	S3C24X0_UART1,
-} S3C24X0_UARTS_NR;
+};
 
-/* S3C2400 device base addresses */
+/*S3C2400 device base addresses */
 #define S3C24X0_MEMCTL_BASE		0x14000000
 #define S3C24X0_USB_HOST_BASE		0x14200000
 #define S3C24X0_INTERRUPT_BASE		0x14400000
@@ -63,492 +63,74 @@ typedef enum {
 #include <s3c24x0.h>
 
 
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
 {
-	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
 }
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
 {
-	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
 }
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
 {
-	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
 }
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
 {
-	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
 }
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
 {
-	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
 }
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
 {
-	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
 }
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
 {
-	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
 }
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
 {
-	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
 }
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
 {
-	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
 }
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
 {
-	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
 }
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
 {
-	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
 }
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
 {
-	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
 }
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
 {
-	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
 }
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
 {
-	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
 }
-static inline S3C2400_ADC * S3C2400_GetBase_ADC(void)
+static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
 {
-	return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
+	return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
 }
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
 {
-	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
 }
-static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
+static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
 {
-	return (S3C2400_MMC * const)S3C2400_MMC_BASE;
+	return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
 }
 
-#if 0
-/* Memory control */
-#define rBWSCON		(*(volatile unsigned *)0x14000000)
-#define rBANKCON0	(*(volatile unsigned *)0x14000004)
-#define rBANKCON1	(*(volatile unsigned *)0x14000008)
-#define rBANKCON2	(*(volatile unsigned *)0x1400000C)
-#define rBANKCON3	(*(volatile unsigned *)0x14000010)
-#define rBANKCON4	(*(volatile unsigned *)0x14000014)
-#define rBANKCON5	(*(volatile unsigned *)0x14000018)
-#define rBANKCON6	(*(volatile unsigned *)0x1400001C)
-#define rBANKCON7	(*(volatile unsigned *)0x14000020)
-#define rREFRESH	(*(volatile unsigned *)0x14000024)
-#define rBANKSIZE	(*(volatile unsigned *)0x14000028)
-#define rMRSRB6		(*(volatile unsigned *)0x1400002C)
-#define rMRSRB7		(*(volatile unsigned *)0x14000030)
-
-
-/* INTERRUPT */
-#define rSRCPND		(*(volatile unsigned *)0x14400000)
-#define rINTMOD		(*(volatile unsigned *)0x14400004)
-#define rINTMSK		(*(volatile unsigned *)0x14400008)
-#define rPRIORITY	(*(volatile unsigned *)0x1440000C)
-#define rINTPND		(*(volatile unsigned *)0x14400010)
-#define rINTOFFSET	(*(volatile unsigned *)0x14400014)
-
-
-/* DMA */
-#define rDISRC0		(*(volatile unsigned *)0x14600000)
-#define rDIDST0		(*(volatile unsigned *)0x14600004)
-#define rDCON0		(*(volatile unsigned *)0x14600008)
-#define rDSTAT0		(*(volatile unsigned *)0x1460000C)
-#define rDCSRC0		(*(volatile unsigned *)0x14600010)
-#define rDCDST0		(*(volatile unsigned *)0x14600014)
-#define rDMASKTRIG0	(*(volatile unsigned *)0x14600018)
-#define rDISRC1		(*(volatile unsigned *)0x14600020)
-#define rDIDST1		(*(volatile unsigned *)0x14600024)
-#define rDCON1		(*(volatile unsigned *)0x14600028)
-#define rDSTAT1		(*(volatile unsigned *)0x1460002C)
-#define rDCSRC1		(*(volatile unsigned *)0x14600030)
-#define rDCDST1		(*(volatile unsigned *)0x14600034)
-#define rDMASKTRIG1	(*(volatile unsigned *)0x14600038)
-#define rDISRC2		(*(volatile unsigned *)0x14600040)
-#define rDIDST2		(*(volatile unsigned *)0x14600044)
-#define rDCON2		(*(volatile unsigned *)0x14600048)
-#define rDSTAT2		(*(volatile unsigned *)0x1460004C)
-#define rDCSRC2		(*(volatile unsigned *)0x14600050)
-#define rDCDST2		(*(volatile unsigned *)0x14600054)
-#define rDMASKTRIG2	(*(volatile unsigned *)0x14600058)
-#define rDISRC3		(*(volatile unsigned *)0x14600060)
-#define rDIDST3		(*(volatile unsigned *)0x14600064)
-#define rDCON3		(*(volatile unsigned *)0x14600068)
-#define rDSTAT3		(*(volatile unsigned *)0x1460006C)
-#define rDCSRC3		(*(volatile unsigned *)0x14600070)
-#define rDCDST3		(*(volatile unsigned *)0x14600074)
-#define rDMASKTRIG3	(*(volatile unsigned *)0x14600078)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME	(*(volatile unsigned *)0x14800000)
-#define rMPLLCON	(*(volatile unsigned *)0x14800004)
-#define rUPLLCON	(*(volatile unsigned *)0x14800008)
-#define rCLKCON		(*(volatile unsigned *)0x1480000C)
-#define rCLKSLOW	(*(volatile unsigned *)0x14800010)
-#define rCLKDIVN	(*(volatile unsigned *)0x14800014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1	(*(volatile unsigned *)0x14A00000)
-#define rLCDCON2	(*(volatile unsigned *)0x14A00004)
-#define rLCDCON3	(*(volatile unsigned *)0x14A00008)
-#define rLCDCON4	(*(volatile unsigned *)0x14A0000C)
-#define rLCDCON5	(*(volatile unsigned *)0x14A00010)
-#define rLCDSADDR1	(*(volatile unsigned *)0x14A00014)
-#define rLCDSADDR2	(*(volatile unsigned *)0x14A00018)
-#define rLCDSADDR3	(*(volatile unsigned *)0x14A0001C)
-#define rREDLUT		(*(volatile unsigned *)0x14A00020)
-#define rGREENLUT	(*(volatile unsigned *)0x14A00024)
-#define rBLUELUT	(*(volatile unsigned *)0x14A00028)
-#define rDP1_2		(*(volatile unsigned *)0x14A0002C)
-#define rDP4_7		(*(volatile unsigned *)0x14A00030)
-#define rDP3_5		(*(volatile unsigned *)0x14A00034)
-#define rDP2_3		(*(volatile unsigned *)0x14A00038)
-#define rDP5_7		(*(volatile unsigned *)0x14A0003c)
-#define rDP3_4		(*(volatile unsigned *)0x14A00040)
-#define rDP4_5		(*(volatile unsigned *)0x14A00044)
-#define rDP6_7		(*(volatile unsigned *)0x14A00048)
-#define rDITHMODE	(*(volatile unsigned *)0x14A0004C)
-#define rTPAL		(*(volatile unsigned *)0x14A00050)
-#define PALETTE		(0x14A00400)	/* SJS */
-
-
-/* UART */
-#define rULCON0		(*(volatile unsigned char *)0x15000000)
-#define rUCON0		(*(volatile unsigned short *)0x15000004)
-#define rUFCON0		(*(volatile unsigned char *)0x15000008)
-#define rUMCON0		(*(volatile unsigned char *)0x1500000C)
-#define rUTRSTAT0	(*(volatile unsigned char *)0x15000010)
-#define rUERSTAT0	(*(volatile unsigned char *)0x15000014)
-#define rUFSTAT0	(*(volatile unsigned short *)0x15000018)
-#define rUMSTAT0	(*(volatile unsigned char *)0x1500001C)
-#define rUBRDIV0	(*(volatile unsigned short *)0x15000028)
-
-#define rULCON1		(*(volatile unsigned char *)0x15004000)
-#define rUCON1		(*(volatile unsigned short *)0x15004004)
-#define rUFCON1		(*(volatile unsigned char *)0x15004008)
-#define rUMCON1		(*(volatile unsigned char *)0x1500400C)
-#define rUTRSTAT1	(*(volatile unsigned char *)0x15004010)
-#define rUERSTAT1	(*(volatile unsigned char *)0x15004014)
-#define rUFSTAT1	(*(volatile unsigned short *)0x15004018)
-#define rUMSTAT1	(*(volatile unsigned char *)0x1500401C)
-#define rUBRDIV1	(*(volatile unsigned short *)0x15004028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0		(*(volatile unsigned char *)0x15000023)
-#define rURXH0		(*(volatile unsigned char *)0x15000027)
-#define rUTXH1		(*(volatile unsigned char *)0x15004023)
-#define rURXH1		(*(volatile unsigned char *)0x15004027)
-
-#define WrUTXH0(ch)	(*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
-#define RdURXH0()	(*(volatile unsigned char *)0x15000027)
-#define WrUTXH1(ch)	(*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
-#define RdURXH1()	(*(volatile unsigned char *)0x15004027)
-
-#define UTXH0		(0x15000020+3)  /* byte_access address by DMA */
-#define URXH0		(0x15000024+3)
-#define UTXH1		(0x15004020+3)
-#define URXH1		(0x15004024+3)
-
-#else /* Little Endian */
-#define rUTXH0		(*(volatile unsigned char *)0x15000020)
-#define rURXH0		(*(volatile unsigned char *)0x15000024)
-#define rUTXH1		(*(volatile unsigned char *)0x15004020)
-#define rURXH1		(*(volatile unsigned char *)0x15004024)
-
-#define WrUTXH0(ch)	(*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
-#define RdURXH0()	(*(volatile unsigned char *)0x15000024)
-#define WrUTXH1(ch)	(*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
-#define RdURXH1()	(*(volatile unsigned char *)0x15004024)
-
-#define UTXH0		(0x15000020)    /* byte_access address by DMA */
-#define URXH0		(0x15000024)
-#define UTXH1		(0x15004020)
-#define URXH1		(0x15004024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0		(*(volatile unsigned *)0x15100000)
-#define rTCFG1		(*(volatile unsigned *)0x15100004)
-#define rTCON		(*(volatile unsigned *)0x15100008)
-#define rTCNTB0		(*(volatile unsigned *)0x1510000C)
-#define rTCMPB0		(*(volatile unsigned *)0x15100010)
-#define rTCNTO0		(*(volatile unsigned *)0x15100014)
-#define rTCNTB1		(*(volatile unsigned *)0x15100018)
-#define rTCMPB1		(*(volatile unsigned *)0x1510001C)
-#define rTCNTO1		(*(volatile unsigned *)0x15100020)
-#define rTCNTB2		(*(volatile unsigned *)0x15100024)
-#define rTCMPB2		(*(volatile unsigned *)0x15100028)
-#define rTCNTO2		(*(volatile unsigned *)0x1510002C)
-#define rTCNTB3		(*(volatile unsigned *)0x15100030)
-#define rTCMPB3		(*(volatile unsigned *)0x15100034)
-#define rTCNTO3		(*(volatile unsigned *)0x15100038)
-#define rTCNTB4		(*(volatile unsigned *)0x1510003C)
-#define rTCNTO4		(*(volatile unsigned *)0x15100040)
-
-
-/* USB DEVICE */
-#define rFUNC_ADDR_REG	(*(volatile unsigned *)0x15200140)
-#define rPWR_REG	(*(volatile unsigned *)0x15200144)
-#define rINT_REG	(*(volatile unsigned *)0x15200148)
-#define rINT_MASK_REG	(*(volatile unsigned *)0x1520014C)
-#define rFRAME_NUM_REG	(*(volatile unsigned *)0x15200150)
-#define rRESUME_CON_REG	(*(volatile unsigned *)0x15200154)
-#define rEP0_CSR	(*(volatile unsigned *)0x15200160)
-#define rEP0_MAXP	(*(volatile unsigned *)0x15200164)
-#define rEP0_OUT_CNT	(*(volatile unsigned *)0x15200168)
-#define rEP0_FIFO	(*(volatile unsigned *)0x1520016C)
-#define rEP1_IN_CSR	(*(volatile unsigned *)0x15200180)
-#define rEP1_IN_MAXP	(*(volatile unsigned *)0x15200184)
-#define rEP1_FIFO	(*(volatile unsigned *)0x15200188)
-#define rEP2_IN_CSR	(*(volatile unsigned *)0x15200190)
-#define rEP2_IN_MAXP	(*(volatile unsigned *)0x15200194)
-#define rEP2_FIFO	(*(volatile unsigned *)0x15200198)
-#define rEP3_OUT_CSR	(*(volatile unsigned *)0x152001A0)
-#define rEP3_OUT_MAXP	(*(volatile unsigned *)0x152001A4)
-#define rEP3_OUT_CNT	(*(volatile unsigned *)0x152001A8)
-#define rEP3_FIFO	(*(volatile unsigned *)0x152001AC)
-#define rEP4_OUT_CSR	(*(volatile unsigned *)0x152001B0)
-#define rEP4_OUT_MAXP	(*(volatile unsigned *)0x152001B4)
-#define rEP4_OUT_CNT	(*(volatile unsigned *)0x152001B8)
-#define rEP4_FIFO	(*(volatile unsigned *)0x152001BC)
-#define rDMA_CON	(*(volatile unsigned *)0x152001C0)
-#define rDMA_UNIT	(*(volatile unsigned *)0x152001C4)
-#define rDMA_FIFO	(*(volatile unsigned *)0x152001C8)
-#define rDMA_TX		(*(volatile unsigned *)0x152001CC)
-#define rTEST_MODE	(*(volatile unsigned *)0x152001F4)
-#define rIN_CON_REG	(*(volatile unsigned *)0x152001F8)
-
-
-/* WATCH DOG TIMER */
-#define rWTCON		(*(volatile unsigned *)0x15300000)
-#define rWTDAT		(*(volatile unsigned *)0x15300004)
-#define rWTCNT		(*(volatile unsigned *)0x15300008)
-
-
-/* IIC */
-#define rIICCON		(*(volatile unsigned *)0x15400000)
-#define rIICSTAT	(*(volatile unsigned *)0x15400004)
-#define rIICADD		(*(volatile unsigned *)0x15400008)
-#define rIICDS		(*(volatile unsigned *)0x1540000C)
-
-
-/* IIS */
-#define rIISCON		(*(volatile unsigned *)0x15508000)
-#define rIISMOD		(*(volatile unsigned *)0x15508004)
-#define rIISPSR		(*(volatile unsigned *)0x15508008)
-#define rIISFIFCON	(*(volatile unsigned *)0x1550800C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF		((volatile unsigned short *)0x15508012)
-
-#else /* Little Endian */
-#define IISFIF		((volatile unsigned short *)0x15508010)
-#endif
-
-
-/* I/O PORT */
-#define rPACON		(*(volatile unsigned *)0x15600000)
-#define rPADAT		(*(volatile unsigned *)0x15600004)
-
-#define rPBCON		(*(volatile unsigned *)0x15600008)
-#define rPBDAT		(*(volatile unsigned *)0x1560000C)
-#define rPBUP		(*(volatile unsigned *)0x15600010)
-
-#define rPCCON		(*(volatile unsigned *)0x15600014)
-#define rPCDAT		(*(volatile unsigned *)0x15600018)
-#define rPCUP		(*(volatile unsigned *)0x1560001C)
-
-#define rPDCON		(*(volatile unsigned *)0x15600020)
-#define rPDDAT		(*(volatile unsigned *)0x15600024)
-#define rPDUP		(*(volatile unsigned *)0x15600028)
-
-#define rPECON		(*(volatile unsigned *)0x1560002C)
-#define rPEDAT		(*(volatile unsigned *)0x15600030)
-#define rPEUP		(*(volatile unsigned *)0x15600034)
-
-#define rPFCON		(*(volatile unsigned *)0x15600038)
-#define rPFDAT		(*(volatile unsigned *)0x1560003C)
-#define rPFUP		(*(volatile unsigned *)0x15600040)
-
-#define rPGCON		(*(volatile unsigned *)0x15600044)
-#define rPGDAT		(*(volatile unsigned *)0x15600048)
-#define rPGUP		(*(volatile unsigned *)0x1560004C)
-
-#define rOPENCR		(*(volatile unsigned *)0x15600050)
-#define rMISCCR		(*(volatile unsigned *)0x15600054)
-#define rEXTINT		(*(volatile unsigned *)0x15600058)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON		(*(volatile unsigned char *)0x15700043)
-#define rRTCALM		(*(volatile unsigned char *)0x15700053)
-#define rALMSEC		(*(volatile unsigned char *)0x15700057)
-#define rALMMIN		(*(volatile unsigned char *)0x1570005B)
-#define rALMHOUR	(*(volatile unsigned char *)0x1570005F)
-#define rALMDAY		(*(volatile unsigned char *)0x15700063)
-#define rALMMON		(*(volatile unsigned char *)0x15700067)
-#define rALMYEAR	(*(volatile unsigned char *)0x1570006B)
-#define rRTCRST		(*(volatile unsigned char *)0x1570006F)
-#define rBCDSEC		(*(volatile unsigned char *)0x15700073)
-#define rBCDMIN		(*(volatile unsigned char *)0x15700077)
-#define rBCDHOUR	(*(volatile unsigned char *)0x1570007B)
-#define rBCDDAY		(*(volatile unsigned char *)0x1570007F)
-#define rBCDDATE	(*(volatile unsigned char *)0x15700083)
-#define rBCDMON		(*(volatile unsigned char *)0x15700087)
-#define rBCDYEAR	(*(volatile unsigned char *)0x1570008B)
-#define rTICINT		(*(volatile unsigned char *)0x15700047)
-
-#else /* Little Endian */
-#define rRTCCON		(*(volatile unsigned char *)0x15700040)
-#define rRTCALM		(*(volatile unsigned char *)0x15700050)
-#define rALMSEC		(*(volatile unsigned char *)0x15700054)
-#define rALMMIN		(*(volatile unsigned char *)0x15700058)
-#define rALMHOUR	(*(volatile unsigned char *)0x1570005C)
-#define rALMDAY		(*(volatile unsigned char *)0x15700060)
-#define rALMMON		(*(volatile unsigned char *)0x15700064)
-#define rALMYEAR	(*(volatile unsigned char *)0x15700068)
-#define rRTCRST		(*(volatile unsigned char *)0x1570006C)
-#define rBCDSEC		(*(volatile unsigned char *)0x15700070)
-#define rBCDMIN		(*(volatile unsigned char *)0x15700074)
-#define rBCDHOUR	(*(volatile unsigned char *)0x15700078)
-#define rBCDDAY		(*(volatile unsigned char *)0x1570007C)
-#define rBCDDATE	(*(volatile unsigned char *)0x15700080)
-#define rBCDMON		(*(volatile unsigned char *)0x15700084)
-#define rBCDYEAR	(*(volatile unsigned char *)0x15700088)
-#define rTICINT		(*(volatile unsigned char *)0x15700044)
-#endif
-
-
-/* ADC */
-#define rADCCON		(*(volatile unsigned *)0x15800000)
-#define rADCDAT		(*(volatile unsigned *)0x15800004)
-
-
-/* SPI */
-#define rSPCON		(*(volatile unsigned *)0x15900000)
-#define rSPSTA		(*(volatile unsigned *)0x15900004)
-#define rSPPIN		(*(volatile unsigned *)0x15900008)
-#define rSPPRE		(*(volatile unsigned *)0x1590000C)
-#define rSPTDAT		(*(volatile unsigned *)0x15900010)
-#define rSPRDAT		(*(volatile unsigned *)0x15900014)
-
-
-/* MMC INTERFACE */
-#define rMMCON		(*(volatile unsigned *)0x15a00000)
-#define rMMCRR		(*(volatile unsigned *)0x15a00004)
-#define rMMFCON		(*(volatile unsigned *)0x15a00008)
-#define rMMSTA		(*(volatile unsigned *)0x15a0000C)
-#define rMMFSTA		(*(volatile unsigned *)0x15a00010)
-#define rMMPRE		(*(volatile unsigned *)0x15a00014)
-#define rMMLEN		(*(volatile unsigned *)0x15a00018)
-#define rMMCR7		(*(volatile unsigned *)0x15a0001C)
-#define rMMRSP0		(*(volatile unsigned *)0x15a00020)
-#define rMMRSP1		(*(volatile unsigned *)0x15a00024)
-#define rMMRSP2		(*(volatile unsigned *)0x15a00028)
-#define rMMRSP3		(*(volatile unsigned *)0x15a0002C)
-#define rMMCMD0		(*(volatile unsigned *)0x15a00030)
-#define rMMCMD1		(*(volatile unsigned *)0x15a00034)
-#define rMMCR16		(*(volatile unsigned *)0x15a00038)
-#define rMMDAT		(*(volatile unsigned *)0x15a0003C)
-
-
-/* ISR */
-#define pISR_RESET	(*(unsigned *)(_ISR_STARTADDRESS+0x0))
-#define pISR_UNDEF	(*(unsigned *)(_ISR_STARTADDRESS+0x4))
-#define pISR_SWI	(*(unsigned *)(_ISR_STARTADDRESS+0x8))
-#define pISR_PABORT	(*(unsigned *)(_ISR_STARTADDRESS+0xC))
-#define pISR_DABORT	(*(unsigned *)(_ISR_STARTADDRESS+0x10))
-#define pISR_RESERVED	(*(unsigned *)(_ISR_STARTADDRESS+0x14))
-#define pISR_IRQ	(*(unsigned *)(_ISR_STARTADDRESS+0x18))
-#define pISR_FIQ	(*(unsigned *)(_ISR_STARTADDRESS+0x1C))
-
-#define pISR_EINT0	(*(unsigned *)(_ISR_STARTADDRESS+0x20))
-#define pISR_EINT1	(*(unsigned *)(_ISR_STARTADDRESS+0x24))
-#define pISR_EINT2	(*(unsigned *)(_ISR_STARTADDRESS+0x28))
-#define pISR_EINT3	(*(unsigned *)(_ISR_STARTADDRESS+0x2C))
-#define pISR_EINT4	(*(unsigned *)(_ISR_STARTADDRESS+0x30))
-#define pISR_EINT5	(*(unsigned *)(_ISR_STARTADDRESS+0x34))
-#define pISR_EINT6	(*(unsigned *)(_ISR_STARTADDRESS+0x38))
-#define pISR_EINT7	(*(unsigned *)(_ISR_STARTADDRESS+0x3C))
-#define pISR_TICK	(*(unsigned *)(_ISR_STARTADDRESS+0x40))
-#define pISR_WDT	(*(unsigned *)(_ISR_STARTADDRESS+0x44))
-#define pISR_TIMER0	(*(unsigned *)(_ISR_STARTADDRESS+0x48))
-#define pISR_TIMER1	(*(unsigned *)(_ISR_STARTADDRESS+0x4C))
-#define pISR_TIMER2	(*(unsigned *)(_ISR_STARTADDRESS+0x50))
-#define pISR_TIMER3	(*(unsigned *)(_ISR_STARTADDRESS+0x54))
-#define pISR_TIMER4	(*(unsigned *)(_ISR_STARTADDRESS+0x58))
-#define pISR_UERR01	(*(unsigned *)(_ISR_STARTADDRESS+0x5C))
-#define pISR_NOTUSED	(*(unsigned *)(_ISR_STARTADDRESS+0x60))
-#define pISR_DMA0	(*(unsigned *)(_ISR_STARTADDRESS+0x64))
-#define pISR_DMA1	(*(unsigned *)(_ISR_STARTADDRESS+0x68))
-#define pISR_DMA2	(*(unsigned *)(_ISR_STARTADDRESS+0x6C))
-#define pISR_DMA3	(*(unsigned *)(_ISR_STARTADDRESS+0x70))
-#define pISR_MMC	(*(unsigned *)(_ISR_STARTADDRESS+0x74))
-#define pISR_SPI	(*(unsigned *)(_ISR_STARTADDRESS+0x78))
-#define pISR_URXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x7C))
-#define pISR_URXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x80))
-#define pISR_USBD	(*(unsigned *)(_ISR_STARTADDRESS+0x84))
-#define pISR_USBH	(*(unsigned *)(_ISR_STARTADDRESS+0x88))
-#define pISR_IIC	(*(unsigned *)(_ISR_STARTADDRESS+0x8C))
-#define pISR_UTXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x90))
-#define pISR_UTXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x94))
-#define pISR_RTC	(*(unsigned *)(_ISR_STARTADDRESS+0x98))
-#define pISR_ADC	(*(unsigned *)(_ISR_STARTADDRESS+0xA0))
-
-
-/* PENDING BIT */
-#define BIT_EINT0	(0x1)
-#define BIT_EINT1	(0x1<<1)
-#define BIT_EINT2	(0x1<<2)
-#define BIT_EINT3	(0x1<<3)
-#define BIT_EINT4	(0x1<<4)
-#define BIT_EINT5	(0x1<<5)
-#define BIT_EINT6	(0x1<<6)
-#define BIT_EINT7	(0x1<<7)
-#define BIT_TICK	(0x1<<8)
-#define BIT_WDT		(0x1<<9)
-#define BIT_TIMER0	(0x1<<10)
-#define BIT_TIMER1	(0x1<<11)
-#define BIT_TIMER2	(0x1<<12)
-#define BIT_TIMER3	(0x1<<13)
-#define BIT_TIMER4	(0x1<<14)
-#define BIT_UERR01	(0x1<<15)
-#define BIT_NOTUSED	(0x1<<16)
-#define BIT_DMA0	(0x1<<17)
-#define BIT_DMA1	(0x1<<18)
-#define BIT_DMA2	(0x1<<19)
-#define BIT_DMA3	(0x1<<20)
-#define BIT_MMC		(0x1<<21)
-#define BIT_SPI		(0x1<<22)
-#define BIT_URXD0	(0x1<<23)
-#define BIT_URXD1	(0x1<<24)
-#define BIT_USBD	(0x1<<25)
-#define BIT_USBH	(0x1<<26)
-#define BIT_IIC		(0x1<<27)
-#define BIT_UTXD0	(0x1<<28)
-#define BIT_UTXD1	(0x1<<29)
-#define BIT_RTC		(0x1<<30)
-#define BIT_ADC		(0x1<<31)
-#define BIT_ALLMSK	(0xFFFFFFFF)
-
-#define ClearPending(bit) {\
-		 rSRCPND = bit;\
-		 rINTPND = bit;\
-		 rINTPND;\
-		 }
-/* Wait until rINTPND is changed for the case that the ISR is very short. */
-#endif
 #endif /*__S3C2400_H__*/
diff --git a/include/s3c2410.h b/include/s3c2410.h
index 87135b45dd..03b33b4924 100644
--- a/include/s3c2410.h
+++ b/include/s3c2410.h
@@ -38,11 +38,11 @@
 #define S3C2410_ECCSIZE		512
 #define S3C2410_ECCBYTES	3
 
-typedef enum {
+enum s3c24x0_uarts_nr {
 	S3C24X0_UART0,
 	S3C24X0_UART1,
 	S3C24X0_UART2
-} S3C24X0_UARTS_NR;
+};
 
 /* S3C2410 device base addresses */
 #define S3C24X0_MEMCTL_BASE		0x48000000
@@ -69,159 +69,78 @@ typedef enum {
 #include <s3c24x0.h>
 
 
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
 {
-	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
 }
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
 {
-	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
 }
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
 {
-	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
 }
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
 {
-	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
 }
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
 {
-	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
 }
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
 {
-	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
 }
-static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
+static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
 {
-	return (S3C2410_NAND * const)S3C2410_NAND_BASE;
+	return (struct s3c2410_nand *)S3C2410_NAND_BASE;
 }
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
 {
-	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
 }
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
 {
-	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
 }
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
 {
-	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
 }
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
 {
-	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
 }
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
 {
-	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
 }
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
 {
-	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
 }
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
 {
-	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
 }
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
 {
-	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
 }
-static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
+static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
 {
-	return (S3C2410_ADC * const)S3C2410_ADC_BASE;
+	return (struct s3c2410_adc *)S3C2410_ADC_BASE;
 }
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
 {
-	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
 }
-static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
+static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
 {
-	return (S3C2410_SDI * const)S3C2410_SDI_BASE;
+	return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
 }
 
-
-/* ISR */
-#define pISR_RESET		(*(unsigned *)(_ISR_STARTADDRESS+0x0))
-#define pISR_UNDEF		(*(unsigned *)(_ISR_STARTADDRESS+0x4))
-#define pISR_SWI		(*(unsigned *)(_ISR_STARTADDRESS+0x8))
-#define pISR_PABORT		(*(unsigned *)(_ISR_STARTADDRESS+0xC))
-#define pISR_DABORT		(*(unsigned *)(_ISR_STARTADDRESS+0x10))
-#define pISR_RESERVED		(*(unsigned *)(_ISR_STARTADDRESS+0x14))
-#define pISR_IRQ		(*(unsigned *)(_ISR_STARTADDRESS+0x18))
-#define pISR_FIQ		(*(unsigned *)(_ISR_STARTADDRESS+0x1C))
-
-#define pISR_EINT0		(*(unsigned *)(_ISR_STARTADDRESS+0x20))
-#define pISR_EINT1		(*(unsigned *)(_ISR_STARTADDRESS+0x24))
-#define pISR_EINT2		(*(unsigned *)(_ISR_STARTADDRESS+0x28))
-#define pISR_EINT3		(*(unsigned *)(_ISR_STARTADDRESS+0x2C))
-#define pISR_EINT4_7		(*(unsigned *)(_ISR_STARTADDRESS+0x30))
-#define pISR_EINT8_23		(*(unsigned *)(_ISR_STARTADDRESS+0x34))
-#define pISR_BAT_FLT		(*(unsigned *)(_ISR_STARTADDRESS+0x3C))
-#define pISR_TICK		(*(unsigned *)(_ISR_STARTADDRESS+0x40))
-#define pISR_WDT		(*(unsigned *)(_ISR_STARTADDRESS+0x44))
-#define pISR_TIMER0		(*(unsigned *)(_ISR_STARTADDRESS+0x48))
-#define pISR_TIMER1		(*(unsigned *)(_ISR_STARTADDRESS+0x4C))
-#define pISR_TIMER2		(*(unsigned *)(_ISR_STARTADDRESS+0x50))
-#define pISR_TIMER3		(*(unsigned *)(_ISR_STARTADDRESS+0x54))
-#define pISR_TIMER4		(*(unsigned *)(_ISR_STARTADDRESS+0x58))
-#define pISR_UART2		(*(unsigned *)(_ISR_STARTADDRESS+0x5C))
-#define pISR_NOTUSED		(*(unsigned *)(_ISR_STARTADDRESS+0x60))
-#define pISR_DMA0		(*(unsigned *)(_ISR_STARTADDRESS+0x64))
-#define pISR_DMA1		(*(unsigned *)(_ISR_STARTADDRESS+0x68))
-#define pISR_DMA2		(*(unsigned *)(_ISR_STARTADDRESS+0x6C))
-#define pISR_DMA3		(*(unsigned *)(_ISR_STARTADDRESS+0x70))
-#define pISR_SDI		(*(unsigned *)(_ISR_STARTADDRESS+0x74))
-#define pISR_SPI0		(*(unsigned *)(_ISR_STARTADDRESS+0x78))
-#define pISR_UART1		(*(unsigned *)(_ISR_STARTADDRESS+0x7C))
-#define pISR_USBD		(*(unsigned *)(_ISR_STARTADDRESS+0x84))
-#define pISR_USBH		(*(unsigned *)(_ISR_STARTADDRESS+0x88))
-#define pISR_IIC		(*(unsigned *)(_ISR_STARTADDRESS+0x8C))
-#define pISR_UART0		(*(unsigned *)(_ISR_STARTADDRESS+0x90))
-#define pISR_SPI1		(*(unsigned *)(_ISR_STARTADDRESS+0x94))
-#define pISR_RTC		(*(unsigned *)(_ISR_STARTADDRESS+0x98))
-#define pISR_ADC		(*(unsigned *)(_ISR_STARTADDRESS+0xA0))
-
-
-/* PENDING BIT */
-#define BIT_EINT0		(0x1)
-#define BIT_EINT1		(0x1<<1)
-#define BIT_EINT2		(0x1<<2)
-#define BIT_EINT3		(0x1<<3)
-#define BIT_EINT4_7		(0x1<<4)
-#define BIT_EINT8_23		(0x1<<5)
-#define BIT_BAT_FLT		(0x1<<7)
-#define BIT_TICK		(0x1<<8)
-#define BIT_WDT			(0x1<<9)
-#define BIT_TIMER0		(0x1<<10)
-#define BIT_TIMER1		(0x1<<11)
-#define BIT_TIMER2		(0x1<<12)
-#define BIT_TIMER3		(0x1<<13)
-#define BIT_TIMER4		(0x1<<14)
-#define BIT_UART2		(0x1<<15)
-#define BIT_LCD			(0x1<<16)
-#define BIT_DMA0		(0x1<<17)
-#define BIT_DMA1		(0x1<<18)
-#define BIT_DMA2		(0x1<<19)
-#define BIT_DMA3		(0x1<<20)
-#define BIT_SDI			(0x1<<21)
-#define BIT_SPI0		(0x1<<22)
-#define BIT_UART1		(0x1<<23)
-#define BIT_USBD		(0x1<<25)
-#define BIT_USBH		(0x1<<26)
-#define BIT_IIC			(0x1<<27)
-#define BIT_UART0		(0x1<<28)
-#define BIT_SPI1		(0x1<<29)
-#define BIT_RTC			(0x1<<30)
-#define BIT_ADC			(0x1<<31)
-#define BIT_ALLMSK		(0xFFFFFFFF)
-
-#define ClearPending(bit) {\
-		 rSRCPND = bit;\
-		 rINTPND = bit;\
-		 rINTPND;\
-		 }
-/* Wait until rINTPND is changed for the case that the ISR is very short. */
 #endif /*__S3C2410_H__*/
diff --git a/include/s3c24x0.h b/include/s3c24x0.h
index 4fa8000681..56a551aeb4 100644
--- a/include/s3c24x0.h
+++ b/include/s3c24x0.h
@@ -36,18 +36,18 @@ typedef volatile u16	S3C24X0_REG16;
 typedef volatile u32	S3C24X0_REG32;
 
 /* Memory controller (see manual chapter 5) */
-typedef struct {
+struct s3c24x0_memctl {
 	S3C24X0_REG32	BWSCON;
 	S3C24X0_REG32	BANKCON[8];
 	S3C24X0_REG32	REFRESH;
 	S3C24X0_REG32	BANKSIZE;
 	S3C24X0_REG32	MRSRB6;
 	S3C24X0_REG32	MRSRB7;
-} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
+};
 
 
 /* USB HOST (see manual chapter 12) */
-typedef struct {
+struct s3c24x0_usb_host {
 	S3C24X0_REG32	HcRevision;
 	S3C24X0_REG32	HcControl;
 	S3C24X0_REG32	HcCommonStatus;
@@ -71,11 +71,11 @@ typedef struct {
 	S3C24X0_REG32	HcRhStatus;
 	S3C24X0_REG32	HcRhPortStatus1;
 	S3C24X0_REG32	HcRhPortStatus2;
-} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
+};
 
 
 /* INTERRUPT (see manual chapter 14) */
-typedef struct {
+struct s3c24x0_interrupt {
 	S3C24X0_REG32	SRCPND;
 	S3C24X0_REG32	INTMOD;
 	S3C24X0_REG32	INTMSK;
@@ -86,11 +86,11 @@ typedef struct {
 	S3C24X0_REG32	SUBSRCPND;
 	S3C24X0_REG32	INTSUBMSK;
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
+};
 
 
 /* DMAS (see manual chapter 8) */
-typedef struct {
+struct s3c24x0_dma {
 	S3C24X0_REG32	DISRC;
 #ifdef CONFIG_S3C2410
 	S3C24X0_REG32	DISRCC;
@@ -110,27 +110,27 @@ typedef struct {
 #ifdef CONFIG_S3C2410
 	S3C24X0_REG32	res[7];
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_DMA;
+};
 
-typedef struct {
-	S3C24X0_DMA	dma[4];
-} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
+struct s3c24x0_dmas {
+	struct s3c24x0_dma	dma[4];
+};
 
 
 /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
 /*                          (see S3C2410 manual chapter 7) */
-typedef struct {
+struct s3c24x0_clock_power {
 	S3C24X0_REG32	LOCKTIME;
 	S3C24X0_REG32	MPLLCON;
 	S3C24X0_REG32	UPLLCON;
 	S3C24X0_REG32	CLKCON;
 	S3C24X0_REG32	CLKSLOW;
 	S3C24X0_REG32	CLKDIVN;
-} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+};
 
 
 /* LCD CONTROLLER (see manual chapter 15) */
-typedef struct {
+struct s3c24x0_lcd {
 	S3C24X0_REG32	LCDCON1;
 	S3C24X0_REG32	LCDCON2;
 	S3C24X0_REG32	LCDCON3;
@@ -151,22 +151,22 @@ typedef struct {
 	S3C24X0_REG32	LCDINTMSK;
 	S3C24X0_REG32	LPCSEL;
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_LCD;
+};
 
 
 /* NAND FLASH (see S3C2410 manual chapter 6) */
-typedef struct {
+struct s3c2410_nand {
 	S3C24X0_REG32	NFCONF;
 	S3C24X0_REG32	NFCMD;
 	S3C24X0_REG32	NFADDR;
 	S3C24X0_REG32	NFDATA;
 	S3C24X0_REG32	NFSTAT;
 	S3C24X0_REG32	NFECC;
-} /*__attribute__((__packed__))*/ S3C2410_NAND;
+};
 
 
 /* UART (see manual chapter 11) */
-typedef struct {
+struct s3c24x0_uart {
 	S3C24X0_REG32	ULCON;
 	S3C24X0_REG32	UCON;
 	S3C24X0_REG32	UFCON;
@@ -187,28 +187,28 @@ typedef struct {
 	S3C24X0_REG8	res2[3];
 #endif
 	S3C24X0_REG32	UBRDIV;
-} /*__attribute__((__packed__))*/ S3C24X0_UART;
+};
 
 
 /* PWM TIMER (see manual chapter 10) */
-typedef struct {
+struct s3c24x0_timer {
 	S3C24X0_REG32	TCNTB;
 	S3C24X0_REG32	TCMPB;
 	S3C24X0_REG32	TCNTO;
-} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
+};
 
-typedef struct {
-	S3C24X0_REG32	TCFG0;
-	S3C24X0_REG32	TCFG1;
-	S3C24X0_REG32	TCON;
-	S3C24X0_TIMER	ch[4];
-	S3C24X0_REG32	TCNTB4;
-	S3C24X0_REG32	TCNTO4;
-} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
+struct s3c24x0_timers {
+	S3C24X0_REG32		TCFG0;
+	S3C24X0_REG32		TCFG1;
+	S3C24X0_REG32		TCON;
+	struct s3c24x0_timer	ch[4];
+	S3C24X0_REG32		TCNTB4;
+	S3C24X0_REG32		TCNTO4;
+};
 
 
 /* USB DEVICE (see manual chapter 13) */
-typedef struct {
+struct s3c24x0_usb_dev_fifos {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG8	res[3];
 	S3C24X0_REG8	EP_FIFO_REG;
@@ -216,9 +216,9 @@ typedef struct {
 	S3C24X0_REG8	EP_FIFO_REG;
 	S3C24X0_REG8	res[3];
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
+};
 
-typedef struct {
+struct s3c24x0_usb_dev_dmas {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG8	res1[3];
 	S3C24X0_REG8	EP_DMA_CON;
@@ -246,9 +246,9 @@ typedef struct {
 	S3C24X0_REG8	EP_DMA_TTC_H;
 	S3C24X0_REG8	res6[3];
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
+};
 
-typedef struct {
+struct s3c24x0_usb_device {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG8	res1[3];
 	S3C24X0_REG8	FUNC_ADDR_REG;
@@ -316,30 +316,30 @@ typedef struct {
 	S3C24X0_REG8	OUT_FIFO_CNT2_REG;
 	S3C24X0_REG8	res16[3];
 #endif /*  __BIG_ENDIAN */
-	S3C24X0_USB_DEV_FIFOS	fifo[5];
-	S3C24X0_USB_DEV_DMAS	dma[5];
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
+	struct s3c24x0_usb_dev_fifos	fifo[5];
+	struct s3c24x0_usb_dev_dmas	dma[5];
+};
 
 
 /* WATCH DOG TIMER (see manual chapter 18) */
-typedef struct {
+struct s3c24x0_watchdog {
 	S3C24X0_REG32	WTCON;
 	S3C24X0_REG32	WTDAT;
 	S3C24X0_REG32	WTCNT;
-} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
+};
 
 
 /* IIC (see manual chapter 20) */
-typedef struct {
+struct s3c24x0_i2c {
 	S3C24X0_REG32	IICCON;
 	S3C24X0_REG32	IICSTAT;
 	S3C24X0_REG32	IICADD;
 	S3C24X0_REG32	IICDS;
-} /*__attribute__((__packed__))*/ S3C24X0_I2C;
+};
 
 
 /* IIS (see manual chapter 21) */
-typedef struct {
+struct s3c24x0_i2s {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG16	res1;
 	S3C24X0_REG16	IISCON;
@@ -363,11 +363,11 @@ typedef struct {
 	S3C24X0_REG16	IISFIFO;
 	S3C24X0_REG16	res5;
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_I2S;
+};
 
 
 /* I/O PORT (see manual chapter 9) */
-typedef struct {
+struct s3c24x0_gpio {
 #ifdef CONFIG_S3C2400
 	S3C24X0_REG32	PACON;
 	S3C24X0_REG32	PADAT;
@@ -451,11 +451,11 @@ typedef struct {
 	S3C24X0_REG32	GSTATUS3;
 	S3C24X0_REG32	GSTATUS4;
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
+};
 
 
 /* RTC (see manual chapter 17) */
-typedef struct {
+struct s3c24x0_rtc {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG8	res1[67];
 	S3C24X0_REG8	RTCCON;
@@ -528,28 +528,28 @@ typedef struct {
 	S3C24X0_REG8	BCDYEAR;
 	S3C24X0_REG8	res17[3];
 #endif
-} /*__attribute__((__packed__))*/ S3C24X0_RTC;
+};
 
 
 /* ADC (see manual chapter 16) */
-typedef struct {
+struct s3c2400_adc {
 	S3C24X0_REG32	ADCCON;
 	S3C24X0_REG32	ADCDAT;
-} /*__attribute__((__packed__))*/ S3C2400_ADC;
+};
 
 
 /* ADC (see manual chapter 16) */
-typedef struct {
+struct s3c2410_adc {
 	S3C24X0_REG32	ADCCON;
 	S3C24X0_REG32	ADCTSC;
 	S3C24X0_REG32	ADCDLY;
 	S3C24X0_REG32	ADCDAT0;
 	S3C24X0_REG32	ADCDAT1;
-} /*__attribute__((__packed__))*/ S3C2410_ADC;
+};
 
 
 /* SPI (see manual chapter 22) */
-typedef struct {
+struct s3c24x0_spi_channel {
 	S3C24X0_REG8	SPCON;
 	S3C24X0_REG8	res1[3];
 	S3C24X0_REG8	SPSTA;
@@ -563,15 +563,15 @@ typedef struct {
 	S3C24X0_REG8	SPRDAT;
 	S3C24X0_REG8	res6[3];
 	S3C24X0_REG8	res7[16];
-} /*__attribute__((__packed__))*/ S3C24X0_SPI_CHANNEL;
+};
 
-typedef struct {
-	S3C24X0_SPI_CHANNEL	ch[S3C24X0_SPI_CHANNELS];
-} /*__attribute__((__packed__))*/ S3C24X0_SPI;
+struct s3c24x0_spi {
+	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
+};
 
 
 /* MMC INTERFACE (see S3C2400 manual chapter 19) */
-typedef struct {
+struct s3c2400_mmc {
 #ifdef __BIG_ENDIAN
 	S3C24X0_REG8	res1[3];
 	S3C24X0_REG8	MMCON;
@@ -623,11 +623,11 @@ typedef struct {
 	S3C24X0_REG8	MMDAT;
 	S3C24X0_REG8	res11[3];
 #endif
-} /*__attribute__((__packed__))*/ S3C2400_MMC;
+};
 
 
 /* SD INTERFACE (see S3C2410 manual chapter 19) */
-typedef struct {
+struct s3c2410_sdi {
 	S3C24X0_REG32	SDICON;
 	S3C24X0_REG32	SDIPRE;
 	S3C24X0_REG32	SDICARG;
@@ -651,491 +651,6 @@ typedef struct {
 	S3C24X0_REG8	res[3];
 #endif
 	S3C24X0_REG32	SDIIMSK;
-} /*__attribute__((__packed__))*/ S3C2410_SDI;
-
-
-#if 0
-/* Memory control */
-#define rBWSCON			(*(volatile unsigned *)0x48000000)
-#define rBANKCON0		(*(volatile unsigned *)0x48000004)
-#define rBANKCON1		(*(volatile unsigned *)0x48000008)
-#define rBANKCON2		(*(volatile unsigned *)0x4800000C)
-#define rBANKCON3		(*(volatile unsigned *)0x48000010)
-#define rBANKCON4		(*(volatile unsigned *)0x48000014)
-#define rBANKCON5		(*(volatile unsigned *)0x48000018)
-#define rBANKCON6		(*(volatile unsigned *)0x4800001C)
-#define rBANKCON7		(*(volatile unsigned *)0x48000020)
-#define rREFRESH		(*(volatile unsigned *)0x48000024)
-#define rBANKSIZE		(*(volatile unsigned *)0x48000028)
-#define rMRSRB6			(*(volatile unsigned *)0x4800002C)
-#define rMRSRB7			(*(volatile unsigned *)0x48000030)
-
-
-/* USB HOST */
-#define rHcRevision		(*(volatile unsigned *)0x49000000)
-#define rHcControl		(*(volatile unsigned *)0x49000004)
-#define rHcCommonStatus		(*(volatile unsigned *)0x49000008)
-#define rHcInterruptStatus	(*(volatile unsigned *)0x4900000C)
-#define rHcInterruptEnable	(*(volatile unsigned *)0x49000010)
-#define rHcInterruptDisable	(*(volatile unsigned *)0x49000014)
-#define rHcHCCA			(*(volatile unsigned *)0x49000018)
-#define rHcPeriodCuttendED	(*(volatile unsigned *)0x4900001C)
-#define rHcControlHeadED	(*(volatile unsigned *)0x49000020)
-#define rHcControlCurrentED	(*(volatile unsigned *)0x49000024)
-#define rHcBulkHeadED		(*(volatile unsigned *)0x49000028)
-#define rHcBuldCurrentED	(*(volatile unsigned *)0x4900002C)
-#define rHcDoneHead		(*(volatile unsigned *)0x49000030)
-#define rHcRmInterval		(*(volatile unsigned *)0x49000034)
-#define rHcFmRemaining		(*(volatile unsigned *)0x49000038)
-#define rHcFmNumber		(*(volatile unsigned *)0x4900003C)
-#define rHcPeriodicStart	(*(volatile unsigned *)0x49000040)
-#define rHcLSThreshold		(*(volatile unsigned *)0x49000044)
-#define rHcRhDescriptorA	(*(volatile unsigned *)0x49000048)
-#define rHcRhDescriptorB	(*(volatile unsigned *)0x4900004C)
-#define rHcRhStatus		(*(volatile unsigned *)0x49000050)
-#define rHcRhPortStatus1	(*(volatile unsigned *)0x49000054)
-#define rHcRhPortStatus2	(*(volatile unsigned *)0x49000058)
-
-
-/* INTERRUPT */
-#define rSRCPND			(*(volatile unsigned *)0x4A000000)
-#define rINTMOD			(*(volatile unsigned *)0x4A000004)
-#define rINTMSK			(*(volatile unsigned *)0x4A000008)
-#define rPRIORITY		(*(volatile unsigned *)0x4A00000C)
-#define rINTPND			(*(volatile unsigned *)0x4A000010)
-#define rINTOFFSET		(*(volatile unsigned *)0x4A000014)
-#define rSUBSRCPND		(*(volatile unsigned *)0x4A000018)
-#define rINTSUBMSK		(*(volatile unsigned *)0x4A00001C)
-
-
-/* DMA */
-#define rDISRC0			(*(volatile unsigned *)0x4B000000)
-#define rDISRCC0		(*(volatile unsigned *)0x4B000004)
-#define rDIDST0			(*(volatile unsigned *)0x4B000008)
-#define rDIDSTC0		(*(volatile unsigned *)0x4B00000C)
-#define rDCON0			(*(volatile unsigned *)0x4B000010)
-#define rDSTAT0			(*(volatile unsigned *)0x4B000014)
-#define rDCSRC0			(*(volatile unsigned *)0x4B000018)
-#define rDCDST0			(*(volatile unsigned *)0x4B00001C)
-#define rDMASKTRIG0		(*(volatile unsigned *)0x4B000020)
-#define rDISRC1			(*(volatile unsigned *)0x4B000040)
-#define rDISRCC1		(*(volatile unsigned *)0x4B000044)
-#define rDIDST1			(*(volatile unsigned *)0x4B000048)
-#define rDIDSTC1		(*(volatile unsigned *)0x4B00004C)
-#define rDCON1			(*(volatile unsigned *)0x4B000050)
-#define rDSTAT1			(*(volatile unsigned *)0x4B000054)
-#define rDCSRC1			(*(volatile unsigned *)0x4B000058)
-#define rDCDST1			(*(volatile unsigned *)0x4B00005C)
-#define rDMASKTRIG1		(*(volatile unsigned *)0x4B000060)
-#define rDISRC2			(*(volatile unsigned *)0x4B000080)
-#define rDISRCC2		(*(volatile unsigned *)0x4B000084)
-#define rDIDST2			(*(volatile unsigned *)0x4B000088)
-#define rDIDSTC2		(*(volatile unsigned *)0x4B00008C)
-#define rDCON2			(*(volatile unsigned *)0x4B000090)
-#define rDSTAT2			(*(volatile unsigned *)0x4B000094)
-#define rDCSRC2			(*(volatile unsigned *)0x4B000098)
-#define rDCDST2			(*(volatile unsigned *)0x4B00009C)
-#define rDMASKTRIG2		(*(volatile unsigned *)0x4B0000A0)
-#define rDISRC3			(*(volatile unsigned *)0x4B0000C0)
-#define rDISRCC3		(*(volatile unsigned *)0x4B0000C4)
-#define rDIDST3			(*(volatile unsigned *)0x4B0000C8)
-#define rDIDSTC3		(*(volatile unsigned *)0x4B0000CC)
-#define rDCON3			(*(volatile unsigned *)0x4B0000D0)
-#define rDSTAT3			(*(volatile unsigned *)0x4B0000D4)
-#define rDCSRC3			(*(volatile unsigned *)0x4B0000D8)
-#define rDCDST3			(*(volatile unsigned *)0x4B0000DC)
-#define rDMASKTRIG3		(*(volatile unsigned *)0x4B0000E0)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME		(*(volatile unsigned *)0x4C000000)
-#define rMPLLCON		(*(volatile unsigned *)0x4C000004)
-#define rUPLLCON		(*(volatile unsigned *)0x4C000008)
-#define rCLKCON			(*(volatile unsigned *)0x4C00000C)
-#define rCLKSLOW		(*(volatile unsigned *)0x4C000010)
-#define rCLKDIVN		(*(volatile unsigned *)0x4C000014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1		(*(volatile unsigned *)0x4D000000)
-#define rLCDCON2		(*(volatile unsigned *)0x4D000004)
-#define rLCDCON3		(*(volatile unsigned *)0x4D000008)
-#define rLCDCON4		(*(volatile unsigned *)0x4D00000C)
-#define rLCDCON5		(*(volatile unsigned *)0x4D000010)
-#define rLCDSADDR1		(*(volatile unsigned *)0x4D000014)
-#define rLCDSADDR2		(*(volatile unsigned *)0x4D000018)
-#define rLCDSADDR3		(*(volatile unsigned *)0x4D00001C)
-#define rREDLUT			(*(volatile unsigned *)0x4D000020)
-#define rGREENLUT		(*(volatile unsigned *)0x4D000024)
-#define rBLUELUT		(*(volatile unsigned *)0x4D000028)
-#define rDITHMODE		(*(volatile unsigned *)0x4D00004C)
-#define rTPAL			(*(volatile unsigned *)0x4D000050)
-#define rLCDINTPND		(*(volatile unsigned *)0x4D000054)
-#define rLCDSRCPND		(*(volatile unsigned *)0x4D000058)
-#define rLCDINTMSK		(*(volatile unsigned *)0x4D00005C)
-
-
-/* NAND FLASH */
-#define rNFCONF			(*(volatile unsigned *)0x4E000000)
-#define rNFCMD			(*(volatile unsigned *)0x4E000004)
-#define rNFADDR			(*(volatile unsigned *)0x4E000008)
-#define rNFDATA			(*(volatile unsigned *)0x4E00000C)
-#define rNFSTAT			(*(volatile unsigned *)0x4E000010)
-#define rNFECC			(*(volatile unsigned *)0x4E000014)
-
-
-/* UART */
-#define rULCON0			(*(volatile unsigned *)0x50000000)
-#define rUCON0			(*(volatile unsigned *)0x50000004)
-#define rUFCON0			(*(volatile unsigned *)0x50000008)
-#define rUMCON0			(*(volatile unsigned *)0x5000000C)
-#define rUTRSTAT0		(*(volatile unsigned *)0x50000010)
-#define rUERSTAT0		(*(volatile unsigned *)0x50000014)
-#define rUFSTAT0		(*(volatile unsigned *)0x50000018)
-#define rUMSTAT0		(*(volatile unsigned *)0x5000001C)
-#define rUBRDIV0		(*(volatile unsigned *)0x50000028)
-
-#define rULCON1			(*(volatile unsigned *)0x50004000)
-#define rUCON1			(*(volatile unsigned *)0x50004004)
-#define rUFCON1			(*(volatile unsigned *)0x50004008)
-#define rUMCON1			(*(volatile unsigned *)0x5000400C)
-#define rUTRSTAT1		(*(volatile unsigned *)0x50004010)
-#define rUERSTAT1		(*(volatile unsigned *)0x50004014)
-#define rUFSTAT1		(*(volatile unsigned *)0x50004018)
-#define rUMSTAT1		(*(volatile unsigned *)0x5000401C)
-#define rUBRDIV1		(*(volatile unsigned *)0x50004028)
-
-#define rULCON2			(*(volatile unsigned *)0x50008000)
-#define rUCON2			(*(volatile unsigned *)0x50008004)
-#define rUFCON2			(*(volatile unsigned *)0x50008008)
-#define rUTRSTAT2		(*(volatile unsigned *)0x50008010)
-#define rUERSTAT2		(*(volatile unsigned *)0x50008014)
-#define rUFSTAT2		(*(volatile unsigned *)0x50008018)
-#define rUBRDIV2		(*(volatile unsigned *)0x50008028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0			(*(volatile unsigned char *)0x50000023)
-#define rURXH0			(*(volatile unsigned char *)0x50000027)
-#define rUTXH1			(*(volatile unsigned char *)0x50004023)
-#define rURXH1			(*(volatile unsigned char *)0x50004027)
-#define rUTXH2			(*(volatile unsigned char *)0x50008023)
-#define rURXH2			(*(volatile unsigned char *)0x50008027)
-
-#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
-#define RdURXH0()		(*(volatile unsigned char *)0x50000027)
-#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
-#define RdURXH1()		(*(volatile unsigned char *)0x50004027)
-#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
-#define RdURXH2()		(*(volatile unsigned char *)0x50008027)
-
-#define UTXH0			(0x50000020+3)  /* byte_access address by DMA */
-#define URXH0			(0x50000024+3)
-#define UTXH1			(0x50004020+3)
-#define URXH1			(0x50004024+3)
-#define UTXH2			(0x50008020+3)
-#define URXH2			(0x50008024+3)
-
-#else /* Little Endian */
-#define rUTXH0			(*(volatile unsigned char *)0x50000020)
-#define rURXH0			(*(volatile unsigned char *)0x50000024)
-#define rUTXH1			(*(volatile unsigned char *)0x50004020)
-#define rURXH1			(*(volatile unsigned char *)0x50004024)
-#define rUTXH2			(*(volatile unsigned char *)0x50008020)
-#define rURXH2			(*(volatile unsigned char *)0x50008024)
-
-#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
-#define RdURXH0()		(*(volatile unsigned char *)0x50000024)
-#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
-#define RdURXH1()		(*(volatile unsigned char *)0x50004024)
-#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
-#define RdURXH2()		(*(volatile unsigned char *)0x50008024)
-
-#define UTXH0			(0x50000020)    /* byte_access address by DMA */
-#define URXH0			(0x50000024)
-#define UTXH1			(0x50004020)
-#define URXH1			(0x50004024)
-#define UTXH2			(0x50008020)
-#define URXH2			(0x50008024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0			(*(volatile unsigned *)0x51000000)
-#define rTCFG1			(*(volatile unsigned *)0x51000004)
-#define rTCON			(*(volatile unsigned *)0x51000008)
-#define rTCNTB0			(*(volatile unsigned *)0x5100000C)
-#define rTCMPB0			(*(volatile unsigned *)0x51000010)
-#define rTCNTO0			(*(volatile unsigned *)0x51000014)
-#define rTCNTB1			(*(volatile unsigned *)0x51000018)
-#define rTCMPB1			(*(volatile unsigned *)0x5100001C)
-#define rTCNTO1			(*(volatile unsigned *)0x51000020)
-#define rTCNTB2			(*(volatile unsigned *)0x51000024)
-#define rTCMPB2			(*(volatile unsigned *)0x51000028)
-#define rTCNTO2			(*(volatile unsigned *)0x5100002C)
-#define rTCNTB3			(*(volatile unsigned *)0x51000030)
-#define rTCMPB3			(*(volatile unsigned *)0x51000034)
-#define rTCNTO3			(*(volatile unsigned *)0x51000038)
-#define rTCNTB4			(*(volatile unsigned *)0x5100003C)
-#define rTCNTO4			(*(volatile unsigned *)0x51000040)
-
-
-/* USB DEVICE */
-#ifdef __BIG_ENDIAN
-#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000143)
-#define rPWR_REG		(*(volatile unsigned char *)0x52000147)
-#define rEP_INT_REG		(*(volatile unsigned char *)0x5200014B)
-#define rUSB_INT_REG		(*(volatile unsigned char *)0x5200015B)
-#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015F)
-#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016F)
-#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000173)
-#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000177)
-#define rINDEX_REG		(*(volatile unsigned char *)0x5200017B)
-#define rMAXP_REG		(*(volatile unsigned char *)0x52000183)
-#define rEP0_CSR		(*(volatile unsigned char *)0x52000187)
-#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000187)
-#define rIN_CSR2_REG		(*(volatile unsigned char *)0x5200018B)
-#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000193)
-#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000197)
-#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x5200019B)
-#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019F)
-#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C3)
-#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C7)
-#define rEP2_FIFO		(*(volatile unsigned char *)0x520001CB)
-#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CF)
-#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D3)
-#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000203)
-#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000207)
-#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x5200020B)
-#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020F)
-#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000213)
-#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000217)
-#define rEP2_DMA_CON		(*(volatile unsigned char *)0x5200021B)
-#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021F)
-#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000223)
-#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000227)
-#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x5200022B)
-#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022F)
-#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000243)
-#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000247)
-#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x5200024B)
-#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024F)
-#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000253)
-#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000257)
-#define rEP4_DMA_CON		(*(volatile unsigned char *)0x5200025B)
-#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025F)
-#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000263)
-#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000267)
-#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x5200026B)
-#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026F)
-#else /*  little endian */
-#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000140)
-#define rPWR_REG		(*(volatile unsigned char *)0x52000144)
-#define rEP_INT_REG		(*(volatile unsigned char *)0x52000148)
-#define rUSB_INT_REG		(*(volatile unsigned char *)0x52000158)
-#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015C)
-#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016C)
-#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000170)
-#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000174)
-#define rINDEX_REG		(*(volatile unsigned char *)0x52000178)
-#define rMAXP_REG		(*(volatile unsigned char *)0x52000180)
-#define rEP0_CSR		(*(volatile unsigned char *)0x52000184)
-#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000184)
-#define rIN_CSR2_REG		(*(volatile unsigned char *)0x52000188)
-#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000190)
-#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000194)
-#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x52000198)
-#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019C)
-#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C0)
-#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C4)
-#define rEP2_FIFO		(*(volatile unsigned char *)0x520001C8)
-#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CC)
-#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D0)
-#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000200)
-#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000204)
-#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x52000208)
-#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020C)
-#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000210)
-#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000214)
-#define rEP2_DMA_CON		(*(volatile unsigned char *)0x52000218)
-#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021C)
-#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000220)
-#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000224)
-#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x52000228)
-#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022C)
-#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000240)
-#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000244)
-#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x52000248)
-#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024C)
-#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000250)
-#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000254)
-#define rEP4_DMA_CON		(*(volatile unsigned char *)0x52000258)
-#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025C)
-#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000260)
-#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000264)
-#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x52000268)
-#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026C)
-#endif /*  __BIG_ENDIAN */
-
-
-/* WATCH DOG TIMER */
-#define rWTCON			(*(volatile unsigned *)0x53000000)
-#define rWTDAT			(*(volatile unsigned *)0x53000004)
-#define rWTCNT			(*(volatile unsigned *)0x53000008)
-
-
-/* IIC */
-#define rIICCON			(*(volatile unsigned *)0x54000000)
-#define rIICSTAT		(*(volatile unsigned *)0x54000004)
-#define rIICADD			(*(volatile unsigned *)0x54000008)
-#define rIICDS			(*(volatile unsigned *)0x5400000C)
-
-
-/* IIS */
-#define rIISCON			(*(volatile unsigned *)0x55000000)
-#define rIISMOD			(*(volatile unsigned *)0x55000004)
-#define rIISPSR			(*(volatile unsigned *)0x55000008)
-#define rIISFCON		(*(volatile unsigned *)0x5500000C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF			((volatile unsigned short *)0x55000012)
-#else /*  little endian */
-#define IISFIF			((volatile unsigned short *)0x55000010)
-#endif
-
-
-/* I/O PORT */
-#define rGPACON			(*(volatile unsigned *)0x56000000)
-#define rGPADAT			(*(volatile unsigned *)0x56000004)
-
-#define rGPBCON			(*(volatile unsigned *)0x56000010)
-#define rGPBDAT			(*(volatile unsigned *)0x56000014)
-#define rGPBUP			(*(volatile unsigned *)0x56000018)
-
-#define rGPCCON			(*(volatile unsigned *)0x56000020)
-#define rGPCDAT			(*(volatile unsigned *)0x56000024)
-#define rGPCUP			(*(volatile unsigned *)0x56000028)
-
-#define rGPDCON			(*(volatile unsigned *)0x56000030)
-#define rGPDDAT			(*(volatile unsigned *)0x56000034)
-#define rGPDUP			(*(volatile unsigned *)0x56000038)
-
-#define rGPECON			(*(volatile unsigned *)0x56000040)
-#define rGPEDAT			(*(volatile unsigned *)0x56000044)
-#define rGPEUP			(*(volatile unsigned *)0x56000048)
-
-#define rGPFCON			(*(volatile unsigned *)0x56000050)
-#define rGPFDAT			(*(volatile unsigned *)0x56000054)
-#define rGPFUP			(*(volatile unsigned *)0x56000058)
-
-#define rGPGCON			(*(volatile unsigned *)0x56000060)
-#define rGPGDAT			(*(volatile unsigned *)0x56000064)
-#define rGPGUP			(*(volatile unsigned *)0x56000068)
-
-#define rGPHCON			(*(volatile unsigned *)0x56000070)
-#define rGPHDAT			(*(volatile unsigned *)0x56000074)
-#define rGPHUP			(*(volatile unsigned *)0x56000078)
-
-#define rMISCCR			(*(volatile unsigned *)0x56000080)
-#define rDCLKCON		(*(volatile unsigned *)0x56000084)
-#define rEXTINT0		(*(volatile unsigned *)0x56000088)
-#define rEXTINT1		(*(volatile unsigned *)0x5600008C)
-#define rEXTINT2		(*(volatile unsigned *)0x56000090)
-#define rEINTFLT0		(*(volatile unsigned *)0x56000094)
-#define rEINTFLT1		(*(volatile unsigned *)0x56000098)
-#define rEINTFLT2		(*(volatile unsigned *)0x5600009C)
-#define rEINTFLT3		(*(volatile unsigned *)0x560000A0)
-#define rEINTMASK		(*(volatile unsigned *)0x560000A4)
-#define rEINTPEND		(*(volatile unsigned *)0x560000A8)
-#define rGSTATUS0		(*(volatile unsigned *)0x560000AC)
-#define rGSTATUS1		(*(volatile unsigned *)0x560000B0)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON			(*(volatile unsigned char *)0x57000043)
-#define rTICNT			(*(volatile unsigned char *)0x57000047)
-#define rRTCALM			(*(volatile unsigned char *)0x57000053)
-#define rALMSEC			(*(volatile unsigned char *)0x57000057)
-#define rALMMIN			(*(volatile unsigned char *)0x5700005B)
-#define rALMHOUR		(*(volatile unsigned char *)0x5700005F)
-#define rALMDATE		(*(volatile unsigned char *)0x57000063)
-#define rALMMON			(*(volatile unsigned char *)0x57000067)
-#define rALMYEAR		(*(volatile unsigned char *)0x5700006B)
-#define rRTCRST			(*(volatile unsigned char *)0x5700006F)
-#define rBCDSEC			(*(volatile unsigned char *)0x57000073)
-#define rBCDMIN			(*(volatile unsigned char *)0x57000077)
-#define rBCDHOUR		(*(volatile unsigned char *)0x5700007B)
-#define rBCDDATE		(*(volatile unsigned char *)0x5700007F)
-#define rBCDDAY			(*(volatile unsigned char *)0x57000083)
-#define rBCDMON			(*(volatile unsigned char *)0x57000087)
-#define rBCDYEAR		(*(volatile unsigned char *)0x5700008B)
-#else /*  little endian */
-#define rRTCCON			(*(volatile unsigned char *)0x57000040)
-#define rTICNT			(*(volatile unsigned char *)0x57000044)
-#define rRTCALM			(*(volatile unsigned char *)0x57000050)
-#define rALMSEC			(*(volatile unsigned char *)0x57000054)
-#define rALMMIN			(*(volatile unsigned char *)0x57000058)
-#define rALMHOUR		(*(volatile unsigned char *)0x5700005C)
-#define rALMDATE		(*(volatile unsigned char *)0x57000060)
-#define rALMMON			(*(volatile unsigned char *)0x57000064)
-#define rALMYEAR		(*(volatile unsigned char *)0x57000068)
-#define rRTCRST			(*(volatile unsigned char *)0x5700006C)
-#define rBCDSEC			(*(volatile unsigned char *)0x57000070)
-#define rBCDMIN			(*(volatile unsigned char *)0x57000074)
-#define rBCDHOUR		(*(volatile unsigned char *)0x57000078)
-#define rBCDDATE		(*(volatile unsigned char *)0x5700007C)
-#define rBCDDAY			(*(volatile unsigned char *)0x57000080)
-#define rBCDMON			(*(volatile unsigned char *)0x57000084)
-#define rBCDYEAR		(*(volatile unsigned char *)0x57000088)
-#endif
-
-
-/* ADC */
-#define rADCCON			(*(volatile unsigned *)0x58000000)
-#define rADCTSC			(*(volatile unsigned *)0x58000004)
-#define rADCDLY			(*(volatile unsigned *)0x58000008)
-#define rADCDAT0		(*(volatile unsigned *)0x5800000C)
-#define rADCDAT1		(*(volatile unsigned *)0x58000010)
-
-
-/* SPI */
-#define rSPCON0			(*(volatile unsigned *)0x59000000)
-#define rSPSTA0			(*(volatile unsigned *)0x59000004)
-#define rSPPIN0			(*(volatile unsigned *)0x59000008)
-#define rSPPRE0			(*(volatile unsigned *)0x5900000C)
-#define rSPTDAT0		(*(volatile unsigned *)0x59000010)
-#define rSPRDAT0		(*(volatile unsigned *)0x59000014)
-#define rSPCON1			(*(volatile unsigned *)0x59000020)
-#define rSPSTA1			(*(volatile unsigned *)0x59000024)
-#define rSPPIN1			(*(volatile unsigned *)0x59000028)
-#define rSPPRE1			(*(volatile unsigned *)0x5900002C)
-#define rSPTDAT1		(*(volatile unsigned *)0x59000030)
-#define rSPRDAT1		(*(volatile unsigned *)0x59000034)
-
-
-/* SD INTERFACE */
-#define rSDICON			(*(volatile unsigned *)0x5A000000)
-#define rSDIPRE			(*(volatile unsigned *)0x5A000004)
-#define rSDICmdArg		(*(volatile unsigned *)0x5A000008)
-#define rSDICmdCon		(*(volatile unsigned *)0x5A00000C)
-#define rSDICmdSta		(*(volatile unsigned *)0x5A000010)
-#define rSDIRSP0		(*(volatile unsigned *)0x5A000014)
-#define rSDIRSP1		(*(volatile unsigned *)0x5A000018)
-#define rSDIRSP2		(*(volatile unsigned *)0x5A00001C)
-#define rSDIRSP3		(*(volatile unsigned *)0x5A000020)
-#define rSDIDTimer		(*(volatile unsigned *)0x5A000024)
-#define rSDIBSize		(*(volatile unsigned *)0x5A000028)
-#define rSDIDatCon		(*(volatile unsigned *)0x5A00002C)
-#define rSDIDatCnt		(*(volatile unsigned *)0x5A000030)
-#define rSDIDatSta		(*(volatile unsigned *)0x5A000034)
-#define rSDIFSTA		(*(volatile unsigned *)0x5A000038)
-#ifdef __BIG_ENDIAN
-#define rSDIDAT			(*(volatile unsigned char *)0x5A00003F)
-#else
-#define rSDIDAT			(*(volatile unsigned char *)0x5A00003C)
-#endif
-#define rSDIIntMsk		(*(volatile unsigned *)0x5A000040)
-
-#endif
+};
 
 #endif /*__S3C24X0_H__*/
diff --git a/include/serial.h b/include/serial.h
index 821b58399d..bbda3f08c6 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -43,6 +43,13 @@ extern struct serial_device s3c24xx_serial1_device;
 extern struct serial_device s3c24xx_serial2_device;
 #endif
 
+#if defined(CONFIG_S5PC1XX)
+extern struct serial_device s5pc1xx_serial0_device;
+extern struct serial_device s5pc1xx_serial1_device;
+extern struct serial_device s5pc1xx_serial2_device;
+extern struct serial_device s5pc1xx_serial3_device;
+#endif
+
 #if defined(CONFIG_OMAP3_ZOOM2)
 extern struct serial_device zoom2_serial_device0;
 extern struct serial_device zoom2_serial_device1;