Merge tag 'v2014.10' into 2014.10-toradex-next

Prepare v2014.10

60 files changed, 1169 insertions, 3234 deletions

diff --git a/include/compiler.h b/include/compiler.h
index 14519163a3..21036022d7 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -48,6 +48,10 @@
 # include <machine/endian.h>
 typedef unsigned long ulong;
 #endif
+#ifdef __FreeBSD__
+# include <sys/endian.h> /* htole32 and friends */
+#endif
+
 #include <time.h>
 
 typedef uint8_t __u8;
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
deleted file mode 100644
index 788fa0f91c..0000000000
--- a/include/configs/CRAYL1.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_CRAYL1
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
-
-/*
- * Note: I make an "image" from U-Boot itself, which prefixes 0x40
- * bytes of header info, hence start address is thus shifted.
- */
-#define	CONFIG_SYS_TEXT_BASE	0xFFFD0040
-
-#define CONFIG_SYS_CLK_FREQ 25000000
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		    1	/* MII PHY management */
-#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
-#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
- * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
- #define CONFIG_PRAM			16
- */
-#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
-#undef CONFIG_BOOTARGS
-
-/* Bootcmd is overridden by the bootscript in board/cray/L1
- */
-#define	CONFIG_SYS_AUTOLOAD		"no"
-#define CONFIG_BOOTCOMMAND	"dhcp"
-
-/*
- * ..during experiments..
- #define CONFIG_SERVERIP         10.0.0.1
- #define CONFIG_ETHADDR          00:40:a6:80:14:5
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SDRAM_BANK0		1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		    400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		    0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_IDENT_STRING     "Cray L1"
-#define CONFIG_ENV_OVERWRITE     1
-#define CONFIG_SYS_HUSH_PARSER			1
-#define CONFIG_SOURCE			1
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * how many time to fail & restart a net-TFTP before giving up & resetting
- * the board hoping that a reset of net interface might help..
- */
-#define CONFIG_NET_RESET 5
-
-/*
- * bauds.  Just to make it compile; in our case, I read the base_baud
- * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
- * drives the system clock.
- */
-#define CONFIG_SYS_BASE_BAUD       403225
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16				/* max number of command args	*/
-
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
-#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-#define CONFIG_SYS_DRAM_TEST		1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
-
-/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
-#define CONFIG_ENV_OFFSET		0x3c8000
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define	CONFIG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
-#define CONFIG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
-
-/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
- * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
- */
-#define CONFIG_SYS_SDRAM_SIZE		32		/* megs of ram */
-#define CONFIG_SYS_MEMTEST_START	0x2000  /* memtest works from the end of */
-									/* the exception vector table */
-									/* to the end of the DRAM  */
-									/* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
-#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
-				+ CONFIG_SYS_MALLOC_LEN \
-				+ CONFIG_ENV_SECT_SIZE \
-				+ CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
-/* END ENVIRONNEMENT FLASH */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in OnChipMem )
- */
-#if 1
-/* On Chip Memory location */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	     */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- */
-#define EEPROM_WRITE_ADDRESS 0xA0
-#define EEPROM_READ_ADDRESS  0xA1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
deleted file mode 100644
index 546b725317..0000000000
--- a/include/configs/KAREF.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
- *		    design.
- ***********************************************************************/
-
-/*
- * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
-#define CONFIG_440GX		  1	     /* Specifc GX support	*/
-#define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
-#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
-#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
-#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/* Here for completeness */
-#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM    1
-#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_BAUDRATE	      9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
-#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
-#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
-
-#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
-
-#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII	      1		     /* MII PHY management	*/
-#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
-#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
-#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
-#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
-#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
-#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
-#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK	      255.255.0.0
-#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
-#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
-
-#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
-
-#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-					     /* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
-#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
-					    to get to the correct offset */
-#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI			     /* include pci support	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
-#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
deleted file mode 100644
index 19ea3167af..0000000000
--- a/include/configs/MERGERBOX.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300	1
-#define CONFIG_MPC837x	1
-#define CONFIG_MPC8377	1
-
-#define CONFIG_SYS_TEXT_BASE	0xFC000000
-
-#define CONFIG_PCI	1
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-
-#define	CONFIG_MASK_AER_AO
-#define CONFIG_DISPLAY_AER_FULL
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-#define CONFIG_TSEC_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
-#define CONFIG_PCIE
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word stored in EEPROM.
- */
-#define CONFIG_SYS_HRCW_LOW	0
-#define CONFIG_SYS_HRCW_HIGH	0
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP	3
-#define CONFIG_SYS_ACR_RPTCNT	3
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP	3
-
-/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM		3
-#define CONFIG_SYS_SCCR_TSEC2CM		0
-#define CONFIG_SYS_SCCR_SDHCCM		3
-#define CONFIG_SYS_SCCR_ENCCM		3 /* also clock for I2C-1 */
-#define CONFIG_SYS_SCCR_USBDRCM		CONFIG_SYS_SCCR_ENCCM /* must match */
-#define CONFIG_SYS_SCCR_PCIEXP1CM	3
-#define CONFIG_SYS_SCCR_PCIEXP2CM	3
-#define CONFIG_SYS_SCCR_PCICM		1
-#define CONFIG_SYS_SCCR_SATACM		0xFF
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH	0x087c0000
-#define CONFIG_SYS_SICRL	0x40000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR		0x30000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_EN | DDRCDR_PZ_HIZ |\
-					 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
-					 DDRCDR_Q_DRN)
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_MODE_WEAK
-#define CONFIG_SYS_DDR_WRITE_DATA_DELAY	2
-#define CONFIG_SYS_DDR_CPO	0x1f
-
-/* SPD table located at offset 0x20 in extended adressing ROM
- * used for HRCW fetch after power-on reset
- */
-#define	CONFIG_SPD_EEPROM
-#define	SPD_EEPROM_ADDRESS	0x50
-#define	SPD_EEPROM_OFFSET	0x20
-#define	SPD_EEPROM_ADDR_LEN	2
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512*1024)
-#define CONFIG_SYS_MALLOC_LEN		(512*1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
-					 GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-#define CONFIG_FSL_ELBC		1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		64
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
-				 BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
-				 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
-				 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
-				 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
-				 OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_NAND_FSL_ELBC		1
-
-#define CONFIG_SYS_NAND_BASE	0xE0600000
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
-				 BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
-				 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
-				 OR_FCM_TRLX | OR_FCM_EHTR)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CONSOLE		ttyS0
-#define CONFIG_BAUDRATE		115200
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1	0xe3000
-#define CONFIG_FSL_SERDES2	0xe3100
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		(256 << 20)
-#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	(256 << 20)
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE		(1 << 20)
-
-#ifdef CONFIG_PCIE
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	(128 << 20)
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	(256 << 20)
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	(8 << 20)
-
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	(128 << 20)
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	(256 << 20)
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	(8 << 20)
-#endif
-
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-
-/*
- * TSEC
- */
-#define CONFIG_GMII			/* MII PHY management */
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define	CONFIG_SYS_VSC8601_SKEW_TX	3
-#define	CONFIG_SYS_VSC8601_SKEW_RX	3
-
-#define CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET		0x24000
-#define TSEC1_PHY_ADDR			0x10
-#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX			0
-
-#define CONFIG_ETHPRIME			"TSEC0"
-#define CONFIG_HAS_ETH0
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET	0x18000
-#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET	0x19000
-#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
-
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SATA
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
-
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	1
-
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_LOAD_ADDR	0x2000000
-#define CONFIG_LOADADDR		0x4000000
-#define CONFIG_SYS_CBSIZE	256
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_SYS_MEMTEST_START	(60<<20)
-#define CONFIG_SYS_MEMTEST_END		(70<<20)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS	1
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE
-
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
-				 BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* unused */
-#define CONFIG_SYS_IBAT1L	(0)
-#define CONFIG_SYS_IBAT1U	(0)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_RW |\
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
-				 BATU_VP)
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* unused */
-#define CONFIG_SYS_IBAT3L	(0)
-#define CONFIG_SYS_IBAT3U	(0)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-/*
- * I2C EEPROM settings
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_SIZE			0x4000
-
-/*
- * Environment Configuration
- */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0xFFD00000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_CMD_BMP
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET	0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
-
-/*
- * SPI
- */
-#define CONFIG_MPC8XXX_SPI
-
-/*
- * USB
- */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-/*
- *
- */
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY	1000
-
-#define MV_CI		"MergerBox"
-#define MV_VCI		"MergerBox"
-#define MV_FPGA_DATA	0xfc100000
-#define MV_FPGA_SIZE	0x00200000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x02800000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-#define MV_FITADDR		0xfc300000
-#define	MV_SPLAH_ADDR		0xffe00000
-
-#define CONFIG_BOOTCOMMAND	"run i2c_init;if test ${boot_sqfs} -eq 1;"\
-				"then; run fitboot;else;run ubiboot;fi;"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200n8"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"console_nr=0\0"\
-	"stdin=serial\0"\
-	"stdout=serial\0"\
-	"stderr=serial\0"\
-	"boot_sqfs=1\0"\
-	"usb_dr_mode=host\0"\
-	"bootfile=MergerBox.fit\0"\
-	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
-	"fpga=0\0"\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
-	"mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
-	"mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
-	"mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
-	"uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
-	"fitaddr=" __stringify(MV_FITADDR) "\0"\
-	"mv_version=" U_BOOT_VERSION "\0"\
-	"mtdids=" MTDIDS_DEFAULT "\0"\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"\
-	"dhcp_client_id=" MV_CI "\0"\
-	"dhcp_vendor-class-identifier=" MV_VCI "\0"\
-	"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
-		"protect off all;erase $uboota +0xC0000;"\
-		"cp.b $loadaddr $uboota $filesize\0"\
-	"upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
-		"cp.b $loadaddr $fpgadata $filesize\0"\
-	"upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
-		"cp.b $loadaddr $fitaddr $filesize\0"\
-	"addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
-		"rootfstype=squashfs\0"\
-	"addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
-		"rootfstype=ubifs\0"\
-	"addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
-		"rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
-	"netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
-	"netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
-	"ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
-	"doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
-	"fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
-		"imxtract $fitaddr ramdisk $mv_initrd_ram;"\
-		"imxtract $fitaddr fdt $mv_dtb_ram\0"\
-	"fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
-	"fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
-	"i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
-	"i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
-		"i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
-		"i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
-	"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
-	"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
-		"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
-	"splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
-	""
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
deleted file mode 100644
index 69ab5bb517..0000000000
--- a/include/configs/METROBOX.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * METROBOX.h - configuration Sandburst MetroBox
- ***********************************************************************/
-
-/*
- * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
- *
- *
- * $Log: METROBOX.h,v $
- * Revision 1.21  2005/06/03 15:05:25  tsawyer
- * MB rev 2.0.3 KA rev 0.0.7.  Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
- *
- * Revision 1.20  2005/04/11 20:51:11  tsawyer
- * fix ethernet
- *
- * Revision 1.19  2005/04/06 15:13:36  tsawyer
- * Update appropriate files to coincide with u-boot 1.1.3
- *
- * Revision 1.18  2005/03/10 14:16:02  tsawyer
- * add def'n for cis8201 short etch option.
- *
- * Revision 1.17  2005/03/09 19:49:51  tsawyer
- * Remove KGDB to allow use of 2nd serial port
- *
- * Revision 1.16  2004/12/02 19:00:23  tsawyer
- * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
- *
- * Revision 1.15  2004/09/15 18:04:12  tsawyer
- * add multiple serial port support
- *
- * Revision 1.14  2004/09/03 15:27:51  tsawyer
- * All metrobox boards are at 66.66 sys clock
- *
- * Revision 1.13  2004/08/05 20:27:46  tsawyer
- * Remove system ace definitions, add net console support
- *
- * Revision 1.12  2004/07/29 20:00:13  tsawyer
- * Add i2c bus 1
- *
- * Revision 1.11  2004/07/21 13:44:18  tsawyer
- * SystemACE is out, CF direct to local bus is in
- *
- * Revision 1.10  2004/06/29 19:08:55  tsawyer
- * Add CONFIG_MISC_INIT_R
- *
- * Revision 1.9	 2004/06/28 21:30:53  tsawyer
- * Fix default BOOTARGS
- *
- * Revision 1.8	 2004/06/17 15:51:08  tsawyer
- * auto complete
- *
- * Revision 1.7	 2004/06/17 15:08:49  tsawyer
- * Add autocomplete
- *
- * Revision 1.6	 2004/06/15 12:33:57  tsawyer
- * debugging checkpoint
- *
- * Revision 1.5	 2004/06/12 19:48:28  tsawyer
- * Debugging checkpoint
- *
- * Revision 1.4	 2004/06/02 13:03:06  tsawyer
- * Fix eth addrs
- *
- * Revision 1.3	 2004/05/18 19:56:10  tsawyer
- * Change default bootcommand to pImage.metrobox
- *
- * Revision 1.2	 2004/05/18 14:13:44  tsawyer
- * Add bringup values for bootargs and bootcommand.
- * Remove definition of ipaddress and serverip addresses.
- *
- * Revision 1.1	 2004/04/16 15:08:54  tsawyer
- * Initial Revision
- *
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
-#define CONFIG_440GX		  1	     /* Specifc GX support	*/
-#define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
-#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
-#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Metrobox"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_FPGA_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM    1
-#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_BAUDRATE	      9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
-#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
-#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
-
-#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
-#define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
-#define CONFIG_BOOTDELAY      5		    /* disable autoboot */
-
-#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII	      1		     /* MII PHY management	*/
-#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
-#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
-#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
-#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
-#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
-#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
-#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK	      255.255.0.0
-#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
-#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
-
-#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
-
-#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-					     /* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
-#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
-					    to get to the correct offset */
-#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI			     /* include pci support	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
-#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 68824fd2d4..147f122967 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /***********************************************************
  * Note that it may also be a MIP405T board which is a subset of the
  * MIP405
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
deleted file mode 100644
index 1ab2b3d51a..0000000000
--- a/include/configs/MVBC_P.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2008
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvBlueCOUGAR-P
-#define MV_VCI			mvBlueCOUGAR-P
-#define MV_FPGA_DATA		0xff860000
-#define MV_FPGA_SIZE		0
-#define MV_KERNEL_ADDR		0xffd00000
-#define MV_INITRD_ADDR		0xff900000
-#define MV_INITRD_LENGTH	0x00400000
-#define MV_SCRATCH_ADDR		0x00000000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-#define MV_SCRIPT_ADDR		0xff840000
-#define MV_SCRIPT_ADDR2		0xff850000
-#define MV_DTB_ADDR		0xfffc0000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define MV_DTB_NAME		mvbc-p.dtb
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		2
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1000
-
-#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
-					then source ${script_addr};	\
-					else source ${script_addr2};	\
-				fi;"
-
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=yes\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
-	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
-	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.90.10\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
-	"zcip=no\0"						\
-	"netboot=yes\0"						\
-	"mvtest=Ff\0"						\
-	"tried_bootfromflash=no\0"				\
-	"tried_bootfromnet=no\0"				\
-	"use_dhcp=yes\0"					\
-	"gev_start=yes\0"					\
-	"mvbcdma_debug=0\0"					\
-	"mvbcia_debug=0\0"					\
-	"propdev_debug=0\0"					\
-	"gevss_debug=0\0"					\
-	"watchdog=1\0"						\
-	"sensor_cnt=1\0"					\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_ADDR		0xFFFE0000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_E1000
-#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
-#undef CONFIG_MPC5xxx_FEC
-#undef CONFIG_PHY_ADDR
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 	0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA	1
-#define CONFIG_FPGA_CYCLON2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
deleted file mode 100644
index 1ee4d7cc33..0000000000
--- a/include/configs/MVBLM7.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright (C) Matrix Vision GmbH 2008
- *
- * Matrix Vision mvBlueLYNX-M7 configuration file
- * based on Freescale's MPC8349ITX.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300	1
-#define CONFIG_MPC834x	1
-#define CONFIG_MPC8343	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_IMMR		0xE0000000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_TSEC_ENET
-#define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI
-#define MVBLM7_MMC_CS   0x04000000
-#define CONFIG_MISC_INIT_R
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	100000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	100000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/*
- * DDR Setup
- */
-#undef	CONFIG_SPD_EEPROM
-
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0	1
-#define CONFIG_SYS_MEMTEST_START	(60<<20)
-#define CONFIG_SYS_MEMTEST_END		(70<<20)
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_DDRCDR		(DDRCDR_PZ_HIZ \
-					| DDRCDR_NZ_HIZ \
-					| DDRCDR_Q_DRN)
-					/* 0x22000001 */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_SIZE		512
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
-
-#define CONFIG_SYS_DDR_TIMING_0		0x00260802
-#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
-#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_INTERVAL		0x02000100
-
-#define CONFIG_SYS_DDR_MODE		0x04040242
-#define CONFIG_SYS_DDR_MODE2		0x00800000
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-#define CONFIG_SYS_FLASH_SIZE		8
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16 \
-				| BR_MS_GPCM \
-				| BR_V)
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#undef	CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-
-/*
- * Local Bus LCRR and LBCR regs
- *  LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE		ttyS0
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-#define MV_DTB_NAME	"mvblm7.dtb"
-
-/*
- * PCI
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCI1_MMIO_BASE	\
-			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000
-
-#define CONFIG_NET_RETRY_COUNT	3
-
-#define CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN	66666667
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-/* TSEC */
-#define CONFIG_GMII
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define	CONFIG_SYS_VSC8601_SKEW_TX	3
-#define	CONFIG_SYS_VSC8601_SKEW_RX	3
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_FEC1_PHY_NORXERR
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define TSEC1_PHY_ADDR		0x10
-#define TSEC1_PHYIDX		0
-#define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define CONFIG_FEC2_PHY_NORXERR
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-#define TSEC2_PHY_ADDR		0x11
-#define TSEC2_PHYIDX		0
-#define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/* USB */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * Environment
- */
-#undef  CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0xFF800000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_USB
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR	0x200000
-
-#define CONFIG_SYS_PROMPT	"mvBL-M7> "
-#define CONFIG_SYS_CBSIZE	256
-
-#define CONFIG_SYS_PBSIZE	\
-			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW	0x0
-#define CONFIG_SYS_HRCW_HIGH	0x0
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-
-/* clocking */
-#define CONFIG_SYS_SCCR_ENCCM		0
-#define CONFIG_SYS_SCCR_USBMPHCM	0
-#define	CONFIG_SYS_SCCR_USBDRCM	2
-#define CONFIG_SYS_SCCR_TSEC1CM	1
-#define CONFIG_SYS_SCCR_TSEC2CM	1
-
-#define CONFIG_SYS_SICRH	0x1fef0003
-#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2	HID2_HBE
-#define CONFIG_HIGH_BATS	1
-
-/* DDR  */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI  */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* no PCI2 */
-#define CONFIG_SYS_IBAT3L	0
-#define CONFIG_SYS_IBAT3U	0
-#define CONFIG_SYS_IBAT4L	0
-#define CONFIG_SYS_IBAT4U	0
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT7L	0
-#define CONFIG_SYS_IBAT7U	0
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV		eth0
-
-/* Default path and filenames */
-#define CONFIG_BOOTDELAY		5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1000
-
-#define MV_CI			"mvBL-M7"
-#define MV_VCI			"mvBL-M7"
-#define MV_FPGA_DATA		0xfff40000
-#define MV_FPGA_SIZE		0
-#define MV_KERNEL_ADDR		0xff810000
-#define MV_INITRD_ADDR		0xffb00000
-#define MV_SCRIPT_ADDR		0xff804000
-#define MV_SCRIPT_ADDR2		0xff806000
-#define MV_DTB_ADDR		0xff808000
-#define MV_INITRD_LENGTH	0x00400000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-
-#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; "		\
-					"then source ${script_addr}; "	\
-					"else source ${script_addr2}; "	\
-				"fi;"
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"		\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
-	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
-	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" MV_CI "\0"				\
-	"dhcp_vendor-class-identifier=" MV_VCI "\0"		\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.90.10\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
-	"zcip=no\0"						\
-	"netboot=yes\0"						\
-	"mvtest=Ff\0"						\
-	"tried_bootfromflash=no\0"				\
-	"tried_bootfromnet=no\0"				\
-	"bootfile=mvblm72625.boot\0"				\
-	"use_dhcp=yes\0"					\
-	"gev_start=yes\0"					\
-	"mvbcdma_debug=0\0"					\
-	"mvbcia_debug=0\0"					\
-	"propdev_debug=0\0"					\
-	"gevss_debug=0\0"					\
-	"watchdog=0\0"						\
-	"usb_dr_mode=host\0"					\
-	"sensor_cnt=2\0"					\
-	""
-
-#define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
deleted file mode 100644
index 27f730d84b..0000000000
--- a/include/configs/MVSMR.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2010
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-#define CONFIG_SYS_LDSCRIPT	"board/matrix_vision/mvsmr/u-boot.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
-						230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvSMR
-#define MV_VCI			mvSMR
-#define MV_FPGA_DATA		0xff840000
-#define MV_FPGA_SIZE		0x1ff88
-#define MV_KERNEL_ADDR		0xfff00000
-#define MV_SCRIPT_ADDR		0xff806000
-#define MV_INITRD_ADDR		0xff880000
-#define MV_INITRD_LENGTH	0x00240000
-#define MV_SCRATCH_ADDR		0xffcc0000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_INITRD_ADDR_RAM	0x00400000
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
-					" allocate=6M"
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=no\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.0.101\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvsmr-rfs\0"			\
-	"zcip=yes\0"						\
-	"netboot=no\0"						\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-#define	CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-
-/* used by linker script to wrap code around */
-#define CONFIG_SCRIPT_OFFSET	0x6000
-#define CONFIG_SCRIPT_SECT_SIZE	0x2000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 		0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX	1
-#define CONFIG_FPGA_SPARTAN2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index d823b0f3cc..3ca204e1e2 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Serial Console Configuration */
 #define	CONFIG_5xx_CONS_SCI1
 #undef	CONFIG_5xx_CONS_SCI2
@@ -96,6 +98,7 @@
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /***********************************************************************
  * Last Stage Init
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index a6f505aaa9..9a1b2acac3 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /***********************************************************
  * Clock
  ***********************************************************/
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index d40185e1e2..a97f5faae4 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -28,6 +28,8 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* input clock of PLL (VCMA9 has 12MHz input clock) */
@@ -214,7 +216,6 @@
 
 /* File system */
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e2f7ead9bc..476430ddd0 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -223,6 +223,7 @@
 /* Bootcount using the RTC block */
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
 
 /* USB gadget RNDIS */
 #define CONFIG_SPL_MUSB_NEW_SUPPORT
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 43077cf851..f9ee40fa7e 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -9,109 +9,19 @@
 #ifndef __CONFIG_ARNDALE_H
 #define __CONFIG_ARNDALE_H
 
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
-#define CONFIG_S5P			/* S5P Family */
-#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
-#define CONFIG_EXYNOS5250
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-
-/* Allow tracing to be enabled */
-#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR		0x50000000
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x43E00000
-
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP			0x00000BAD
-#define S5P_CHECK_DIDLE			0xBAD00000
-#define S5P_CHECK_LPA			0xABAD0000
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET			0x800
-#define INFORM1_OFFSET			0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
-
-/* select serial console configuration */
-#define CONFIG_BAUDRATE			115200
-#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
-#define CONFIG_SILENT_CONSOLE
-
-/* Console configuration */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define EXYNOS_DEVICE_SETTINGS \
-		"stdin=serial\0" \
-		"stdout=serial\0" \
-		"stderr=serial\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	EXYNOS_DEVICE_SETTINGS
+#include "exynos5250-common.h"
 
 /* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
 #define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_BOUNCE_BUFFER
-
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* PWM */
-#define CONFIG_PWM
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Command definition*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_HASH
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
 #define CONFIG_USB_HOST_ETHER
@@ -119,106 +29,23 @@
 
 /* MMC SPL */
 #define CONFIG_EXYNOS_SPL
-#define COPY_BL2_FNPTR_ADDR	0x02020030
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
-/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
-#define CONFIG_SPL_TEXT_BASE	0x02023400
-#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
-
-#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_PROMPT		"ARNDALE # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_RD_LVL
 
 #define CONFIG_NR_DRAM_BANKS	8
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
 
-#define CONFIG_SYS_MONITOR_BASE	0x00000000
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for ARNDALE"
 
-#define CONFIG_SYS_MMC_ENV_DEV		0
-
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef	CONFIG_SECURE_BL1_ONLY
-#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
-#else
-#define	CONFIG_SEC_FW_SIZE		0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE	(512)
-#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
-#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
-
-#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
 #define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
 
-/* U-boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
-#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
-
 #define CONFIG_IRAM_STACK	0x02050000
 
 #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
 
-/* I2C */
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
-#define CONFIG_I2C_EDID
-
 /* PMIC */
 #define CONFIG_PMIC
 #define CONFIG_POWER_I2C
@@ -227,26 +54,6 @@
 
 #define CONFIG_PREBOOT
 
-/* Ethernet Controllor Driver */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE		0x5000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_ENV_SROM_BANK		1
-#endif /*CONFIG_CMD_NET*/
-
-/* Enable PXE Support */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#endif
-
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
-/* Enable Time Command */
-#define CONFIG_CMD_TIME
-
 #define CONFIG_S5P_PA_SYSRAM	0x02020000
 #define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 48c12ea880..b666d9494d 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -48,6 +48,8 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Hardware drivers
  */
diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
deleted file mode 100644
index 8bd71c6a15..0000000000
--- a/include/configs/bluestone.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * bluestone.h - configuration for Bluestone (APM821XX)
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_APM821XX		1	/* APM821XX series    */
-#define CONFIG_HOSTNAME		bluestone
-
-#define CONFIG_440		1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-#define CONFIG_SYS_CLK_FREQ	50000000
-
-#define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CONFIG_BOARD_EARLY_INIT_F	1       /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R		1       /* Call misc_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* EBC stuff */
-/* later mapped to this addr */
-#define CONFIG_SYS_FLASH_BASE		0xFFF00000
-#define CONFIG_SYS_FLASH_SIZE		(4 << 20)	/* 1MB usable */
-
-/* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000
-#define CONFIG_SYS_OCM_BASE		0xE3000000 /* OCM: 32k             */
-#define CONFIG_SYS_SRAM_BASE		0xE8000000 /* SRAM: 256k           */
-#define CONFIG_SYS_AHB_BASE		0xE2000000 /* internal AHB peripherals*/
-
-#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM    */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI	/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* max number of sectors on one chip    */
-#define CONFIG_SYS_MAX_FLASH_SECT	80
-/* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-/* Timeout for Flash Write (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-/* use buffered writes (20x faster)     */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector  */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector   */
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* SDRAM */
-#define CONFIG_SPD_EEPROM	1       /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS	{0x53, 0x51}	/* SPD i2c spd addresses */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-#define CONFIG_DDR_ECC		1	/* with ECC support             */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* Data sheet */
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_NONE_RGMII
-#define CONFIG_HAS_ETH0
-/* PHY address, See schematics  */
-#define CONFIG_PHY_ADDR			0x1f
-/* reset phy upon startup       */
-#define CONFIG_PHY_RESET		1
-/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_GIGE			1
-#define CONFIG_PHY_DYNAMIC_ANEG		1
-
-/*
- * External Bus Controller (EBC) Setup
- **/
-#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_LOCK    |	\
-				 EBC_CFG_PTD_ENABLE   |	\
-				 EBC_CFG_RTC_2048PERCLK | \
-				 EBC_CFG_ATC_HI | \
-				 EBC_CFG_DTC_HI | \
-				 EBC_CFG_CTC_HI | \
-				 EBC_CFG_OEO_PREVIOUS)
-/* NOR Flash */
-#define CONFIG_SYS_EBC_PB0AP 	(EBC_BXAP_BME_DISABLED   | \
-				EBC_BXAP_TWT_ENCODE(64)  | \
-				EBC_BXAP_BCE_DISABLE    | \
-				EBC_BXAP_BCT_2TRANS     | \
-				EBC_BXAP_CSN_ENCODE(1)  | \
-				EBC_BXAP_OEN_ENCODE(2)  | \
-				EBC_BXAP_WBN_ENCODE(2)  | \
-				EBC_BXAP_WBF_ENCODE(2)  | \
-				EBC_BXAP_TH_ENCODE(7)   | \
-				EBC_BXAP_SOR_DELAYED    | \
-				EBC_BXAP_BEM_WRITEONLY  | \
-				EBC_BXAP_PEN_DISABLED)
-/* Peripheral Bank Configuration Register - EBC_BxCR */
-#define CONFIG_SYS_EBC_PB0CR	\
-			(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-			EBC_BXCR_BS_1MB                | \
-			EBC_BXCR_BU_RW                  | \
-			EBC_BXCR_BW_8BIT)
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 10d02b4e18..7cf241e31d 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -222,7 +222,6 @@
 #define CONFIG_MII
 #define CONFIG_ETHPRIME			"FEC0"
 #define CONFIG_ARP_TIMEOUT		200UL
-#define CONFIG_NETMASK			255.255.255.0
 #define CONFIG_NET_RETRY_COUNT		5
 
 /* USB */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 6171060e9c..eb1584d3cc 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -18,6 +18,8 @@
 
 #define MACH_TYPE_CORVUS               2066
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos-common.h
index 99472acd0c..371f32d840 100644
--- a/include/configs/exynos4-dt.h
+++ b/include/configs/exynos-common.h
@@ -1,109 +1,78 @@
 /*
- * Copyright (C) 2014 Samsung Electronics
+ * Copyright (C) 2013 Samsung Electronics
  *
- * Configuration settings for the SAMSUNG EXYNOS5 board.
+ * Common configuration settings for the SAMSUNG EXYNOS boards.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __EXYNOS_COMMON_H
+#define __EXYNOS_COMMON_H
 
 /* High Level Configuration Options */
 #define CONFIG_SAMSUNG			/* in a SAMSUNG core */
 #define CONFIG_S5P			/* S5P Family */
-#define CONFIG_EXYNOS4			/* which is in a Exynos4 Family */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
 
+#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Enable fdt support */
+#define CONFIG_OF_LIBFDT
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
+/* Keep L2 Cache Disabled */
+#define CONFIG_CMD_CACHE
 
-/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+/* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
+#define CONFIG_ENV_OVERWRITE
 
-#include <linux/sizes.h>
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
 
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
 #define CONFIG_S5P_SDHCI
 #define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
 #define CONFIG_DWMMC
 #define CONFIG_EXYNOS_DWMMC
 #define CONFIG_BOUNCE_BUFFER
-#define CONFIG_MMC_DEFAULT_DEV	0
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* PWM */
 #define CONFIG_PWM
 
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
 /* Command definition*/
 #include <config_cmd_default.h>
 
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_PMIC
-#define CONFIG_CMD_SETEXPR
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* FAT */
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* EXT4 */
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
 
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
@@ -111,6 +80,7 @@
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
@@ -118,22 +88,4 @@
 #define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
-
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
new file mode 100644
index 0000000000..89ba14e05d
--- /dev/null
+++ b/include/configs/exynos4-common.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS4_COMMON_H
+#define __CONFIG_EXYNOS4_COMMON_H
+
+#define CONFIG_EXYNOS4			/* Exynos4 Family */
+
+#include "exynos-common.h"
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_REVISION_TAG
+
+/* SD/MMC configuration */
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV	0
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+#endif	/* __CONFIG_EXYNOS4_COMMON_H */
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-common.h
index 1dc3002523..ba591e7c1e 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-common.h
@@ -6,22 +6,14 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
-#define CONFIG_S5P			/* S5P Family */
-#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_COMMON
-#define CONFIG_ARCH_EARLY_INIT_R
+#ifndef __CONFIG_EXYNOS5_COMMON_H
+#define __CONFIG_EXYNOS5_COMMON_H
+
+#define CONFIG_EXYNOS5			/* Exynos5 Family */
+
+#include "exynos-common.h"
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_EXYNOS_SPL
 
 /* Allow tracing to be enabled */
@@ -32,22 +24,11 @@
 #define CONFIG_TRACE_EARLY
 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_SHA_HW_ACCEL
 
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
 /* Power Down Modes */
 #define S5P_CHECK_SLEEP			0x00000BAD
 #define S5P_CHECK_DIDLE			0xBAD00000
@@ -59,66 +40,26 @@
 #define INFORM2_OFFSET			0x808
 #define INFORM3_OFFSET			0x80c
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
-
 /* select serial console configuration */
 #define CONFIG_BAUDRATE			115200
 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
 #define CONFIG_SILENT_CONSOLE
-
-/* Enable keyboard */
-#define CONFIG_CROS_EC		/* CROS_EC protocol */
-#define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
-#define CONFIG_CROS_EC_I2C		/* Support CROS_EC over I2C */
-#define CONFIG_CROS_EC_KEYB	/* CROS_EC keyboard input */
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_KEYBOARD
-
-/* Console configuration */
-#define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
 #define EXYNOS_DEVICE_SETTINGS \
-		"stdin=serial,cros-ec-keyb\0" \
-		"stdout=serial,lcd\0" \
-		"stderr=serial,lcd\0"
+		"stdin=serial\0" \
+		"stdout=serial\0" \
+		"stderr=serial\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	EXYNOS_DEVICE_SETTINGS
 
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_BOUNCE_BUFFER
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* PWM */
-#define CONFIG_PWM
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
-
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_HASH
 
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 /* Thermal Management Unit */
 #define CONFIG_EXYNOS_TMU
 #define CONFIG_CMD_DTT
@@ -133,6 +74,7 @@
 
 /* MMC SPL */
 #define COPY_BL2_FNPTR_ADDR	0x02020030
+#define CONFIG_SUPPORT_EMMC_BOOT
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
@@ -140,15 +82,7 @@
 /* specific .lds file */
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
@@ -175,10 +109,6 @@
 
 #define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
-
 #define CONFIG_SYS_MMC_ENV_DEV		0
 
 #define CONFIG_SECURE_BL1_ONLY
@@ -199,23 +129,13 @@
 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
 
-/* Store environment at the end of a 4 MB SPI flash */
-#define FLASH_SIZE		(0x4 << 20)
-#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
-
 /* U-boot copy size from boot Media to DRAM.*/
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 
-#define CONFIG_SPI_BOOTING
 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_SYS_I2C
@@ -227,10 +147,6 @@
 #define CONFIG_I2C_EDID
 
 /* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-#define CONFIG_ENV_SPI_BASE	0x12D30000
-
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_EXYNOS_SPI
 #define CONFIG_CMD_SF
@@ -250,11 +166,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	50000000
 #endif
 
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_TPS65090
-
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
@@ -269,9 +180,6 @@
 #define CONFIG_MENU
 #endif
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
 /* SHA hashing */
 #define CONFIG_CMD_HASH
 #define CONFIG_HASH_VERIFY
@@ -291,4 +199,8 @@
 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
 
-#endif	/* __CONFIG_H */
+/* Enable FIT support and comparison */
+#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
+
+#endif	/* __CONFIG_EXYNOS5_COMMON_H */
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
new file mode 100644
index 0000000000..66547fa34e
--- /dev/null
+++ b/include/configs/exynos5-dt-common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * Configuration settings for generic Exynos 5 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
+#define __CONFIG_EXYNOS5_DT_COMMON_H
+
+#include "exynos5-common.h"
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65090
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC		/* CROS_EC protocol */
+#define CONFIG_CROS_EC_KEYB	/* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#undef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,lcd\0" \
+		"stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS
+
+#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-common.h
index c24984bd2b..713614f3ad 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-common.h
@@ -10,7 +10,7 @@
 #ifndef __CONFIG_5250_H
 #define __CONFIG_5250_H
 
-#include <configs/exynos5-dt.h>
+#include <configs/exynos5-common.h>
 #define CONFIG_EXYNOS5250
 
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
@@ -24,8 +24,6 @@
 
 /* USB */
 #define CONFIG_CMD_USB
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_EXYNOS
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
 
@@ -33,9 +31,6 @@
 
 #define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
 
-#define CONFIG_SYS_PROMPT		"SMDK5250 # "
-#define CONFIG_IDENT_STRING		" for SMDK5250"
-
 #define CONFIG_IRAM_STACK	0x02050000
 
 #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420-common.h
index d2a95567a8..b0f940cd16 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420-common.h
@@ -9,7 +9,18 @@
 #ifndef __CONFIG_EXYNOS5420_H
 #define __CONFIG_EXYNOS5420_H
 
-#define CONFIG_EXYNOS5420		/* which is in a Exynos5 Family */
+#define CONFIG_EXYNOS5420
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+#define FLASH_SIZE		(0x4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
+
+#include <configs/exynos5-common.h>
+
+#define CONFIG_ARCH_EARLY_INIT_R
 
 #define MACH_TYPE_SMDK5420	8002
 #define CONFIG_MACH_TYPE	MACH_TYPE_SMDK5420
@@ -31,14 +42,12 @@
 
 #define CONFIG_MAX_I2C_NUM	11
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
-
 #define CONFIG_BOARD_REV_GPIO_COUNT	2
 
 #define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
 
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+
 /*
  * Put the initial stack pointer 1KB below this to allow room for the
  * SPL marker. This value is arbitrary, but gd_t is placed starting here.
@@ -49,4 +58,7 @@
 #define CONFIG_NR_DRAM_BANKS	7
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
 
+/* Miscellaneous configurable options */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
 #endif	/* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 21667d1f78..e015e9091b 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -89,6 +89,7 @@
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE
 #define CONFIG_CONS_SCIF0
+#define CONFIG_SCIF_USE_EXT_CLK
 #undef	CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 6e9d67d690..699135fc0e 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -90,6 +90,7 @@
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE
 #define CONFIG_CONS_SCIF0
+#define CONFIG_SCIF_USE_EXT_CLK
 #undef	CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
@@ -167,7 +168,7 @@
 #define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
 #define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
 #define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
-#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_MP_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600 /* External Clock */
 
 #define CONFIG_SYS_TMU_CLK_DIV	4
 
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index bf5c1a1298..a14bfe3a85 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -8,6 +8,8 @@
 #ifndef _CONFIG_LSXL_H
 #define _CONFIG_LSXL_H
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Version number information
  */
@@ -157,7 +159,7 @@
 	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; "	\
 		"setenv ncip; setenv gatewayip; setenv ethact; "	\
 		"setenv bootfile; setenv dnsip; "			\
-		"setenv bootsource hdd; run ser\0"			\
+		"setenv bootsource legacy; run ser\0"			\
 	"restore_env=run standard_env; saveenv; reset\0"		\
 	"ser=setenv stdin serial; setenv stdout serial; "		\
 		"setenv stderr serial\0"				\
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index fccd29dc26..efe770b81b 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -32,6 +32,7 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_I2C
@@ -236,7 +237,7 @@
 	"addargs=run addcons addmtd addmisc\0"				\
 	"mmcload="							\
 		"mmc rescan ; "						\
-		"ext4load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"	\
+		"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"		\
 	"ubiload="							\
 		"ubi part UBI ; ubifsmount ubi0:rootfs ; "		\
 		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
@@ -279,10 +280,12 @@
 		"bootm ${kernel_addr_r}\0"				\
 	"try_bootscript="						\
 		"mmc rescan;"						\
-		"if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};"	\
-		"then;"							\
-			"\techo Running bootscript...;"			\
-			"\tsource ${kernel_addr_r};"			\
+		"if test -e mmc 0:2 ${bootscript} ; then "		\
+		"if load mmc 0:2 ${kernel_addr_r} ${bootscript};"	\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
 		"fi\0"
 
 /* The rest of the configuration is shared */
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index df6a226109..c133ba9d03 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -38,6 +38,7 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
@@ -305,7 +306,7 @@
 	"addargs=run addcons addmtd addmisc\0"				\
 	"mmcload="							\
 		"mmc rescan ; "						\
-		"ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"	\
+		"load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"		\
 	"ubiload="							\
 		"ubi part UBI ; ubifsmount ubi0:rootfs ; "		\
 		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
@@ -348,10 +349,12 @@
 		"bootm ${kernel_addr_r}\0"				\
 	"try_bootscript="						\
 		"mmc rescan;"						\
-		"if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};"	\
-		"then;"							\
-			"\techo Running bootscript...;"			\
-			"\tsource ${kernel_addr_r};"			\
+		"if test -e mmc 0:1 ${bootscript} ; then "		\
+		"if load mmc 0:1 ${kernel_addr_r} ${bootscript};"	\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
 		"fi\0"
 
 #endif	/* __M53EVK_CONFIG_H__ */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index d464ad964b..c02e29be9a 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -14,6 +14,7 @@
 #define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 #define CONFIG_MXC_GPIO
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SYS_TIMER_RATE		32768
 #define CONFIG_SYS_TIMER_COUNTER	\
@@ -100,7 +101,7 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	IMX_MMC_SDHC1_BASE
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
 
 /* PMIC Configs */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index b389475ebe..d6e8ec4e13 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -26,6 +26,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_OF_LIBFDT
 
@@ -69,7 +70,7 @@
  * MMC Configs
  * */
 #define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR
 #define CONFIG_SYS_FSL_ESDHC_NUM	2
 
 #define CONFIG_MMC
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 35c0a85080..6e01fa0435 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -10,7 +10,6 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 
 #include "mx6_common.h"
 
@@ -37,7 +36,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
 #define CONFIG_MMC
@@ -69,18 +68,22 @@
 
 #define CONFIG_BOOTDELAY		3
 
-#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_LOADADDR			0x12000000
 #define CONFIG_SYS_TEXT_BASE		0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc3\0" \
+	"fdt_file=imx6q-arm2.dtb\0" \
+	"fdt_addr=0x18000000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
 	"mmcdev=1\0" \
-	"mmcpart=2\0" \
-	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
@@ -88,15 +91,46 @@
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"bootz\0" \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs; " \
-		"dhcp ${image}; bootz\0" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev};" \
@@ -134,7 +168,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			(2u * 1024 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 4208ba1563..fddedf1a8e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -40,7 +40,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index b92d9443d4..e02ea18a64 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -159,7 +159,7 @@
 /* MMC Configuration */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
@@ -204,8 +204,8 @@
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
-#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 0)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 1)
 #endif
 
 /* FLASH and environment organization */
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 39d5bb34bb..6d379ed7ad 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -32,6 +32,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
+#define CONFIG_CMD_GPIO
 #define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
 #define CONFIG_USB_GADGET_DUALSPEED
@@ -63,6 +64,7 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_I2C_EDID
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -75,6 +77,8 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
@@ -122,6 +126,8 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 
 /* Miscellaneous commands */
 #define CONFIG_CMD_BMODE
@@ -137,7 +143,6 @@
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_CONSOLE_MUX
@@ -173,7 +178,14 @@
 #define CONFIG_DRIVE_MMC
 #endif
 
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+#ifdef CONFIG_USB_STORAGE
+#define CONFIG_DRIVE_USB "usb "
+#else
+#define CONFIG_DRIVE_USB
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB
+#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
 
 #if defined(CONFIG_SABRELITE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -186,7 +198,7 @@
 	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
+	"mmcdevs=0 1\0" \
 	"mmcpart=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
@@ -238,47 +250,71 @@
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
-	   "mmc dev ${mmcdev}; if mmc rescan; then " \
-		   "if run loadbootscript; then " \
-			   "run bootscript; " \
-		   "else " \
-			   "if run loaduimage; then " \
-				   "run mmcboot; " \
-			   "else run netboot; " \
-			   "fi; " \
-		   "fi; " \
-	   "else run netboot; fi"
+	"for mmcdev in ${mmcdevs}; do " \
+		"mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loaduimage; then " \
+					"run mmcboot; " \
+				"fi; " \
+			"fi; " \
+		"fi; " \
+	"done; " \
+	"run netboot; "
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
+	"umsdevs=" CONFIG_UMSDEVS "\0" \
 	"console=ttymxc1\0" \
 	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
 		"sf erase 0xc0000 0x2000 && " \
 		"echo restored environment to factory default ; fi\0" \
-	"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
+	"bootcmd=for dtype in ${bootdevs}" \
 		"; do " \
+			"if itest.s \"xusb\" == \"x${dtype}\" ; then " \
+				"usb start ;" \
+			"fi; " \
 			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-				"for fs in fat ext2 ; do " \
-					"${fs}load " \
-						"${dtype} ${disk}:1 " \
-						"10008000 " \
-						"/6x_bootscript" \
-						"&& source 10008000 ; " \
-				"done ; " \
+				"load " \
+					"${dtype} ${disk}:1 " \
+					"10008000 " \
+					"/6x_bootscript" \
+					"&& source 10008000 ; " \
 			"done ; " \
 		"done; " \
 		"setenv stdout serial,vga ; " \
 		"echo ; echo 6x_bootscript not found ; " \
 		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
 		"echo details at http://boundarydevices.com/6q_bootscript ; " \
-		"setenv stdout serial\0" \
-	"upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
+		"setenv stdout serial;" \
+		"setenv stdin serial,usbkbd;" \
+		"for dtype in ${umsdevs} ; do " \
+			"if itest.s sata == ${dtype}; then " \
+				"initcmd='sata init' ;" \
+			"else " \
+				"initcmd='mmc rescan' ;" \
+			"fi; " \
+			"for disk in 0 1 ; do " \
+				"if $initcmd && $dtype dev $disk ; then " \
+					"setenv stdout serial,vga; " \
+					"echo expose ${dtype} ${disk} " \
+						"over USB; " \
+					"ums 0 $dtype $disk ;" \
+				"fi; " \
+		"	done; " \
+		"done ;" \
+		"setenv stdout serial,vga; " \
+		"echo no block devices found;" \
+		"\0" \
+	"initrd_high=0xffffffff\0" \
+	"upgradeu=for dtype in ${bootdevs}" \
 		"; do " \
 		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-		     "for fs in fat ext2 ; do " \
-				"${fs}load ${dtype} ${disk}:1 10008000 " \
-					"/6x_upgrade " \
-					"&& source 10008000 ; " \
-			"done ; " \
+			"load ${dtype} ${disk}:1 10008000 " \
+				"/6x_upgrade " \
+				"&& source 10008000 ; " \
 		"done ; " \
 	"done\0" \
 
@@ -292,7 +328,7 @@
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_MAXARGS	       48
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
@@ -349,6 +385,7 @@
 #define CONFIG_CMD_BMP
 
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_ALT_MEMTEST
 
 #define CONFIG_CMD_BOOTZ
@@ -365,4 +402,22 @@
 #define CONFIG_PCIE_IMX
 #endif
 
+#define CONFIG_CMD_ELF
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+/* Netchip IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Boundary"
+
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE   0x07000000
+
 #endif	       /* __CONFIG_H */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index b616ac2fbd..b928af839e 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -12,7 +12,7 @@
 #ifndef __CONFIG_ODROID_U3_H
 #define __CONFIG_ODROID_U3_H
 
-#include <configs/exynos4-dt.h>
+#include <configs/exynos4-common.h>
 
 #define CONFIG_SYS_PROMPT	"Odroid # "	/* Monitor Command Prompt */
 
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_TEXT_BASE		0x43e00000
 
 #include <linux/sizes.h>
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL1
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index e66f30655d..b17e495f5f 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -151,7 +151,7 @@
 			"run mmcboot;" \
 		"fi;" \
 		"if run loadzimage; then " \
-			"if test $fdtfile; then " \
+			"if test -z \"${fdtfile}\"; then " \
 				"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
 			"fi;" \
 			"if run loadfdt; then " \
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 7e2ecd53f5..e8dc462f14 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -72,7 +72,6 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_CMD_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
diff --git a/include/configs/origen.h b/include/configs/origen.h
index fb1536c62c..da9d6a1ee1 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -9,7 +9,7 @@
 #ifndef __CONFIG_ORIGEN_H
 #define __CONFIG_ORIGEN_H
 
-#include <configs/exynos4-dt.h>
+#include <configs/exynos4-common.h>
 
 #define CONFIG_SYS_PROMPT		"ORIGEN # "
 
@@ -35,9 +35,6 @@
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
new file mode 100644
index 0000000000..071880fe75
--- /dev/null
+++ b/include/configs/ot1200.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+/* FUSE Configs */
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* UART Configs */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+
+/* SF Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  2
+#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(1, 3)<<8))
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* IO expander */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED            100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_IMXOTP
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX                0x7F
+#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
+#define IMX_OTPWRITE_ENABLED
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0x5
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY               2
+
+#define CONFIG_PREBOOT                 ""
+
+#define CONFIG_LOADADDR                0x12000000
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE              1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                 (64 * 1024)	/* 64 kb */
+#define CONFIG_ENV_OFFSET               (1024 * 1024)
+/* M25P16 has an erase size of 64 KiB */
+#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
+#define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* FS Configs */
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTFILE
+
+#endif         /* __CONFIG_H */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 987cef504c..ab8ac60df2 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -9,10 +9,16 @@
 #ifndef __CONFIG_PEACH_PIT_H
 #define __CONFIG_PEACH_PIT_H
 
-#include <configs/exynos5-dt.h>
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+#define FLASH_SIZE		(0x4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
 
-#include <configs/exynos5420.h>
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
 
+#define CONFIG_BOARD_COMMON
 
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
@@ -30,4 +36,10 @@
 #define LCD_BPP			LCD_COLOR16
 #endif
 
+#define CONFIG_POWER_TPS65090_EC
+#define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
+
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
 #endif	/* __CONFIG_PEACH_PIT_H */
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
new file mode 100644
index 0000000000..a28d7b579a
--- /dev/null
+++ b/include/configs/ph1_ld4.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    36864000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1600
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
new file mode 100644
index 0000000000..b79967f7da
--- /dev/null
+++ b/include/configs/ph1_pro4.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    73728000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+#define CONFIG_DDR_FREQ 1600
+
+#define CONFIG_UNIPHIER_SMP
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x20000000
+#define CONFIG_SDRAM1_BASE	0xa0000000
+#define CONFIG_SDRAM1_SIZE	0x20000000
+
+#define CONFIG_SPL_TEXT_BASE 0x100000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
new file mode 100644
index 0000000000..9d391f1d74
--- /dev/null
+++ b/include/configs/ph1_sld8.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    80000000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1333
+
+/* #define CONFIG_DDR_STANDARD */
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index a51215d9ae..0c6e9c7878 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -39,8 +39,9 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 
-/* Size of malloc() pool.*/
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 80 * SZ_1M)
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
 
 /*
  * select serial console configuration
@@ -53,6 +54,7 @@
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_S5P_SDHCI
+#define SDHCI_MAX_HOSTS		4
 
 /* PWM */
 #define CONFIG_PWM			1
@@ -106,7 +108,6 @@
 				",12m(modem)"\
 				",60m(qboot)\0"
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* partitions definitions */
@@ -283,4 +284,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_GADGET_MASS_STORAGE
 
+#define CONFIG_OF_LIBFDT
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 082d51c52b..27f3d0af47 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -10,7 +10,7 @@
 #ifndef __CONFIG_UNIVERSAL_H
 #define __CONFIG_UNIVERSAL_H
 
-#include <configs/exynos4-dt.h>
+#include <configs/exynos4-common.h>
 
 #define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
 
@@ -27,9 +27,6 @@
 
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 4747adfeb0..71be823899 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -1,5 +1,6 @@
 /*
- * (C) Copyright 2009
+ * (C) Copyright 2009-2014
+ * Gerald Kerma <dreagle@doukki.net>
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  *
@@ -23,12 +24,26 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+
+/*
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
@@ -54,8 +69,8 @@
  * it has to be rounded to sector size
  */
 #define CONFIG_ENV_SIZE			0x20000	/* 128k */
-#define CONFIG_ENV_ADDR			0x60000
-#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+#define CONFIG_ENV_ADDR			0x80000
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
 
 /*
  * Default environment variables
@@ -64,8 +79,10 @@
 	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
 	"${x_bootcmd_usb}; bootm 0x6400000;"
 
-#define CONFIG_MTDPARTS		"orion_nand:512k(uboot),"	\
-	"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+#define CONFIG_MTDPARTS		\
+	"mtdparts=orion_nand:512K(uboot),"				\
+	"512K(env),1M(script),6M(kernel),"				\
+	"12M(ramdisk),4M(spare),-(rootfs)"
 
 #define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
 	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
@@ -73,6 +90,11 @@
 	"x_bootcmd_usb=usb start\0" \
 	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
 
+#define MTDIDS_DEFAULT	"nand0=orion_nand"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts="CONFIG_MTDPARTS
+
 /*
  * Ethernet Driver configuration
  */
@@ -92,9 +114,23 @@
 #endif /* CONFIG_CMD_MMC */
 
 /*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/*
  * File system
  */
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_UBI
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 61170941c1..83953728dd 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -9,11 +9,26 @@
 #ifndef __CONFIG_SMDK_H
 #define __CONFIG_SMDK_H
 
-#include <configs/exynos5250-dt.h>
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+#define FLASH_SIZE		(0x4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
 
+#include <configs/exynos5250-common.h>
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
+
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
+#define CONFIG_SYS_PROMPT		"SMDK5250 # "
+#define CONFIG_IDENT_STRING		" for SMDK5250"
+
+/* Miscellaneous configurable options */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
 #endif	/* __CONFIG_SMDK_H */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 36a156f7a7..fd2d482e4a 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -9,9 +9,9 @@
 #ifndef __CONFIG_SMDK5420_H
 #define __CONFIG_SMDK5420_H
 
-#include <configs/exynos5-dt.h>
+#include <configs/exynos5420-common.h>
 
-#include <configs/exynos5420.h>
+#define CONFIG_BOARD_COMMON
 
 #define CONFIG_SMDK5420			/* which is in a SMDK5420 */
 
@@ -21,5 +21,6 @@
 
 #define CONFIG_SYS_PROMPT	"SMDK5420 # "
 #define CONFIG_IDENT_STRING	" for SMDK5420"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
 #endif	/* __CONFIG_SMDK5420_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index c9a2e1568f..22835ffd64 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -47,6 +47,10 @@
  * 1MB = 0x100000, 0x100000 = 1024 * 1024
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* Small malloc pool before relocation */
+#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
+
 /*
  * select serial console configuration
  */
@@ -217,4 +221,6 @@
 #define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for Ethernet*/
 #endif /* CONFIG_CMD_NET */
 
+#define CONFIG_OF_LIBFDT
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 048c178692..a2469eb60c 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -9,71 +9,42 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include "exynos4-common.h"
+
+#undef CONFIG_BOARD_COMMON
+#undef CONFIG_USB_GADGET
+#undef CONFIG_USB_GADGET_S3C_UDC_OTG
+#undef CONFIG_CMD_USB_MASS_STORAGE
+#undef CONFIG_REVISION_TAG
+#undef CONFIG_CMD_THOR_DOWNLOAD
+#undef CONFIG_CMD_DFU
+
 /* High Level Configuration Options */
-#define CONFIG_SAMSUNG			1	/* in a SAMSUNG core */
-#define CONFIG_S5P			1	/* S5P Family */
-#define CONFIG_EXYNOS4				/* EXYNOS4 Family */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
 #define CONFIG_SMDKV310			1	/* working with SMDKV310*/
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
 /* Mach Type */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
 
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_TEXT_BASE		0x43E00000
 
-/* input clock of PLL: SMDKV310 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
 /* Handling Sleep Mode*/
 #define S5P_CHECK_SLEEP			0x00000BAD
 #define S5P_CHECK_DIDLE			0xBAD00000
 #define S5P_CHECK_LPA			0xABAD0000
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL1			1	/* use SERIAL 1 */
-#define CONFIG_BAUDRATE			115200
 #define EXYNOS4_DEFAULT_UART_OFFSET	0x010000
 
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM			1
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Command definition*/
-#include <config_cmd_default.h>
-
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* MMC SPL */
 #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -84,15 +55,8 @@
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_PROMPT		"SMDKV310 # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
@@ -111,8 +75,6 @@
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
 
 /* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH		1
-#undef	CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for SMDKC210/V310"
 
 #define CONFIG_CLK_1000_400_200
@@ -126,7 +88,6 @@
 #define RESERVE_BLOCK_SIZE		(512)
 #define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION		1
 
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
@@ -146,6 +107,4 @@
 #define CONFIG_ENV_SROM_BANK		1
 #endif /*CONFIG_CMD_NET*/
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
 #endif	/* __CONFIG_H */
diff --git a/include/configs/snow.h b/include/configs/snow.h
index fbaaa593cc..7eaa58697e 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -9,11 +9,28 @@
 #ifndef __CONFIG_SNOW_H
 #define __CONFIG_SNOW_H
 
-#include <configs/exynos5250-dt.h>
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+#define FLASH_SIZE		(0x4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
+#define CONFIG_SPI_BOOTING
 
+#include <configs/exynos5250-common.h>
+#include <configs/exynos5-dt-common.h>
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
+
+#define CONFIG_CROS_EC_I2C		/* Support CROS_EC over I2C */
+#define CONFIG_POWER_TPS65090_I2C
+
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
+#define CONFIG_SYS_PROMPT		"snow # "
+#define CONFIG_IDENT_STRING		" for snow"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
 #endif	/* __CONFIG_SNOW_H */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 8d54bf892d..60d7e20e83 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -53,7 +53,7 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-#define CONFIG_EMAC_BASE		SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS
 #define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
 #define CONFIG_EPHY0_PHY_ADDR		0
 
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 20d4cee011..aadf4cd2f8 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -24,6 +24,8 @@
 #define MACH_TYPE_TAURUS		2067
 #define MACH_TYPE_AXM			2068
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 43751e7938..b21ea2de5f 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -10,7 +10,7 @@
 #ifndef __CONFIG_TRATS_H
 #define __CONFIG_TRATS_H
 
-#include <configs/exynos4-dt.h>
+#include <configs/exynos4-common.h>
 
 #define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */
 
@@ -39,10 +39,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x63300000
 
-#include <linux/sizes.h>
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index e9a04f7af3..42481ab6e1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -11,7 +11,7 @@
 #ifndef __CONFIG_TRATS2_H
 #define __CONFIG_TRATS2_H
 
-#include <configs/exynos4-dt.h>
+#include <configs/exynos4-common.h>
 
 #define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
 
@@ -36,10 +36,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x43e00000
 
-#include <linux/sizes.h>
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
-
 /* select serial console configuration */
 #define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h
new file mode 100644
index 0000000000..18fe277cad
--- /dev/null
+++ b/include/configs/uniphier-common.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* U-boot - Common settings for UniPhier Family */
+
+#ifndef __CONFIG_UNIPHIER_COMMON_H__
+#define __CONFIG_UNIPHIER_COMMON_H__
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) &&	\
+				defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
+are defined. Select only one of them."
+#endif
+
+/*
+ * Support card address map
+ */
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x03f00000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00090000)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x08000000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00401630)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00200000)
+#endif
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
+#define CONFIG_SYS_NS16550_CLK		12288000
+#define CONFIG_SYS_NS16550_REG_SIZE	-2
+
+#define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
+#define CONFIG_SMC911X_32_BIT
+
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
+
+/*-----------------------------------------------------------------------
+ * MMU and Cache Setting
+ *----------------------------------------------------------------------*/
+
+/* Comment out the following to enable L1 cache */
+/* #define CONFIG_SYS_ICACHE_OFF */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/* Comment out the following to enable L2 cache */
+#define CONFIG_UNIPHIER_L2CACHE_ON
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP
+
+/* FLASH related */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * uncomment the following to disable FLASH related code.
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE		0
+#define CONFIG_SYS_FLASH_BASE		0
+
+/*
+ * flash_toggle does not work for out supoort card.
+ * We need to use flash_status_poll.
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x00000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x02000000}
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x04000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x04000000}
+#endif
+
+/* serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#endif
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
+ */
+/* #define CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE				0x2000
+#define CONFIG_ENV_OFFSET			0x0
+/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+
+/* Time clock 1MHz */
+#define CONFIG_SYS_TIMER_RATE			1000000
+
+/*
+ * By default, ARP timeout is 5 sec.
+ * The first ARP request does not seem to work.
+ * So we need to retry ARP request anyway.
+ * We want to shrink the interval until the second ARP request.
+ */
+#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND		/* NAND flash suppport */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE			1
+#define CONFIG_SYS_NAND_MAX_CHIPS			2
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_NAND_DENALI_ECC_SIZE			1024
+
+#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
+#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+
+#define CONFIG_BOOTDELAY			3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR		"d"
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_ETHADDR			00:21:83:24:00:00
+#define CONFIG_SERVERIP			192.168.11.1
+#define CONFIG_IPADDR			192.168.11.10
+#define CONFIG_GATEWAYIP		192.168.11.1
+#define CONFIG_NETMASK			255.255.255.0
+
+#define CONFIG_LOADADDR			0x84000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_BOOTFILE			"fit.itb"
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_BOOTCOMMAND		"run $bootmode"
+
+#define CONFIG_ROOTPATH			"/nfs/root/path"
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs $bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
+	"tftpboot; bootm;"
+
+#define CONFIG_BOOTARGS		" user_debug=0x1f init=/sbin/init"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"image_offset=0x00080000\0"		\
+	"image_size=0x00f00000\0"		\
+	"verify=n\0"				\
+	"autostart=yes\0"			\
+	"norboot=run add_default_bootargs;"				\
+		"bootm $image_offset\0"					\
+	"nandboot=run add_default_bootargs;"				\
+		"nand read $loadaddr $image_offset $image_size;"	\
+		"bootm\0"						\
+	"add_default_bootargs=setenv bootargs $bootargs"		\
+		" console=ttyS0,$baudrate\0"				\
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_HAVE_ARM_SECURE
+
+/* Memory Size & Mapping */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SDRAM0_BASE
+
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
+/* Thre is no memory hole */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
+#else
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE)
+#endif
+
+#define CONFIG_SYS_TEXT_BASE		0x84000000
+
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_BOARD_POSTCLK_INIT
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_SPL_MALLOC_START	(0x0ff00000)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(0x00004000)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0x0ff08000)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000
+
+#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 0342550412..6fd0b173eb 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -14,6 +14,7 @@
 
 #define CONFIG_VF610
 
+#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -44,6 +45,41 @@
 
 #undef CONFIG_CMD_IMLS
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+
+/* UBI */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT			"nand0=fsl_nfc"
+#define MTDPARTS_DEFAULT		"mtdparts=fsl_nfc:"		\
+					"128k(vf-bcb)ro,"		\
+					"1408k(u-boot)ro,"		\
+					"512k(u-boot-env),"		\
+					"4m(kernel),"			\
+					"512k(fdt),"		\
+					"-(rootfs)"
+#endif
+
 #define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
@@ -218,11 +254,19 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#ifdef CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_SIZE			(8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
 
 #define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_SECT_SIZE		(64 * 2048)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x180000
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 7d96908f0e..9fb501a341 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -110,6 +110,11 @@
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
 #elif defined(CONFIG_MX6Q)
diff --git a/include/net.h b/include/net.h
index 735b0b9d26..18d279ebe7 100644
--- a/include/net.h
+++ b/include/net.h
@@ -3,7 +3,7 @@
  *
  *	Copyright 1994 - 2000 Neil Russell.
  *	(See License)
- *
+ *	SPDX-License-Identifier:	GPL-2.0
  *
  * History
  *	9/16/00	  bor  adapted to TQM823L/STK8xxL board, RARP/TFTP boot added