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authorTom Rini <trini@konsulko.com>2019-06-19 14:01:11 -0400
committerTom Rini <trini@konsulko.com>2019-06-19 14:01:11 -0400
commit63a458579135c498532e5b47987ed49d09353ce6 (patch)
treee398cb7057694ea5fda9e9ce86ddc561eb8a25e3 /include
parentc3f43185eeb9e600c6cc0e7721f52c749e14c666 (diff)
parentda70f766dd19d3645f32ed51a64b137bac7da423 (diff)
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls1012a_common.h1
-rw-r--r--include/configs/ls1028a_common.h4
-rw-r--r--include/configs/ls1046a_common.h13
-rw-r--r--include/configs/ls1046afrwy.h136
-rw-r--r--include/configs/ls1046ardb.h3
-rw-r--r--include/configs/ls2080aqds.h51
-rw-r--r--include/configs/ls2080ardb.h12
-rw-r--r--include/configs/lx2160a_common.h6
-rw-r--r--include/fm_eth.h12
9 files changed, 214 insertions, 24 deletions
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 5581cfd1c92..dd2a679b799 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -43,7 +43,6 @@
#define CONFIG_FSL_SPI_INTERFACE
#define CONFIG_SF_DATAFLASH
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define CONFIG_SPI_FLASH_SPANSION
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 0db86396e92..d3d787f14d7 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -197,4 +197,8 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
#endif /* __L1028A_COMMON_H */
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 34b4756ed83..59c43f1ae1e 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
+ * Copyright 2019 NXP
*/
#ifndef __LS1046A_COMMON_H
@@ -202,6 +203,15 @@
#include <config_distro_bootcmd.h>
#endif
+#if defined(CONFIG_TARGET_LS1046AFRWY)
+#define LS1046A_BOOT_SRC_AND_HDR\
+ "boot_scripts=ls1046afrwy_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
+#else
+#define LS1046A_BOOT_SRC_AND_HDR\
+ "boot_scripts=ls1046ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
+#endif
#ifndef SPL_NO_MISC
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -232,8 +242,7 @@
"console=ttyS0,115200\0" \
CONFIG_MTDPARTS_DEFAULT "\0" \
BOOTENV \
- "boot_scripts=ls1046ardb_boot.scr\0" \
- "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
+ LS1046A_BOOT_SRC_AND_HDR \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
new file mode 100644
index 00000000000..791bb8dc47f
--- /dev/null
+++ b/include/configs/ls1046afrwy.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1046AFRWY_H__
+#define __LS1046AFRWY_H__
+
+#include "ls1046a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_SYS_UBOOT_BASE 0x40100000
+
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define I2C_RETIMER_ADDR 0x18
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
+#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
+#define CONFIG_SYS_RTC_BUS_NUM 0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+
+/* FMan */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+
+#define QSGMII_PORT1_PHY_ADDR 0x1c
+#define QSGMII_PORT2_PHY_ADDR 0x1d
+#define QSGMII_PORT3_PHY_ADDR 0x1e
+#define QSGMII_PORT4_PHY_ADDR 0x1f
+
+#define FDT_SEQ_MACADDR_FROM_ENV
+
+#define CONFIG_ETHPRIME "FM1@DTSEC3"
+
+#endif
+
+/* QSPI device */
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE SZ_64M
+#define FSL_QSPI_FLASH_NUM 1
+#endif
+
+#undef CONFIG_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046AFRWY_H__ */
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 831767235e6..2d20f156835 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
+ * Copyright 2019 NXP
*/
#ifndef __LS1046ARDB_H__
@@ -162,6 +163,8 @@
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
#else
#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 0
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 74c7dc4f8ab..18f30b585c4 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017, 2019 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -368,9 +368,9 @@ unsigned long get_board_ddr_clk(void);
#else
#ifdef CONFIG_TFABOOT
#define SD_MC_INIT_CMD \
- "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
- "mmc read 0x80100000 0x7000 0x800;" \
- "fsl_mc start mc 0x80000000 0x80100000\0"
+ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
+ "mmc read 0x80e00000 0x7000 0x800;" \
+ "fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD \
"fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
@@ -378,8 +378,8 @@ unsigned long get_board_ddr_clk(void);
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"loadaddr_sd=0x90100000\0" \
- "kernel_addr=0x100000\0" \
- "kernel_addr_sd=0x800\0" \
+ "kernel_addr=0x581000000\0" \
+ "kernel_addr_sd=0x8000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
@@ -389,9 +389,23 @@ unsigned long get_board_ddr_clk(void);
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernel_size_sd=0x14000\0" \
- "mcinitcmd=fsl_mc start mc 0x580a00000" \
- " 0x580e00000 \0" \
- "mcmemsize=0x70000000 \0"
+ "load_addr=0xa0000000\0" \
+ "kernelheader_addr=0x580800000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernelheader_size=0x40000\0" \
+ "BOARD=ls2088aqds\0" \
+ "mcmemsize=0x70000000 \0" \
+ IFC_MC_INIT_CMD \
+ "nor_bootcmd=echo Trying load from nor..;" \
+ "cp.b $kernel_addr $load_addr " \
+ "$kernel_size ; env exists secureboot && " \
+ "cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ "bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "bootm $load_addr#$BOARD\0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
@@ -426,6 +440,25 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_SECURE_BOOT */
+#ifdef CONFIG_TFABOOT
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+ "&& esbc_validate $load_addr; " \
+ "env exists mcinitcmd && run mcinitcmd " \
+ "&& mmc read 0x80d00000 0x6800 0x800 " \
+ "&& fsl_mc lazyapply dpl 0x80d00000; " \
+ "run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+#define IFC_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x580780000; env exists mcinitcmd "\
+ "&& fsl_mc lazyapply dpl 0x580d00000;" \
+ "run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#endif
+
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB_10G
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 2e8a8bbdb74..bfb54be79b9 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017, 2019 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -342,14 +342,14 @@ unsigned long get_board_sys_clk(void);
"esbc_validate 0x20740000;" \
"fsl_mc start mc 0x20a00000 0x20e00000 \0"
#define SD_MC_INIT_CMD \
- "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
- "mmc read 0x80100000 0x7000 0x800;" \
+ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
+ "mmc read 0x80e00000 0x7000 0x800;" \
"env exists secureboot && " \
"mmc read 0x80700000 0x3800 0x10 && " \
"mmc read 0x80740000 0x3A00 0x10 && " \
"esbc_validate 0x80700000 && " \
"esbc_validate 0x80740000 ;" \
- "fsl_mc start mc 0x80000000 0x80100000\0"
+ "fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD \
"env exists secureboot && " \
"esbc_validate 0x580700000 && " \
@@ -528,8 +528,8 @@ unsigned long get_board_sys_clk(void);
"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
"&& esbc_validate $load_addr; " \
"env exists mcinitcmd && run mcinitcmd " \
- "&& mmc read 0x88000000 0x6800 0x800 " \
- "&& fsl_mc lazyapply dpl 0x88000000; " \
+ "&& mmc read 0x80d00000 0x6800 0x800 " \
+ "&& fsl_mc lazyapply dpl 0x80d00000; " \
"run distro_bootcmd;run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index eb0b1766aa7..711b434baff 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -246,12 +246,6 @@ unsigned long get_board_ddr_clk(void);
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
- "scan_dev_for_boot=" \
- "echo Scanning ${devtype} " \
- "${devnum}:${distro_bootpart}...; " \
- "for prefix in ${boot_prefixes}; do " \
- "run scan_dev_for_scripts; " \
- "done;\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 2e2ba756a0b..729ad63cd50 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#ifndef __FM_ETH_H__
@@ -41,8 +42,19 @@ enum fm_eth_type {
FM_ETH_10G_E,
};
+/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
+ * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
+ * TGEC name).
+ *
+ * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
+ * and no TGEC ports are present on-board.
+ */
#ifdef CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_TARGET_LS1046AFRWY
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#else
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#endif
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CONFIG_SYS_NUM_FMAN == 2)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)