diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2015-08-18 10:51:00 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-11 21:27:15 +0100 |
| commit | d74c47c3647f9c11154e1d0bdcfabab819266d5c (patch) | |
| tree | 1ebae3da9bf8cec7f5f1c8103e619295a7ecaf9f /scripts | |
| parent | ea16d8f07e828ea00cfac4c07c75f62723ffbb25 (diff) | |
colibri_t20: implement early pmic rail configuration
Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.
(cherry picked from commit f7c3186985ebb244d075b04ed7c055f39f485670)
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/config_whitelist.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 30c9e5cbd8..5d5ecdc845 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7911,6 +7911,7 @@ CONFIG_TAM3517_SW3_SETTINGS CONFIG_TCA642X CONFIG_TEGRA_BOARD_STRING CONFIG_TEGRA_CLOCK_SCALING +CONFIG_TEGRA_EARLY_TPS6586X CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTB CONFIG_TEGRA_ENABLE_UARTC |