diff options
601 files changed, 40490 insertions, 2676 deletions
@@ -2445,10 +2445,13 @@ endif $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost quiet_cmd_genenv = GENENV $@ -cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \ - sed --in-place -e 's/\x00/\x0A/g' $@ +cmd_genenv = \ + $(objtree)/tools/printinitialenv | \ + sed -e '/^\s*$$/d' | \ + sort --field-separator== -k1,1 --stable -o $@ -u-boot-initial-env: u-boot.bin +u-boot-initial-env: $(env_h) FORCE + $(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv $(call if_changed,genenv) # Consistency checks diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3284211556..09da1b375b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -839,6 +839,19 @@ config ARCH_IMX8ULP select SYS_FSL_HAS_SEC select SYS_FSL_SEC_LE select SYS_FSL_SEC_COMPAT_4 + select MISC + select IMX_SENTINEL + imply CMD_DM + +config ARCH_IMX9 + bool "NXP i.MX9 platform" + select ARM64 + select DM + select MACH_IMX + select SUPPORT_SPL + select GPIO_EXTRA_HEADER + select MISC + select IMX_SENTINEL imply CMD_DM config ARCH_IMXRT @@ -2137,6 +2150,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/imx8ulp/Kconfig" +source "arch/arm/mach-imx/imx9/Kconfig" + source "arch/arm/mach-imx/imxrt/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" @@ -2193,6 +2208,8 @@ source "arch/arm/cpu/armv7/Kconfig" source "arch/arm/cpu/armv8/Kconfig" +source "arch/arm/cpu/armv8/crypto/Kconfig" + source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-nexell/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f35b246a5c..5bfc30861b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -32,7 +32,7 @@ else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) endif -ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP),) +ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP)$(CONFIG_ARCH_IMX9),) arch-y += -mgeneral-regs-only endif @@ -116,11 +116,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imx9 imxrt)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imx9 imxrt vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 85fe0475c8..6e1498b470 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += crypto/ diff --git a/arch/arm/cpu/armv8/crypto/Kconfig b/arch/arm/cpu/armv8/crypto/Kconfig new file mode 100644 index 0000000000..379c673343 --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Kconfig @@ -0,0 +1,6 @@ +if ARM64 + +config CRYPTO_SHA2_ARM64_CE + tristate "SHA-224/SHA-256 digest algorithm (ARMv8 Crypto Extensions)" + +endif diff --git a/arch/arm/cpu/armv8/crypto/Makefile b/arch/arm/cpu/armv8/crypto/Makefile new file mode 100644 index 0000000000..8b23b166ed --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += sha2-ce.o +sha2-ce-y := sha2-ce-glue.o sha2-ce-core.o diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-core.S b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S new file mode 100644 index 0000000000..ad76362dff --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org> + * Copyright 2022 NXP + */ + +#include <linux/linkage.h> +#include <asm/macro.h> + + .text + .arch armv8-a+crypto + + dga .req q20 + dgav .req v20 + dgb .req q21 + dgbv .req v21 + + t0 .req v22 + t1 .req v23 + + dg0q .req q24 + dg0v .req v24 + dg1q .req q25 + dg1v .req v25 + dg2q .req q26 + dg2v .req v26 + + .macro add_only, ev, rc, s0 + mov dg2v.16b, dg0v.16b + .ifeq \ev + add t1.4s, v\s0\().4s, \rc\().4s + sha256h dg0q, dg1q, t0.4s + sha256h2 dg1q, dg2q, t0.4s + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha256h dg0q, dg1q, t1.4s + sha256h2 dg1q, dg2q, t1.4s + .endif + .endm + + .macro add_update, ev, rc, s0, s1, s2, s3 + sha256su0 v\s0\().4s, v\s1\().4s + add_only \ev, \rc, \s1 + sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s + .endm + + /* + * The SHA-256 round constants + */ + .section ".rodata", "a" + .align 4 +.Lsha2_rcon: + .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5 + .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5 + .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3 + .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174 + .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc + .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da + .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7 + .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967 + .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13 + .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85 + .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3 + .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070 + .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5 + .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3 + .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208 + .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 + + /* + * void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + * int blocks) + */ + .text +ENTRY(sha2_ce_transform) + /* load round constants */ + adr_l x8, .Lsha2_rcon + ld1 { v0.4s- v3.4s}, [x8], #64 + ld1 { v4.4s- v7.4s}, [x8], #64 + ld1 { v8.4s-v11.4s}, [x8], #64 + ld1 {v12.4s-v15.4s}, [x8] + + /* load state */ + ld1 {dgav.4s, dgbv.4s}, [x0] + + /* load sha256_ce_state::finalize */ + ldr_l w4, sha256_ce_offsetof_finalize, x4 + ldr w4, [x0, x4] + + /* load input */ +0: ld1 {v16.4s-v19.4s}, [x1], #64 + sub w2, w2, #1 + +CPU_LE( rev32 v16.16b, v16.16b ) +CPU_LE( rev32 v17.16b, v17.16b ) +CPU_LE( rev32 v18.16b, v18.16b ) +CPU_LE( rev32 v19.16b, v19.16b ) + +1: add t0.4s, v16.4s, v0.4s + mov dg0v.16b, dgav.16b + mov dg1v.16b, dgbv.16b + + add_update 0, v1, 16, 17, 18, 19 + add_update 1, v2, 17, 18, 19, 16 + add_update 0, v3, 18, 19, 16, 17 + add_update 1, v4, 19, 16, 17, 18 + + add_update 0, v5, 16, 17, 18, 19 + add_update 1, v6, 17, 18, 19, 16 + add_update 0, v7, 18, 19, 16, 17 + add_update 1, v8, 19, 16, 17, 18 + + add_update 0, v9, 16, 17, 18, 19 + add_update 1, v10, 17, 18, 19, 16 + add_update 0, v11, 18, 19, 16, 17 + add_update 1, v12, 19, 16, 17, 18 + + add_only 0, v13, 17 + add_only 1, v14, 18 + add_only 0, v15, 19 + add_only 1 + + /* update state */ + add dgav.4s, dgav.4s, dg0v.4s + add dgbv.4s, dgbv.4s, dg1v.4s + + /* handled all input blocks? */ + cbz w2, 2f + b 0b + + /* + * Final block: add padding and total bit count. + * Skip if the input size was not a round multiple of the block size, + * the padding is handled by the C code in that case. + */ +2: cbz x4, 3f + ldr_l w4, sha256_ce_offsetof_count, x4 + ldr x4, [x0, x4] + movi v17.2d, #0 + mov x8, #0x80000000 + movi v18.2d, #0 + ror x7, x4, #29 // ror(lsl(x4, 3), 32) + fmov d16, x8 + mov x4, #0 + mov v19.d[0], xzr + mov v19.d[1], x7 + b 1b + + /* store new state */ +3: st1 {dgav.4s, dgbv.4s}, [x0] + mov w0, w2 + ret +ENDPROC(sha2_ce_transform) diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c new file mode 100644 index 0000000000..31e436ef1d --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha2-ce-glue.c - SHA-256 using ARMv8 Crypto Extensions + * + * Copyright (C) 2014 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org> + * Copyright 2022 NXP + */ + +#include <linux/kernel.h> +#include <linux/linkage.h> +#include <crypto/sha256_base.h> + +struct sha256_ce_state { + struct sha256_state sst; + u32 finalize; +}; + +extern const u32 sha256_ce_offsetof_count; +extern const u32 sha256_ce_offsetof_finalize; + +asmlinkage int sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + int blocks); + +static void __sha2_ce_transform(struct sha256_state *sst, u8 const *src, + int blocks) +{ + while (blocks) { + int rem; + + rem = sha2_ce_transform(container_of(sst, struct sha256_ce_state, + sst), src, blocks); + src += (blocks - rem) * SHA256_BLOCK_SIZE; + blocks = rem; + } +} + +const u32 sha256_ce_offsetof_count = offsetof(struct sha256_ce_state, + sst.count); +const u32 sha256_ce_offsetof_finalize = offsetof(struct sha256_ce_state, + finalize); + +static void sha256_ce_update(struct sha256_ce_state *sctx, const u8 *data, + unsigned int len) +{ + sctx->finalize = 0; + sha256_base_do_update(&sctx->sst, data, len, __sha2_ce_transform); +} + +static void sha256_ce_final(struct sha256_ce_state *sctx, u8 *out) +{ + sctx->finalize = 0; + sha256_base_do_finalize(&sctx->sst, __sha2_ce_transform); + sha256_base_finish(&sctx->sst, out); +} + +/* + * Output = SHA-256( input buffer ). + */ +void sha256_ce(const unsigned char *input, unsigned int ilen, unsigned char *output) +{ + struct sha256_ce_state sctx; + + sha256_init(&sctx.sst); + sha256_ce_update(&sctx, input, ilen); + sha256_ce_final(&sctx, output); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8d35a96f61..45a79f0201 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -959,13 +959,16 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb \ imx8ulp-evk-i3c.dtb \ imx8ulp-9x9-evk.dtb \ - imx8ulp-9x9-evk-i3c.dtb + imx8ulp-9x9-evk-i3c.dtb \ + imx8ulp-watch.dtb dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-ddr4-evk.dtb \ + imx8mm-ddr4-ab2.dtb \ imx8mm-ddr3l-val.dtb \ imx8mm-ddr4-val.dtb \ imx8mm-evk.dtb \ + imx8mm-ab2.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-n801x-s.dtb \ @@ -980,8 +983,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ phycore-imx8mm.dtb \ imx8mn-ddr3l-evk.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-ddr4-ab2.dtb \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ + imx8mn-ab2.dtb \ imx8mn-var-som-symphony.dtb \ imx8mn-venice.dtb \ imx8mn-venice-gw7902.dtb \ @@ -999,6 +1004,11 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb +dtb-$(CONFIG_ARCH_IMX9) += \ + imx93-11x11-evk.dtb \ + imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dts + dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts index 040e52912e..3fe19b9848 100644 --- a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts +++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts @@ -100,8 +100,8 @@ SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c - SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 956d724979..22b34c8feb 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -2,6 +2,32 @@ /* * Copyright 2019 Toradex AG */ +/ { + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-pre-proper; +}; &mu { u-boot,dm-pre-proper; @@ -75,6 +101,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -93,6 +135,12 @@ &gpio4 { u-boot,dm-pre-proper; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { @@ -123,6 +171,32 @@ u-boot,dm-pre-proper; }; +/* USB */ +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + dr_mode = "host"; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e..298e4b5907 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2019 Toradex + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -9,7 +9,6 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-apalis-u-boot.dtsi" / { model = "Toradex Apalis iMX8"; @@ -19,6 +18,34 @@ bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; stdout-path = &lpuart1; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-0 = <&pinctrl_gpio_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + }; }; &iomuxc { @@ -30,8 +57,6 @@ <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>, <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>, <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>, - <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>, - <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>, <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, @@ -587,10 +612,26 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; +}; + /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; @@ -598,8 +639,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; bus-width = <8>; cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ status = "okay"; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index 322429a98a..84417d0ea6 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -3,6 +3,34 @@ * Copyright 2019 Toradex AG */ +/ { + aliases { + usbgadget0 = &usbg1; + usbhost1 = &usbh3; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + chipidea,usb = <&usbotg1>; + dr_mode = "peripheral"; + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + cdns3,usb = <&usbotg3>; + dr_mode = "host"; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + &{/imx8qx-pm} { u-boot,dm-pre-proper; @@ -72,6 +100,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &pd_conn_sdch0 { u-boot,dm-pre-proper; }; @@ -84,6 +128,21 @@ u-boot,dm-pre-proper; }; +&gpio_expander_43 { + usb-bypass-n-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + line-name = "usb-bypass-n"; + output-high; + }; + usb-reset-n-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + line-name = "usb-reset-n"; + output-low; + }; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -120,6 +179,30 @@ u-boot,dm-pre-proper; }; +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + #phy-cells = <0>; + reg = <0x0 0x5B160000 0x0 0x40000>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index df992ac639..a672347e1a 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX8X"; @@ -320,8 +319,6 @@ gpio-controller; #gpio-cells = <2>; reg = <0x43>; - initial_io_dir = <0xff>; - initial_output = <0x05>; }; }; @@ -353,3 +350,18 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; status = "okay"; }; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 46e7ad6bab..c5d5a5ab7b 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -66,6 +66,12 @@ clocks = <&clks IMX6ULL_CLK_DCP_CLK>; clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi new file mode 100644 index 0000000000..c0b93bf9c1 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts new file mode 100644 index 0000000000..6d3667ef9a --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi new file mode 100644 index 0000000000..d945d27c54 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ audio-codec; + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + /delete-node/ sound-wm8524; + + leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&fec1 { + mdio { + ethphy0: ethernet-phy@0 { + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&sai3 { + status = "disabled"; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..27daf58a22 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts new file mode 100644 index 0000000000..418db5789e --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM DDR4 Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 9d8f07cfa9..95d339bb37 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -300,7 +300,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index 25bddb4610..311aa39d4c 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -39,6 +39,10 @@ u-boot,dm-spl; }; +&aips4 { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; }; @@ -57,12 +61,20 @@ &gpio5 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &i2c1 { u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -91,6 +103,18 @@ u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi new file mode 100644 index 0000000000..689f6f3218 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts new file mode 100644 index 0000000000..9a5b5f63f8 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi new file mode 100644 index 0000000000..039f3d549a --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + + gpio-leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + mdio { + ethphy0: ethernet-phy@0 { + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi new file mode 100644 index 0000000000..9d595da3a9 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ab2-u-boot.dtsi" + +&blob_1 { + filename = "ddr3_imem_1d_201810.bin"; +}; + +&blob_2 { + filename = "ddr3_dmem_1d_201810.bin"; +}; + +/delete-node/ &blob_3; + +/delete-node/ &blob_4; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts new file mode 100644 index 0000000000..b89e1ce81b --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr3l-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR3L Audio board 2.0"; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..6df56985d6 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts new file mode 100644 index 0000000000..40c9c56bfc --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 00c91d1ae4..d533520efa 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -115,7 +115,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 16d98cb659..203d05e66e 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -39,8 +39,11 @@ */ start-config = < RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index a5c797d357..61e8a70196 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -13,7 +13,7 @@ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { - bootargs = "console=ttymxc1,115200"; + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; @@ -308,7 +308,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h index 420e584bff..155aab1428 100644 --- a/arch/arm/dts/imx8mp-sec-def.h +++ b/arch/arm/dts/imx8mp-sec-def.h @@ -26,6 +26,7 @@ #define D0W 0x00000001 #define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */ +#define PDAP_D0D1_ACCESS 0x0000000F /* D0R|D0W|D1W|D1R */ #define MEM_D1_ACCESS 0x4000000C /* ENA|D1W|D1R */ #define MEM_D0D1_ACCESS 0x4000000F /* ENA|D0W|D0R|D1W|D1R */ @@ -53,6 +54,8 @@ #define RDC_MDA_uSDHC1 15 #define RDC_MDA_uSDHC2 16 #define RDC_MDA_uSDHC3 17 +#define RDC_MDA_ENET1_TX 22 +#define RDC_MDA_ENET1_RX 23 #define RDC_MDA_SDMA3_SPBA2 25 #define RDC_MDA_LCDIF2 27 #define RDC_MDA_HDMI_TX 28 diff --git a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi index 8aec33a463..3f44af90e7 100644 --- a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi @@ -74,6 +74,10 @@ }; +&crypto { + u-boot,dm-spl; +}; + &eqos { compatible = "fsl,imx-eqos"; /delete-property/ assigned-clocks; @@ -95,6 +99,10 @@ &gpio4 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &gpio5 { @@ -113,6 +121,10 @@ u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -150,6 +162,18 @@ u-boot,dm-spl; }; +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &uart3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-verdin.dts b/arch/arm/dts/imx8mp-verdin.dts index a50f42f4ce..19ce3ee193 100644 --- a/arch/arm/dts/imx8mp-verdin.dts +++ b/arch/arm/dts/imx8mp-verdin.dts @@ -88,7 +88,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; }; +}; +&gpio4 { ctrl_sleep_moci { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 2876b94b2a..4662d53183 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -979,7 +979,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-fspi-nand"; - reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; reg-names = "FlexSPI", "FlexSPI-memory"; status = "disabled"; }; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 0c2dcc0792..b22d62c0d9 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -33,6 +33,18 @@ u-boot,dm-spl; }; +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + &per_bridge3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8ulp-watch-u-boot.dtsi b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi new file mode 100644 index 0000000000..a918ce0a05 --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + dsi_host: dsi-host { + compatible = "northwest,mipi-dsi"; + status = "okay"; + }; +}; + +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + +&per_bridge3 { + u-boot,dm-spl; +}; + +&per_bridge4 { + u-boot,dm-spl; +}; + +&iomuxc1 { + u-boot,dm-spl; + fsl,mux_mask = <0xf00>; +}; + +&pinctrl_lpuart5 { + u-boot,dm-spl; +}; + +&s400_mu { + u-boot,dm-spl; +}; + +&lpuart5 { + u-boot,dm-spl; +}; + +&usdhc0 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&pinctrl_usdhc0 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; + +&scmi_buf { + reg = <0x0 0x1000>; /* Align page size */ +}; + +&dsi { + data-lanes-num = <4>; +}; + +&usbotg1 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb"; + fsl,usbphy = <&usbphy1>; +}; diff --git a/arch/arm/dts/imx8ulp-watch.dts b/arch/arm/dts/imx8ulp-watch.dts new file mode 100644 index 0000000000..232485486c --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP WATCH"; + compatible = "fsl,imx8ulp-watch", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + bootargs = "console=ttyLP1,115200 earlycon"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + linux,cma-default; + }; + + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + + +&clock_ext_ts { + /* External ts clock is 50MHZ from PHY on EVK board. */ + clock-frequency = <50000000>; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_otgid1>; + pinctrl-1 = <&pinctrl_otgid1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_otgid1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 + >; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "usmp,rm67162"; + reg = <0>; + dsi-lanes = <1>; + reset,otherway; + vcc-supply = <®_5v>; + iovcc-supply = <®_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dcnano { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&usbotg2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi index 155d29fb19..901766957d 100644 --- a/arch/arm/dts/imx8ulp.dtsi +++ b/arch/arm/dts/imx8ulp.dtsi @@ -157,6 +157,11 @@ reg = <0x11>; #power-domain-cells = <1>; }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi new file mode 100644 index 0000000000..13474a35fc --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c3 { + u-boot,dm-spl; +}; + +&fec { + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&ptn5110_2>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts new file mode 100644 index 0000000000..c82e5a9c67 --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk.dts @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + i2c8 = &flexio_i2c_master; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + audio: audio@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; + enable-active-low; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dsi_host: dsi-host { + compatible = "synopsys,dw-mipi-dsi"; + status = "okay"; + }; + + rm67199_panel { + compatible = "raydium,rm67199"; + reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_to_adv7535: endpoint { + remote-endpoint = <&adv7535_to_dsi>; + }; + }; + + port@2 { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + interrupt-parent = <&pcal6524>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585gpio: gpio@34 { + compatible = "adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&pcal6524>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + status = "okay"; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; + +&wdog3 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts new file mode 100644 index 0000000000..6eb09ec9e3 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" +#include "imx93-9x9-qsb-u-boot.dtsi" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1", "simple-panel"; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + + vsync-active = <0>; + hsync-active = <0>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + /*assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>;*/ +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 0000000000..06935ce1e4 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts new file mode 100644 index 0000000000..accb295c03 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-micfil"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 0000000000..4298a145f8 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 +#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 +#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 +#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 +#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 +#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 +#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 +#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 +#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 +#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 +#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 +#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 +#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 +#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 +#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 +#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 +#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 +#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 +#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 +#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 +#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 +#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 +#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 +#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 +#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 +#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 +#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 +#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 +#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 +#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 +#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 +#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 +#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 +#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 +#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 +#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 +#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 +#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 +#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 +#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 +#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 +#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 +#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 +#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 +#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 +#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 +#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 +#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 +#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 +#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 +#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 +#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 +#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 +#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 +#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 +#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 +#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 +#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 +#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 +#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 +#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 +#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 +#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 +#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 +#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 +#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 +#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 +#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 +#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 +#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 +#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 +#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 +#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 +#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 +#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 +#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 +#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 +#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 +#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 +#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 +#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 +#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 +#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 +#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 +#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 +#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 +#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 +#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 +#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 +#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 +#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 +#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 +#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 +#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 +#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 +#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 +#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 +#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 +#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 +#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 +#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 +#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 +#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 +#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 +#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 +#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 +#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 +#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 +#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 +#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 +#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 +#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 +#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 +#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 +#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 +#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 +#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 +#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 +#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 +#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 +#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 +#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 +#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 +#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 +#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 +#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 +#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 +#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 + +#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi new file mode 100644 index 0000000000..be4626d5e7 --- /dev/null +++ b/arch/arm/dts/imx93.dtsi @@ -0,0 +1,1503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/imx93-power.h> +#include <dt-bindings/usb/pd.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &flexspi; + isi0 = &isi_0; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + csi0 = &mipi_csi; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + edma1: dma-controller@44000000{ + compatible = "fsl,imx93-edma-v3"; + reg = <0x44000000 0x10000>, + <0x44010000 0x10000>, <0x44020000 0x10000>, + <0x44030000 0x10000>, <0x44040000 0x10000>, + <0x44050000 0x10000>, <0x44060000 0x10000>, + <0x44070000 0x10000>, <0x44080000 0x10000>, + <0x44090000 0x10000>, <0x440a0000 0x10000>, + <0x440b0000 0x10000>, <0x440c0000 0x10000>, + <0x440d0000 0x10000>, <0x440e0000 0x10000>, + <0x440f0000 0x10000>, <0x44100000 0x10000>, + <0x44110000 0x10000>, <0x44120000 0x10000>, + <0x44130000 0x10000>, <0x44140000 0x10000>, + <0x44150000 0x10000>, <0x44160000 0x10000>, + <0x44170000 0x10000>, <0x44180000 0x10000>, + <0x44190000 0x10000>, <0x441a0000 0x10000>, + <0x441b0000 0x10000>, <0x441c0000 0x10000>, + <0x441d0000 0x10000>, <0x441e0000 0x10000>, + <0x441f0000 0x10000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-err"; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + anomix_ns_gpr: blk-ctrl-anomix@42420000 { + compatible = "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + i3c1: i3c-master@44330000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_LPI2C1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_LPI2C2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_LPSPI1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_LPSPI2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + /* sai1 supports 2x TX/RX */ + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&anomix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + }; + + bbnsm: bbnsm@44440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,bbnsm-rtc"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,bbnsm-pwrkey"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + src: src@44460000 { + compatible = "fsl,imx93-src"; + reg = <0x44460000 0x10000>; + + slice { + #address-cells = <1>; + #size-cells = <0>; + + mlmix: slice@1800 { + reg = <IMX93_POWER_DOMAIN_MLMIX>; + #power-domain-cells = <0>; + }; + + mediamix: slice@2400 { + reg = <IMX93_POWER_DOMAIN_MEDIAMIX>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + + tmu: tmu@44482000 { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <0>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + /* + 199 pdm ipi_int_hwvad_err + 200 pdm ipi_int_hwvad_event + 201 pdm ipi_int_mic_err + 202 pdm ipi_int_mic_filter + */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "clkext3"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@42000000{ + compatible = "fsl,imx93-edma-v4"; + reg = <0x42000000 0x10000>, + <0x42010000 0x8000>, <0x42018000 0x8000>, + <0x42020000 0x8000>, <0x42028000 0x8000>, + <0x42030000 0x8000>, <0x42038000 0x8000>, + <0x42040000 0x8000>, <0x42048000 0x8000>, + <0x42050000 0x8000>, <0x42058000 0x8000>, + <0x42060000 0x8000>, <0x42068000 0x8000>, + <0x42070000 0x8000>, <0x42078000 0x8000>, + <0x42080000 0x8000>, <0x42088000 0x8000>, + <0x42090000 0x8000>, <0x42098000 0x8000>, + <0x420a0000 0x8000>, <0x420a8000 0x8000>, + <0x420b0000 0x8000>, <0x420b8000 0x8000>, + <0x420c0000 0x8000>, <0x420c8000 0x8000>, + <0x420d0000 0x8000>, <0x420d8000 0x8000>, + <0x420e0000 0x8000>, <0x420e8000 0x8000>, + <0x420f0000 0x8000>, <0x420f8000 0x8000>, + <0x42100000 0x8000>, <0x42108000 0x8000>, + <0x42110000 0x8000>, <0x42118000 0x8000>, + <0x42120000 0x8000>, <0x42128000 0x8000>, + <0x42130000 0x8000>, <0x42138000 0x8000>, + <0x42140000 0x8000>, <0x42148000 0x8000>, + <0x42150000 0x8000>, <0x42158000 0x8000>, + <0x42160000 0x8000>, <0x42168000 0x8000>, + <0x42170000 0x8000>, <0x42178000 0x8000>, + <0x42180000 0x8000>, <0x42188000 0x8000>, + <0x42190000 0x8000>, <0x42198000 0x8000>, + <0x421a0000 0x8000>, <0x421a8000 0x8000>, + <0x421b0000 0x8000>, <0x421b8000 0x8000>, + <0x421c0000 0x8000>, <0x421c8000 0x8000>, + <0x421d0000 0x8000>, <0x421d8000 0x8000>, + <0x421e0000 0x8000>, <0x421e8000 0x8000>, + <0x421f0000 0x8000>, <0x421f8000 0x8000>, + <0x42200000 0x8000>, <0x42208000 0x8000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx", + "edma2-chan32-tx", "edma2-chan33-tx", + "edma2-chan34-tx", "edma2-chan35-tx", + "edma2-chan36-tx", "edma2-chan37-tx", + "edma2-chan38-tx", "edma2-chan39-tx", + "edma2-chan40-tx", "edma2-chan41-tx", + "edma2-chan42-tx", "edma2-chan43-tx", + "edma2-chan44-tx", "edma2-chan45-tx", + "edma2-chan46-tx", "edma2-chan47-tx", + "edma2-chan48-tx", "edma2-chan49-tx", + "edma2-chan50-tx", "edma2-chan51-tx", + "edma2-chan52-tx", "edma2-chan53-tx", + "edma2-chan54-tx", "edma2-chan55-tx", + "edma2-chan56-tx", "edma2-chan57-tx", + "edma2-chan58-tx", "edma2-chan59-tx", + "edma2-chan60-tx", "edma2-chan61-tx", + "edma2-chan62-tx", "edma2-chan63-tx", + "edma2-err"; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { + compatible = "syscon"; + reg = <0x42420000 0x1000>; + }; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: wdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + assigned-clocks = <&clk IMX93_CLK_TPM4>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c-master@42520000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_LPI2C3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_LPI2C4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_LPSPI3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_LPSPI4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + dmas = <&edma2 17 0 0>, <&edma2 18 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + dmas = <&edma2 19 0 0>, <&edma2 20 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + dmas = <&edma2 21 0 0>, <&edma2 22 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + dmas = <&edma2 23 0 0>, <&edma2 24 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexspi: spi@425e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 59 0 1>, <&edma1 58 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif: spdif@42680000 { + compatible = "fsl,imx93-spdif"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + /* XCVR PHY - SPDIF wakeup IRQ */ + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + dmas = <&edma2 87 0 0>, <&edma2 88 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + dmas = <&edma2 89 0 0>, <&edma2 90 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_LPI2C5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_LPI2C6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_LPI2C7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_LPI2C8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_LPSPI5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_LPSPI6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_LPSPI7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_LPSPI8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexio_i2c_master: flexio@425c0000 { + compatible = "imx,flexio_i2c_master"; + reg = <0x425c0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXIO1_GATE>, + <&clk IMX93_CLK_FLEXIO1_GATE>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + reg = <0x42890000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_WAKEUP_AXI>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + clk_csr = <0>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + epxp: epxp@4ae20000 { + compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma"; + reg = <0x4ae20000 0x10000>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pxp_ipg", "pxp_axi"; + pxp-gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@4ae40000{ + compatible = "fsl,imx93-isi", "fsl,imx8-isi"; + reg = <0x4ae40000 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "per", "axi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333333>; + interface = <2 0 2>; + no-reset-control; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>; + gasket = <&media_blk_ctrl>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi: csi@4ae00000 { + compatible = "fsl,dwc-mipi-csi2-host"; + reg = <0x4ae00000 0x10000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + clock-names = "clk_core", "clk_pixel", "phy_cfg"; + assigned-clocks = <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_24M>; + assigned-clock-rates = <140000000>, <24000000>; + gasket = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>; + status = "disabled"; + }; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO2>, + <&clk IMX93_CLK_PCTL2>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO3>, + <&clk IMX93_CLK_PCTL3>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO4>, + <&clk IMX93_CLK_PCTL4>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO1>, + <&clk IMX93_CLK_PCTL1>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 0 32>; + }; + + ocotp: efuse@47510000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x1000>; + status = "disabled"; + }; + + s4muap: s4muap@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "txirq", "rxirq"; + #mbox-cells = <2>; + status = "okay"; + }; + + sentnl_mu: sentnl-mu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx-sentnl"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,sentnl_mu_id = <2>; + fsl,sentnl_mu_max_users = <4>; + status = "okay"; + dma-ranges = <0x80000000 0x80000000 0x20000000>; + }; + + media_blk_ctrl: blk-ctrl@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, + <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + }; + + parallel_disp_fmt: dpi { + compatible = "fsl,imx93-parallel-display-format"; + /* power-domains = <&mediamix>; [Not enable for U-Boot], otherwise driver probe fail */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + }; + }; + }; + + ldb: ldb@4ac10020 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-ldb"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + gpr = <&media_blk_ctrl>; + power-domains = <&mediamix>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + }; + }; + + ldb_phy: phy@4ac10024 { + compatible = "fsl,imx93-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_APB>; + clock-names = "apb"; + power-domains = <&mediamix>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + dsi: dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x4000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "byte", "pclk"; + assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <20000000>, <133333334>; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + }; + }; + + lcdif: lcd-controller@4ae30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + fsl,gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_LCDIF_GATE>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_24M>, + <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif_to_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_to_lcdif>; + }; + + lcdif_to_ldb: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif_to_dpi: endpoint@2 { + reg = <2>; + remote-endpoint = <&dpi_to_lcdif>; + }; + }; + }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp>; + }; +}; diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi new file mode 100644 index 0000000000..3711e42419 --- /dev/null +++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2022 NXP + */ + +&{/soc} { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index bf96af7e36..82df2f11bb 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -6,6 +6,7 @@ */ #include "ls1021a.dtsi" +#include "ls1021a-twr-u-boot.dtsi" / { model = "LS1021A TWR Board"; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 63bb3fb2bf..36f51e0792 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -61,6 +61,14 @@ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ +#define MXC_CPU_IMX93 0xC1 /* dummy ID */ +#define MXC_CPU_IMX9351 0xC2 /* dummy ID */ +#define MXC_CPU_IMX9332 0xC3 /* dummy ID */ +#define MXC_CPU_IMX9331 0xC4 /* dummy ID */ +#define MXC_CPU_IMX9322 0xC5 /* dummy ID */ +#define MXC_CPU_IMX9321 0xC6 /* dummy ID */ +#define MXC_CPU_IMX9312 0xC7 /* dummy ID */ +#define MXC_CPU_IMX9311 0xC8 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 @@ -68,6 +76,7 @@ #define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_IMXRT 0xB0 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ +#define MXC_SOC_IMX9 0xC0 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c03..5e4fbecf05 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -724,6 +724,8 @@ void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + static inline void reg32_write(unsigned long addr, u32 val) { writel(val, addr); @@ -740,9 +742,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit) } #define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) #define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) extern struct dram_cfg_param ddrphy_trained_csr[]; extern uint32_t ddrphy_trained_csr_num; diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index f8115ce3fa..e07012e7d6 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -67,6 +67,8 @@ #define FEC_QUIRK_ENET_MAC +#define IMG_CONTAINER_BASE (0x22010000UL) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h index b002970fd8..cdea5d6f3c 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -30,6 +30,7 @@ enum { IMX8ULP_PAD_PTC8__FLEXSPI0_A_DATA2 = IOMUX_PAD(0x0120, 0x0120, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), IMX8ULP_PAD_PTC9__FLEXSPI0_A_DATA1 = IOMUX_PAD(0x0124, 0x0124, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), IMX8ULP_PAD_PTC10__FLEXSPI0_A_DATA0 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), IMX8ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0000, 0x0000, 0x8, 0x0000, 0x0, 0), @@ -72,6 +73,6 @@ enum { IMX8ULP_PAD_PTF5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0A6C, 0x2, 0), IMX8ULP_PAD_PTF0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0A68, 0x2, 0), IMX8ULP_PAD_PTF1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0A64, 0x2, 0), - + IMX8ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), }; #endif /* __ASM_ARCH_IMX8ULP_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h deleted file mode 100644 index b3e6b3fa45..0000000000 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - -#ifndef __S400_API_H__ -#define __S400_API_H__ - -#define AHAB_VERSION 0x6 -#define AHAB_CMD_TAG 0x17 -#define AHAB_RESP_TAG 0xe1 - -#define AHAB_LOG_CID 0x21 -#define AHAB_AUTH_OEM_CTNR_CID 0x87 -#define AHAB_VERIFY_IMG_CID 0x88 -#define AHAB_RELEASE_CTNR_CID 0x89 -#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 -#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 -#define AHAB_READ_FUSE_REQ_CID 0x97 -#define AHAB_GET_FW_VERSION_CID 0x9D -#define AHAB_RELEASE_RDC_REQ_CID 0xC4 -#define AHAB_WRITE_FUSE_REQ_CID 0xD6 -#define AHAB_CAAM_RELEASE_CID 0xD7 - -#define S400_MAX_MSG 255U - -struct imx8ulp_s400_msg { - u8 version; - u8 size; - u8 command; - u8 tag; - u32 data[(S400_MAX_MSG - 1U)]; -}; - -int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response); -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); -int ahab_release_container(u32 *response); -int ahab_verify_image(u32 img_id, u32 *response); -int ahab_forward_lifecycle(u16 life_cycle, u32 *response); -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); -int ahab_release_caam(u32 core_did, u32 *response); -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); -int ahab_dump_buffer(u32 *buffer, u32 buffer_length); - -#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 5f030eaa0a..e240ee6fca 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -19,5 +19,6 @@ enum boot_device get_boot_device(void); void set_lpav_qos(void); void load_lposc_fuse(void); bool m33_image_booted(void); +bool is_m33_handshake_necessary(void); int m33_image_handshake(ulong timeout_ms); #endif diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 0000000000..d326a6ea51 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT 0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT 5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT 7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT 14 +#define LPTMR2_CLK_ROOT 15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT 33 +#define LPI2C2_CLK_ROOT 34 +#define LPI2C3_CLK_ROOT 35 +#define LPI2C4_CLK_ROOT 36 +#define LPI2C5_CLK_ROOT 37 +#define LPI2C6_CLK_ROOT 38 +#define LPI2C7_CLK_ROOT 39 +#define LPI2C8_CLK_ROOT 40 +#define LPSPI1_CLK_ROOT 41 +#define LPSPI2_CLK_ROOT 42 +#define LPSPI3_CLK_ROOT 43 +#define LPSPI4_CLK_ROOT 44 +#define LPSPI5_CLK_ROOT 45 +#define LPSPI6_CLK_ROOT 46 +#define LPSPI7_CLK_ROOT 47 +#define LPSPI8_CLK_ROOT 48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT 51 +#define USDHC2_CLK_ROOT 52 +#define USDHC3_CLK_ROOT 53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT 67 +#define ML_CLK_ROOT 68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT 72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT 74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT 80 +#define TSTMR2_CLK_ROOT 81 +#define MQS1_CLK_ROOT 82 +#define MQS2_CLK_ROOT 83 +#define AUDIO_XCVR_CLK_ROOT 84 +#define SPDIF_CLK_ROOT 85 +#define ENET_CLK_ROOT 86 +#define ENET_TIMER1_CLK_ROOT 87 +#define ENET_TIMER2_CLK_ROOT 88 +#define ENET_REF_CLK_ROOT 89 +#define ENET_REF_PHY_CLK_ROOT 90 +#define I3C1_SLOW_CLK_ROOT 91 +#define I3C2_SLOW_CLK_ROOT 92 +#define USB_PHY_BURUNIN_CLK_ROOT 93 +#define PAL_CAME_SCAN_CLK_ROOT 94 +#define CLK_ROOT_NUM 95 + +#define CCGR_A55 0 +#define CCGR_CM33 1 +#define CCGR_ARMTROUT 2 +#define CCGR_SENT 3 +#define CCGR_BUSM 4 +#define CCGR_BUS7 5 +#define CCGR_BUSD 6 +#define CCGR_ANAD 7 +#define CCGR_SRC 8 +#define CCGR_CCM 9 +#define CCGR_GPC 10 +#define CCGR_ADC 11 +#define CCGR_WDG1 12 +#define CCGR_WDG2 13 +#define CCGR_WDG3 14 +#define CCGR_WDG4 15 +#define CCGR_WDG5 16 +#define CCGR_SEM1 17 +#define CCGR_SEM2 18 +#define CCGR_MUA 19 +#define CCGR_MUB 20 +#define CCGR_DMA1 21 +#define CCGR_DMA2 22 +#define CCGR_ROMCA55 23 +#define CCGR_ROMCM33 24 +#define CCGR_QSP1 25 +#define CCGR_AONRDC 26 +#define CCGR_WKUPRDC 27 +#define CCGR_FUSE 28 +#define CCGR_SNVH 29 +#define CCGR_SNVS 30 +#define CCGR_TRAC 31 +#define CCGR_SWO 32 +#define CCGR_IOCG 33 +#define CCGR_PIO1 34 +#define CCGR_PIO2 35 +#define CCGR_PIO3 36 +#define CCGR_PIO4 37 +#define CCGR_FIO1 38 +#define CCGR_FIO2 39 +#define CCGR_PIT1 40 +#define CCGR_PIT2 41 +#define CCGR_GPT1 42 +#define CCGR_GPT2 43 +#define CCGR_TPM1 44 +#define CCGR_TPM2 45 +#define CCGR_TPM3 46 +#define CCGR_TPM4 47 +#define CCGR_TPM5 48 +#define CCGR_TPM6 49 +#define CCGR_CAN1 50 +#define CCGR_CAN2 51 +#define CCGR_URT1 52 +#define CCGR_URT2 53 +#define CCGR_URT3 54 +#define CCGR_URT4 55 +#define CCGR_URT5 56 +#define CCGR_URT6 57 +#define CCGR_URT7 58 +#define CCGR_URT8 59 +#define CCGR_I2C1 60 +#define CCGR_I2C2 61 +#define CCGR_I2C3 62 +#define CCGR_I2C4 63 +#define CCGR_I2C5 64 +#define CCGR_I2C6 65 +#define CCGR_I2C7 66 +#define CCGR_I2C8 67 +#define CCGR_SPI1 68 +#define CCGR_SPI2 69 +#define CCGR_SPI3 70 +#define CCGR_SPI4 71 +#define CCGR_SPI5 72 +#define CCGR_SPI6 73 +#define CCGR_SPI7 74 +#define CCGR_SPI8 75 +#define CCGR_I3C1 76 +#define CCGR_I3C2 77 +#define CCGR_USDHC1 78 +#define CCGR_USDHC2 79 +#define CCGR_USDHC3 80 +#define CCGR_SAI1 81 +#define CCGR_SAI2 82 +#define CCGR_SAI3 83 +#define CCGR_W2AO 84 +#define CCGR_AO2W 85 +#define CCGR_MIPIC 86 +#define CCGR_MIPID 87 +#define CCGR_LVDS 88 +#define CCGR_LCDIF 89 +#define CCGR_PXP 90 +#define CCGR_ISI 91 +#define CCGR_NMED 92 +#define CCGR_DFI 93 +#define CCGR_DDRC 94 +#define CCGR_DFIC 95 +#define CCGR_DSSI 96 +#define CCGR_DBYP 97 +#define CCGR_DAPB 98 +#define CCGR_DRAMP 99 +#define CCGR_DCLKC 100 +#define CCGR_NCTL 101 +#define CCGR_GIC 102 +#define CCGR_NICAPB 103 +#define CCGR_USBC 104 +#define CCGR_USBT 105 +#define CCGR_HSIO 106 +#define CCGR_PDM 107 +#define CCGR_MQS1 108 +#define CCGR_MQS2 109 +#define CCGR_AXCVR 110 +#define CCGR_MECC 111 +#define CCGR_SPDIF 112 +#define CCGR_ML2NIC 113 +#define CCGR_MED2NIC 114 +#define CCGR_HSIO2NIC 115 +#define CCGR_W2NIC 116 +#define CCGR_NIC2W 117 +#define CCGR_NIC2DDR 118 +#define CCGR_HSIO32K 119 +#define CCGR_ENET1 120 +#define CCGR_ENETQOS 121 +#define CCGR_SYSCNT 122 +#define CCGR_TSTMR1 123 +#define CCGR_TSTMR2 124 +#define CCGR_TMC 125 +#define CCGR_PMRO 126 +#define CCGR_NUM 127 + +#define SHARED_GPR_EXT_CLK 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT1 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0) +#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1) +#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0) + +#define SHARED_GPR_A55_CLK 1 +#define SHARED_GPR_A55_CLK_SEL_CCM 0 +#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0) + +#define SHARED_GPR_DRAM_CLK 2 +#define SHARED_GPR_DRAM_CLK_SEL_PLL 0 +#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) + +#define SHARED_GPR_NUM 8 +#define PRIVATE_GPR_NUM 8 + +#define CLK_ROOT_STATUS_OFF BIT(24) +#define CLK_ROOT_STATUS_CHANGING BIT(31) +#define CLK_ROOT_MUX_MASK GENMASK(9, 8) +#define CLK_ROOT_MUX_SHIFT 8 +#define CLK_ROOT_DIV_MASK GENMASK(7, 0) + +#define CCM_AUTHEN_LOCK_TZ BIT(11) +#define CCM_AUTHEN_TZ_NS BIT(9) +#define CCM_AUTHEN_TZ_USER BIT(8) +#define CCM_AUTHEN_CPULPM_MODE BIT(2) +#define CCM_AUTHEN_AUTO_CTRL BIT(3) + +#endif diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h new file mode 100644 index 0000000000..758ee26ff2 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan at nxp.com> + */ + +#ifndef __CLOCK_IMX9__ +#define __CLOCK_IMX9__ + +#include <linux/bitops.h> + +#define MHZ(x) ((x) * 1000000UL) + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +enum ccm_clk_src { + OSC_24M_CLK, + ARM_PLL, + ARM_PLL_CLK, + SYS_PLL_PG, + SYS_PLL_PFD0_PG, + SYS_PLL_PFD0, + SYS_PLL_PFD0_DIV2, + SYS_PLL_PFD1_PG, + SYS_PLL_PFD1, + SYS_PLL_PFD1_DIV2, + SYS_PLL_PFD2_PG, + SYS_PLL_PFD2, + SYS_PLL_PFD2_DIV2, + AUDIO_PLL, + AUDIO_PLL_CLK, + DRAM_PLL, + DRAM_PLL_CLK, + VIDEO_PLL, + VIDEO_PLL_CLK, + OSCPLL_END, + EXT_CLK, +}; + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_FLEXSPI_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_UART_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +struct ccm_obs { + u32 direct; + u32 reserved[31]; +}; + +struct ccm_gpr { + u32 gpr; + u32 gpr_set; + u32 gpr_clr; + u32 gpr_tog; + u32 authen; + u32 authen_set; + u32 authen_clr; + u32 authen_tog; +}; + +struct ccm_lpcg_oscpll { + u32 direct; + u32 lpm_status0; + u32 lpm_status1; + u32 reserved0; + u32 lpm0; + u32 lpm1; + u32 reserved1; + u32 lpm_cur; + u32 status0; + u32 status1; + u32 reserved2[2]; + u32 authen; + u32 reserved3[3]; +}; + +struct ccm_root { + u32 control; + u32 control_set; + u32 control_clr; + u32 control_tog; + u32 reserved[4]; + u32 status0; + u32 reserved1[3]; + u32 authen; + u32 reserved2[19]; +}; + +struct ccm_reg { + struct ccm_root clk_roots[95]; /* 0x0 */ + u32 reserved_0[1312]; + struct ccm_obs clk_obs[6]; /* 0x4400 */ + u32 reserved_1[64]; + struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */ + u32 reserved_2[192]; + struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */ + u32 reserved_3[192]; + struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */ + u32 reserved_4[2768]; + struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */ +}; + +struct ana_pll_reg_elem { + u32 reg; + u32 reg_set; + u32 reg_clr; + u32 reg_tog; +}; + +struct ana_pll_dfs { + struct ana_pll_reg_elem dfs_ctrl; + struct ana_pll_reg_elem dfs_div; +}; + +struct ana_pll_reg { + struct ana_pll_reg_elem ctrl; + struct ana_pll_reg_elem ana_prg; + struct ana_pll_reg_elem test; + struct ana_pll_reg_elem ss; /* Spread spectrum */ + struct ana_pll_reg_elem num; /* numerator */ + struct ana_pll_reg_elem denom; /* demoninator */ + struct ana_pll_reg_elem div; + struct ana_pll_dfs dfs[4]; + u32 pll_status; + u32 dfs_status; + u32 reserved[2]; +}; + +struct anatop_reg { + u32 osc_ctrl; + u32 osc_state; + u32 reserved_0[510]; + u32 chip_version; + u32 reserved_1[511]; + struct ana_pll_reg arm_pll; + struct ana_pll_reg sys_pll; + struct ana_pll_reg audio_pll; + struct ana_pll_reg dram_pll; + struct ana_pll_reg video_pll; +}; + +#define PLL_CTRL_HW_CTRL_SEL BIT(16) +#define PLL_CTRL_CLKMUX_BYPASS BIT(2) +#define PLL_CTRL_CLKMUX_EN BIT(1) +#define PLL_CTRL_POWERUP BIT(0) + +#define PLL_STATUS_PLL_LOCK BIT(0) +#define PLL_DFS_CTRL_ENABLE BIT(31) +#define PLL_DFS_CTRL_CLKOUT BIT(30) +#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29) +#define PLL_DFS_CTRL_BYPASS BIT(23) + +#define PLL_SS_EN BIT(15) + +struct imx_intpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; +}; + +struct imx_fracpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; + int mfn; + int mfd; +}; + +#define INT_PLL_RATE(_rate, _r, _m, _o) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + } + +#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + .mfn = (_n), \ + .mfd = (_d), \ + } + +struct clk_root_map { + u32 clk_root_id; + u32 mux_type; +}; + + +int clock_init(void); +u32 get_clk_src_rate(enum ccm_clk_src source); +u32 get_lpuart_clk(void); +void init_uart_clk(u32 index); +void init_clk_usdhc(u32 index); +int enable_i2c_clk(unsigned char enable, u32 i2c_num); +u32 imx_get_i2cclk(u32 i2c_num); +u32 mxc_get_clock(enum mxc_clock clk); +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); +void set_arm_core_max_clk(void); + +int configure_intpll(enum ccm_clk_src pll, u32 freq); + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val); +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll); +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div); +u32 ccm_clk_root_get_rate(u32 clk_root_id); +int ccm_clk_root_tz_access(u32 clk_root_id, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_lpcg_on(u32 lpcg, bool enable); +int ccm_lpcg_lpm(u32 lpcg, bool enable); +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val); +bool ccm_lpcg_is_clk_on(u32 lpcg); +int ccm_lpcg_tz_access(u32 lpcg, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_shared_gpr_set(u32 gpr, u32 val); +int ccm_shared_gpr_get(u32 gpr, u32 *val); +int ccm_shared_gpr_tz_access(u32 gpr, + bool non_secure, bool user_mode, bool lock_tz); + +void enable_usboh3_clk(unsigned char enable); +int set_clk_enet(enum enet_freq type); +int set_clk_eqos(enum enet_freq type); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +#endif diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h new file mode 100644 index 0000000000..af5e6b5764 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include <asm/io.h> +#include <asm/types.h> + +#define DDR_CTL_BASE 0x4E300000 +#define DDR_PHY_BASE 0x4E100000 +#define DDRMIX_BLK_CTRL_BASE 0x4E010000 + +#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) +#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) +#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) +#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114) +#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) +#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) +#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) + +#define SRC_BASE_ADDR (0x44460000) +#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) +#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20) +#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24) + +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + (X * 0x2000000)) +#define DDRPHY_MEM(X) (DDR_PHY_BASE + (X * 0x2000000) + 0x50000) + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +int ddr_init(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); +void board_dram_ecc_scrub(void); +void ddrc_inline_ecc_scrub(unsigned int start_address, + unsigned int range_address); +void ddrc_inline_ecc_scrub_end(unsigned int start_address, + unsigned int range_address); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +void get_trained_CDD(unsigned int fsp); + +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +#endif diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h new file mode 100644 index 0000000000..599f7511c3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_GPIO_H +#define __ASM_ARCH_IMX9_GPIO_H + +#include <common.h> + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_pidr; + u8 gpio_pxdr[32]; +}; + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h new file mode 100644 index 0000000000..593409c30c --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_REGS_H__ +#define __ASM_ARCH_IMX9_REGS_H__ + +#define ARCH_MXC +#define FEC_QUIRK_ENET_MAC + +#define IOMUXC_BASE_ADDR 0x443C0000UL +#define CCM_BASE_ADDR 0x44450000UL +#define CCM_CCGR_BASE_ADDR 0x44458000UL +#define SYSCNT_CTRL_BASE_ADDR 0x44290000 + +#define WDG3_BASE_ADDR 0x42490000UL +#define WDG4_BASE_ADDR 0x424a0000UL +#define WDG5_BASE_ADDR 0x424b0000UL + +#define ANATOP_BASE_ADDR 0x44480000UL + +#define USB1_BASE_ADDR 0x4c100000 +#define USB2_BASE_ADDR 0x4c200000 + +#define USB_BASE_ADDR USB1_BASE_ADDR + +#define FSB_BASE_ADDR 0x47510000 + +#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000 +#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000 + +#define SRC_IPS_BASE_ADDR (0x44460000) +#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x0000) + +#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000) +#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800) +#define SRC_MEDIA_RBASE (SRC_IPS_BASE_ADDR + 0x2400) +#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800) + +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0) +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2) +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4) +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12) + +#define IMG_CONTAINER_BASE (0x80000000UL) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#include <stdbool.h> + +#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) +#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + +#define BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK BIT(2) + +enum mix_power_domain { + MIX_PD_MEDIAMIX, + MIX_PD_MLMIX, + MIX_PD_DDRMIX, +}; + +enum src_mix_slice_id { + SRC_MIX_EDGELOCK = 0, + SRC_MIX_AONMIX = 1, + SRC_MIX_WAKEUPMIX = 2, + SRC_MIX_DDRMIX = 3, + SRC_MIX_DDRPHY = 4, + SRC_MIX_ML = 5, + SRC_MIX_NIC = 6, + SRC_MIX_HSIO = 7, + SRC_MIX_MEDIA = 8, + SRC_MIX_CM33 = 9, + SRC_MIX_CA55C0 = 10, + SRC_MIX_CA55C1 = 11, + SRC_MIX_CA55CLUSTER = 12, +}; + +enum src_mem_slice_id { + SRC_MEM_AONMIX = 0, + SRC_MEM_WAKEUPMIX = 1, + SRC_MEM_DDRMIX = 2, + SRC_MEM_DDRPHY = 3, + SRC_MEM_ML = 4, + SRC_MEM_NIC = 5, + SRC_MEM_OCRAM = 6, + SRC_MEM_HSIO = 7, + SRC_MEM_MEDIA = 8, + SRC_MEM_CA55C0 = 9, + SRC_MEM_CA55C1 = 10, + SRC_MEM_CA55CLUSTER = 11, + SRC_MEM_L3 = 12, +}; + +struct blk_ctrl_s_aonmix_regs { + u32 cm33_irq_mask[7]; + u32 initnsvtor; + u32 reserved1[8]; + u32 ca55_irq_mask[7]; + u32 initsvtor; + u32 m33_cfg; + u32 reserved2[11]; + u32 axbs_aon_ctrl; + u32 reserved3[27]; + u32 dap_access_stkybit; + u32 reserved4[3]; + u32 lp_handshake[2]; + u32 ca55_cpuwait; + u32 ca55_rvbaraddr0_l; + u32 ca55_rvbaraddr0_h; + u32 ca55_rvbaraddr1_l; + u32 ca55_rvbaraddr1_h; + u32 s401_irq_mask; + u32 s401_reset_req_mask; + u32 s401_halt_st; + u32 ca55_mode; + u32 nmi_mask; + u32 nmi_clr; + u32 wdog_any_mask; + u32 s4v1_ipi_noclk_ref1; +}; + +struct blk_ctrl_wakeupmix_regs { + u32 upper_addr; + u32 ipg_debug_cm33; + u32 reserved[2]; + u32 qch_dis; + u32 ssi; + u32 reserved1[1]; + u32 dexsc_err; + u32 mqs_setting; + u32 sai_clk_sel; + u32 eqos_gpr; + u32 enet_clk_sel; + u32 reserved2[1]; + u32 volt_detect; + u32 i3c2_wakeup; + u32 ipg_debug_ca55c0; + u32 ipg_debug_ca55c1; + u32 axi_attr_cfg; + u32 i3c2_sda_irq; +}; + +struct mu_type { + u32 ver; + u32 par; + u32 cr; + u32 sr; + u32 reserved0[60]; + u32 fcr; + u32 fsr; + u32 reserved1[2]; + u32 gier; + u32 gcr; + u32 gsr; + u32 reserved2; + u32 tcr; + u32 tsr; + u32 rcr; + u32 rsr; + u32 reserved3[52]; + u32 tr[16]; + u32 reserved4[16]; + u32 rr[16]; + u32 reserved5[14]; + u32 mu_attr; +}; + +struct src_general_regs { + u32 reserved[1]; + u32 authen_ctrl; + u32 reserved1[2]; + u32 scr; + u32 srtmr; + u32 srmask; + u32 reserved2[1]; + u32 srmr[6]; + u32 reserved3[2]; + u32 sbmr[2]; + u32 reserved4[2]; + u32 srsr; + u32 gpr[19]; + u32 reserved5[24]; + u32 gpr20; + u32 cm_quiesce; + u32 cold_reset_ssar_ack_ctrl; + u32 sp_iso_ctrl; + u32 rom_lp_ctrl; + u32 a55_deny_stat; +}; + +struct src_mem_slice_regs { + u32 reserved[1]; + u32 mem_ctrl; + u32 memlp_ctrl_0; + u32 reserved1[1]; + u32 memlp_ctrl_1; + u32 memlp_ctrl_2; + u32 mem_stat; +}; + +struct src_mix_slice_regs { + u32 reserved[1]; + u32 authen_ctrl; + u32 reserved1[2]; + u32 lpm_setting[3]; + u32 reserved2[1]; + u32 slice_sw_ctrl; + u32 single_reset_sw_ctrl; + u32 reserved3[6]; + u32 a55_hdsk_ack_ctrl; + u32 a55_hdsk_ack_stat; + u32 reserved4[2]; + u32 ssar_ack_ctrl; + u32 ssar_ack_stat; + u32 reserved5[1]; + u32 iso_off_dly_por; + u32 iso_on_dly; + u32 iso_off_dly; + u32 psw_off_lf_dly; + u32 reserved6[1]; + u32 psw_off_hf_dly; + u32 psw_on_lf_dly; + u32 psw_on_hf_dly; + u32 reserved7[1]; + u32 psw_ack_ctrl[2]; + u32 psw_ack_stat; + u32 reserved8[1]; + u32 mtr_ack_ctrl; + u32 mtr_ack_stat; + u32 reserved9[2]; + u32 upi_stat[4]; + u32 fsm_stat; + u32 func_stat; +}; + +bool is_usb_boot(void); +void disconnect_from_pc(void); +#define is_boot_from_usb is_usb_boot + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h new file mode 100644 index 0000000000..ae0eaa8354 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX93_PINS_H__ +#define __ASM_ARCH_IMX93_PINS_H__ + +#include <asm/mach-imx/iomux-v3.h> + +enum { + MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x01B0, 0x0000, 0, 0x03D8, 0, 0), + MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x01B0, 0x0000, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x01B0, 0x0000, 3, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x01B0, 0x0000, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x01B0, 0x0000, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x01B0, 0x0000, 6, 0x0430, 0, 0), + + MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x01B4, 0x0004, 0, 0x03DC, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x01B4, 0x0004, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x01B4, 0x0004, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x01B4, 0x0004, 6, 0x0000, 0, 0), + + MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x01B8, 0x0008, 0, 0x03D4, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x01B8, 0x0008, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x01B8, 0x0008, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x01B8, 0x0008, 6, 0x042C, 0, 0), + + MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x01BC, 0x000C, 0, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x01BC, 0x000C, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x01BC, 0x000C, 3, 0x0364, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x01BC, 0x000C, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x01BC, 0x000C, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x01BC, 0x000C, 6, 0x0434, 0, 0), + + MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x01C0, 0x0010, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x01C0, 0x0010, 1 | IOMUX_CONFIG_SION, 0x03E4, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x01C0, 0x0010, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x01C0, 0x0010, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x01C0, 0x0010, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x01C0, 0x0010, 5, 0x0434, 1, 0), + MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x01C0, 0x0010, 6 | IOMUX_CONFIG_SION, 0x03EC, 0, 0), + MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x01C0, 0x0010, 7, 0x036C, 0, 0), + + MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x01C4, 0x0014, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x01C4, 0x0014, 1 | IOMUX_CONFIG_SION, 0x03E0, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x01C4, 0x0014, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x01C4, 0x0014, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x01C4, 0x0014, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x01C4, 0x0014, 5, 0x0430, 1, 0), + MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x01C4, 0x0014, 6 | IOMUX_CONFIG_SION, 0x03E8, 0, 0), + MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x01C4, 0x0014, 7, 0x0370, 0, 0), + + MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x01C8, 0x0018, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x01C8, 0x0018, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x01C8, 0x0018, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x01C8, 0x0018, 5, 0x042C, 1, 0), + MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x01C8, 0x0018, 6 | IOMUX_CONFIG_SION, 0x03F4, 0, 0), + MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x01C8, 0x0018, 7, 0x0374, 0, 0), + + MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x01CC, 0x001C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x01CC, 0x001C, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x01CC, 0x001C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x01CC, 0x001C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x01CC, 0x001C, 6 | IOMUX_CONFIG_SION, 0x03F0, 0, 0), + MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x01CC, 0x001C, 7, 0x0378, 0, 0), + + MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x01D0, 0x0020, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x01D0, 0x0020, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x01D0, 0x0020, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x01D0, 0x0020, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x01D0, 0x0020, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x01D0, 0x0020, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x01D0, 0x0020, 6 | IOMUX_CONFIG_SION, 0x03F4, 1, 0), + MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x01D0, 0x0020, 7, 0x037C, 0, 0), + + MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x01D4, 0x0024, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x01D4, 0x0024, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 = IOMUX_PAD(0x01D4, 0x0024, 2, 0x0438, 0, 0), + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x01D4, 0x0024, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x01D4, 0x0024, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x01D4, 0x0024, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x01D4, 0x0024, 6 | IOMUX_CONFIG_SION, 0x03F0, 1, 0), + MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x01D4, 0x0024, 7, 0x0380, 0, 0), + + MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x01D8, 0x0028, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x01D8, 0x0028, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 = IOMUX_PAD(0x01D8, 0x0028, 2, 0x043C, 0, 0), + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x01D8, 0x0028, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x01D8, 0x0028, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x01D8, 0x0028, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x01D8, 0x0028, 6 | IOMUX_CONFIG_SION, 0x03FC, 0, 0), + MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x01D8, 0x0028, 7, 0x0384, 0, 0), + + MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x01DC, 0x002C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x01DC, 0x002C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 = IOMUX_PAD(0x01DC, 0x002C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x01DC, 0x002C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x01DC, 0x002C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x01DC, 0x002C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x01DC, 0x002C, 6 | IOMUX_CONFIG_SION, 0x03F8, 0, 0), + MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x01DC, 0x002C, 7, 0x0388, 0, 0), + + MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x01E0, 0x0030, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x01E0, 0x0030, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 = IOMUX_PAD(0x01E0, 0x0030, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x01E0, 0x0030, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x01E0, 0x0030, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x01E0, 0x0030, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x01E0, 0x0030, 6 | IOMUX_CONFIG_SION, 0x03FC, 1, 0), + MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x01E0, 0x0030, 7, 0x038C, 0, 0), + + MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x01E4, 0x0034, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x01E4, 0x0034, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 = IOMUX_PAD(0x01E4, 0x0034, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x01E4, 0x0034, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x01E4, 0x0034, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x01E4, 0x0034, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x01E4, 0x0034, 6 | IOMUX_CONFIG_SION, 0x03F8, 1, 0), + MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x01E4, 0x0034, 7, 0x0390, 0, 0), + + MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x01E8, 0x0038, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x01E8, 0x0038, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 = IOMUX_PAD(0x01E8, 0x0038, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x01E8, 0x0038, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x01E8, 0x0038, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x01E8, 0x0038, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x01E8, 0x0038, 6 | IOMUX_CONFIG_SION, 0x0404, 0, 0), + MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x01E8, 0x0038, 7, 0x0394, 0, 0), + + MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x01EC, 0x003C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x01EC, 0x003C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 = IOMUX_PAD(0x01EC, 0x003C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x01EC, 0x003C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x01EC, 0x003C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x01EC, 0x003C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x01EC, 0x003C, 6 | IOMUX_CONFIG_SION, 0x0400, 0, 0), + MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x01EC, 0x003C, 7, 0x0398, 0, 0), + + MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x01F0, 0x0040, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x01F0, 0x0040, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 = IOMUX_PAD(0x01F0, 0x0040, 2, 0x0440, 0, 0), + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x01F0, 0x0040, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x01F0, 0x0040, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x01F0, 0x0040, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x01F0, 0x0040, 6 | IOMUX_CONFIG_SION, 0x0404, 1, 0), + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x01F0, 0x0040, 7, 0x0450, 0, 0), + + MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x01F4, 0x0044, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x01F4, 0x0044, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 = IOMUX_PAD(0x01F4, 0x0044, 2, 0x0444, 0, 0), + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x01F4, 0x0044, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x01F4, 0x0044, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x01F4, 0x0044, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x01F4, 0x0044, 6 | IOMUX_CONFIG_SION, 0x0400, 1, 0), + MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x01F4, 0x0044, 7, 0x039C, 0, 0), + + MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x01F8, 0x0048, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x01F8, 0x0048, 1, 0x041C, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 = IOMUX_PAD(0x01F8, 0x0048, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x01F8, 0x0048, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x01F8, 0x0048, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x01F8, 0x0048, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x01F8, 0x0048, 6, 0x0428, 0, 0), + MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x01F8, 0x0048, 7, 0x03A0, 0, 0), + + MX93_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x01FC, 0x004C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x01FC, 0x004C, 1, 0x0418, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 = IOMUX_PAD(0x01FC, 0x004C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x01FC, 0x004C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x01FC, 0x004C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x01FC, 0x004C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x01FC, 0x004C, 6, 0x0424, 0, 0), + MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x01FC, 0x004C, 7, 0x03A4, 0, 0), + + MX93_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x0200, 0x0050, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x0200, 0x0050, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 = IOMUX_PAD(0x0200, 0x0050, 2, 0x0440, 1, 0), + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x0200, 0x0050, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x0200, 0x0050, 4, 0x0414, 0, 0), + MX93_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x0200, 0x0050, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x0200, 0x0050, 6, 0x0420, 0, 0), + MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x0200, 0x0050, 7, 0x03A8, 0, 0), + + MX93_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x0204, 0x0054, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x0204, 0x0054, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 = IOMUX_PAD(0x0204, 0x0054, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x0204, 0x0054, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x0204, 0x0054, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x0204, 0x0054, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x0204, 0x0054, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x0204, 0x0054, 7, 0x03AC, 0, 0), + + MX93_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x0208, 0x0058, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x0208, 0x0058, 1, 0x044C, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 = IOMUX_PAD(0x0208, 0x0058, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x0208, 0x0058, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x0208, 0x0058, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x0208, 0x0058, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x0208, 0x0058, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x0208, 0x0058, 7, 0x03B0, 0, 0), + + MX93_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x020C, 0x005C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x020C, 0x005C, 1, 0x0450, 1, 0), + MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 = IOMUX_PAD(0x020C, 0x005C, 2, 0x0444, 1, 0), + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x020C, 0x005C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x020C, 0x005C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x020C, 0x005C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x020C, 0x005C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 = IOMUX_PAD(0x020C, 0x005C, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x0210, 0x0060, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 = IOMUX_PAD(0x0210, 0x0060, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 = IOMUX_PAD(0x0210, 0x0060, 2, 0x0438, 1, 0), + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x0210, 0x0060, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x0210, 0x0060, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x0210, 0x0060, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x0210, 0x0060, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x0210, 0x0060, 7, 0x03B4, 0, 0), + + MX93_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x0214, 0x0064, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 = IOMUX_PAD(0x0214, 0x0064, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x0214, 0x0064, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x0214, 0x0064, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x0214, 0x0064, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x0214, 0x0064, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x0214, 0x0064, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x0214, 0x0064, 7, 0x044C, 1, 0), + + MX93_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x0218, 0x0068, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x0218, 0x0068, 1, 0x0458, 0, 0), + MX93_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x0218, 0x0068, 2, 0x0454, 0, 0), + MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x0218, 0x0068, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x0218, 0x0068, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x0218, 0x0068, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x0218, 0x0068, 6 | IOMUX_CONFIG_SION, 0x03EC, 1, 0), + MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x0218, 0x0068, 7, 0x03B8, 0, 0), + + MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x021C, 0x006C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x021C, 0x006C, 1, 0x045C, 0, 0), + MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x021C, 0x006C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x021C, 0x006C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x021C, 0x006C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x021C, 0x006C, 6 | IOMUX_CONFIG_SION, 0x03E8, 1, 0), + MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x021C, 0x006C, 7, 0x03BC, 0, 0), + + MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x0220, 0x0070, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x0220, 0x0070, 1, 0x0460, 0, 0), + MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x0220, 0x0070, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x0220, 0x0070, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x0220, 0x0070, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x0220, 0x0070, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x0220, 0x0070, 7, 0x03C0, 0, 0), + + MX93_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x0224, 0x0074, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x0224, 0x0074, 1, 0x0464, 0, 0), + MX93_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x0224, 0x0074, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x0224, 0x0074, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x0224, 0x0074, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x0224, 0x0074, 5, 0x03D4, 1, 0), + MX93_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x0224, 0x0074, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x0224, 0x0074, 7, 0x03C4, 0, 0), + + MX93_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x0228, 0x0078, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x0228, 0x0078, 1, 0x0468, 0, 0), + MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 = IOMUX_PAD(0x0228, 0x0078, 2, 0x043C, 1, 0), + MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x0228, 0x0078, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x0228, 0x0078, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x0228, 0x0078, 5, 0x03D8, 1, 0), + MX93_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x0228, 0x0078, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x0228, 0x0078, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x022C, 0x007C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x022C, 0x007C, 1, 0x046C, 0, 0), + MX93_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x022C, 0x007C, 2, 0x0364, 1, 0), + MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x022C, 0x007C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x022C, 0x007C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x022C, 0x007C, 5, 0x03DC, 1, 0), + MX93_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x022C, 0x007C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x022C, 0x007C, 7, 0x03C8, 0, 0), + + MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x0230, 0x0080, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x0230, 0x0080, 1 | IOMUX_CONFIG_SION, 0x03E4, 1, 0), + MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x0230, 0x0080, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x0234, 0x0084, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x0234, 0x0084, 1 | IOMUX_CONFIG_SION, 0x03E0, 1, 0), + MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x0234, 0x0084, 7, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0238, 0x0088, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x0238, 0x0088, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x0238, 0x0088, 5, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x023C, 0x008C, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x023C, 0x008C, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x023C, 0x008C, 4, 0x03C8, 1, 0), + + MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x0240, 0x0090, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x0240, 0x0090, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x0240, 0x0090, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x0244, 0x0094, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x0244, 0x0094, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x0244, 0x0094, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDC__ENET_QOS_MDC = IOMUX_PAD(0x0248, 0x0098, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x0248, 0x0098, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x0248, 0x0098, 2 | IOMUX_CONFIG_SION, 0x03CC, 0, 0), + MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x0248, 0x0098, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 = IOMUX_PAD(0x0248, 0x0098, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__GPIO4_IO00 = IOMUX_PAD(0x0248, 0x0098, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x024C, 0x009C, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x024C, 0x009C, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x024C, 0x009C, 2 | IOMUX_CONFIG_SION, 0x03D0, 0, 0), + MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x024C, 0x009C, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 = IOMUX_PAD(0x024C, 0x009C, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__GPIO4_IO01 = IOMUX_PAD(0x024C, 0x009C, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x0250, 0x00A0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 = IOMUX_PAD(0x0250, 0x00A0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__GPIO4_IO02 = IOMUX_PAD(0x0250, 0x00A0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x0254, 0x00A4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x0254, 0x00A4, 2, 0x0364, 2, 0), + MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x0254, 0x00A4, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 = IOMUX_PAD(0x0254, 0x00A4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__GPIO4_IO03 = IOMUX_PAD(0x0254, 0x00A4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x0258, 0x00A8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x0258, 0x00A8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x0258, 0x00A8, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x0258, 0x00A8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 = IOMUX_PAD(0x0258, 0x00A8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__GPIO4_IO04 = IOMUX_PAD(0x0258, 0x00A8, 5, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x0258, 0x00A8, 6, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x025C, 0x00AC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x025C, 0x00AC, 1, 0x041C, 1, 0), + MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 = IOMUX_PAD(0x025C, 0x00AC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__GPIO4_IO05 = IOMUX_PAD(0x025C, 0x00AC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x0260, 0x00B0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x0260, 0x00B0, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 = IOMUX_PAD(0x0260, 0x00B0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 = IOMUX_PAD(0x0260, 0x00B0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x0264, 0x00B4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x0264, 0x00B4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 = IOMUX_PAD(0x0264, 0x00B4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__GPIO4_IO07 = IOMUX_PAD(0x0264, 0x00B4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x0268, 0x00B8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x0268, 0x00B8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x0268, 0x00B8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 = IOMUX_PAD(0x0268, 0x00B8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 = IOMUX_PAD(0x0268, 0x00B8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x026C, 0x00BC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x026C, 0x00BC, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 = IOMUX_PAD(0x026C, 0x00BC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__GPIO4_IO09 = IOMUX_PAD(0x026C, 0x00BC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x0270, 0x00C0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x0270, 0x00C0, 1, 0x0418, 1, 0), + MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x0270, 0x00C0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x0270, 0x00C0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x0274, 0x00C4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x0274, 0x00C4, 1, 0x0414, 1, 0), + MX93_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x0274, 0x00C4, 3, 0x0408, 0, 0), + MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x0274, 0x00C4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x0274, 0x00C4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x0278, 0x00C8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x0278, 0x00C8, 3, 0x040C, 0, 0), + MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x0278, 0x00C8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x0278, 0x00C8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x027C, 0x00CC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x027C, 0x00CC, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x027C, 0x00CC, 3, 0x0410, 0, 0), + MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x027C, 0x00CC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x027C, 0x00CC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDC__ENET1_MDC = IOMUX_PAD(0x0280, 0x00D0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x0280, 0x00D0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x0280, 0x00D0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x0280, 0x00D0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x0280, 0x00D0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDIO__ENET1_MDIO = IOMUX_PAD(0x0284, 0x00D4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x0284, 0x00D4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x0284, 0x00D4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x0284, 0x00D4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x0284, 0x00D4, 5, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 = IOMUX_PAD(0x0288, 0x00D8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x0288, 0x00D8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x0288, 0x00D8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x0288, 0x00D8, 0, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x028C, 0x00DC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__ENET1_TX_CLK = IOMUX_PAD(0x028C, 0x00DC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 = IOMUX_PAD(0x028C, 0x00DC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x028C, 0x00DC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x028C, 0x00DC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x0290, 0x00E0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x0290, 0x00E0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 = IOMUX_PAD(0x0290, 0x00E0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x0290, 0x00E0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x0290, 0x00E0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x0294, 0x00E4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x0294, 0x00E4, 1, 0x0428, 1, 0), + MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 = IOMUX_PAD(0x0294, 0x00E4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x0294, 0x00E4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x0294, 0x00E4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0298, 0x00E8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x0298, 0x00E8, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x0298, 0x00E8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x0298, 0x00E8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x0298, 0x00E8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x029C, 0x00EC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__ENET1_TX_ER = IOMUX_PAD(0x029C, 0x00EC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x029C, 0x00EC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x029C, 0x00EC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x029C, 0x00EC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02A0, 0x00F0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x02A0, 0x00F0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 = IOMUX_PAD(0x02A0, 0x00F0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x02A0, 0x00F0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x02A0, 0x00F0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x02A4, 0x00F4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__ENET1_RX_ER = IOMUX_PAD(0x02A4, 0x00F4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 = IOMUX_PAD(0x02A4, 0x00F4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x02A4, 0x00F4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x02A4, 0x00F4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x02A8, 0x00F8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x02A8, 0x00F8, 1, 0x0424, 1, 0), + MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 = IOMUX_PAD(0x02A8, 0x00F8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x02A8, 0x00F8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x02A8, 0x00F8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x02AC, 0x00FC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x02AC, 0x00FC, 1, 0x0454, 1, 0), + MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 = IOMUX_PAD(0x02AC, 0x00FC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x02AC, 0x00FC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x02AC, 0x00FC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x02B0, 0x0100, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x02B0, 0x0100, 1, 0x0420, 1, 0), + MX93_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x02B0, 0x0100, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x02B0, 0x0100, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x02B0, 0x0100, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x02B0, 0x0100, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x02B4, 0x0104, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x02B4, 0x0104, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x02B4, 0x0104, 2, 0x0454, 2, 0), + MX93_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x02B4, 0x0104, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x02B4, 0x0104, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x02B4, 0x0104, 5, 0x0000, 0, 0), + MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x02B8, 0x0108, 4, 0x038C, 1, 0), + MX93_PAD_SD1_CLK__GPIO3_IO08 = IOMUX_PAD(0x02B8, 0x0108, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02B8, 0x0108, 0, 0x0000, 0, 0), + + MX93_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02BC, 0x010C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x02BC, 0x010C, 4, 0x0390, 1, 0), + MX93_PAD_SD1_CMD__GPIO3_IO09 = IOMUX_PAD(0x02BC, 0x010C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02C0, 0x0110, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x02C0, 0x0110, 4, 0x0394, 1, 0), + MX93_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x02C0, 0x0110, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02C4, 0x0114, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x02C4, 0x0114, 4, 0x0398, 1, 0), + MX93_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x02C4, 0x0114, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02C4, 0x0114, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02C8, 0x0118, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x02C8, 0x0118, 4, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x02C8, 0x0118, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02C8, 0x0118, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x02CC, 0x011C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x02CC, 0x011C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x02CC, 0x011C, 4, 0x039C, 1, 0), + MX93_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x02CC, 0x011C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 = IOMUX_PAD(0x02D0, 0x0120, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x02D0, 0x0120, 4, 0x03A0, 1, 0), + MX93_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x02D0, 0x0120, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 = IOMUX_PAD(0x02D4, 0x0124, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x02D4, 0x0124, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x02D4, 0x0124, 4, 0x03A4, 1, 0), + MX93_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x02D4, 0x0124, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 = IOMUX_PAD(0x02D8, 0x0128, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x02D8, 0x0128, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x02D8, 0x0128, 4, 0x03A8, 1, 0), + MX93_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x02D8, 0x0128, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 = IOMUX_PAD(0x02DC, 0x012C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x02DC, 0x012C, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x02DC, 0x012C, 4, 0x03AC, 1, 0), + MX93_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x02DC, 0x012C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x02E0, 0x0130, 0, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x02E0, 0x0130, 1, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x02E0, 0x0130, 4, 0x03B0, 1, 0), + MX93_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x02E0, 0x0130, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x02E4, 0x0134, 0, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x02E4, 0x0134, 1, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x02E4, 0x0134, 2, 0x0410, 1, 0), + MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x02E4, 0x0134, 4, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x02E4, 0x0134, 5, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x02E4, 0x0134, 6, 0x0368, 0, 0), + + MX93_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x02E8, 0x0138, 0, 0x0458, 1, 0), + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x02E8, 0x0138, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x02E8, 0x0138, 4, 0x03B4, 1, 0), + MX93_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x02E8, 0x0138, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x02EC, 0x013C, 0, 0x045C, 1, 0), + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x02EC, 0x013C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x02EC, 0x013C, 4, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x02EC, 0x013C, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0, 0x0460, 1, 0), + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 = IOMUX_PAD(0x02F0, 0x0140, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x02F0, 0x0140, 4, 0x03B8, 1, 0), + MX93_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x02F0, 0x0140, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0, 0x0464, 1, 0), + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 = IOMUX_PAD(0x02F4, 0x0144, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x02F4, 0x0144, 4, 0x03BC, 1, 0), + MX93_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x02F4, 0x0144, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0, 0x0468, 1, 0), + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 = IOMUX_PAD(0x02F8, 0x0148, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x02F8, 0x0148, 4, 0x03C0, 1, 0), + MX93_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x02F8, 0x0148, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0, 0x046C, 1, 0), + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 = IOMUX_PAD(0x02FC, 0x014C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x02FC, 0x014C, 4, 0x03C4, 1, 0), + MX93_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x02FC, 0x014C, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0300, 0x0150, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0300, 0x0150, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x0300, 0x0150, 2 | IOMUX_CONFIG_SION, 0x03CC, 1, 0), + MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x0300, 0x0150, 4, 0x036C, 1, 0), + MX93_PAD_SD2_CD_B__GPIO3_IO00 = IOMUX_PAD(0x0300, 0x0150, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0304, 0x0154, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0304, 0x0154, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x0304, 0x0154, 2 | IOMUX_CONFIG_SION, 0x03D0, 1, 0), + MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x0304, 0x0154, 4, 0x0370, 1, 0), + MX93_PAD_SD2_CLK__GPIO3_IO01 = IOMUX_PAD(0x0304, 0x0154, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0304, 0x0154, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0308, 0x0158, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x0308, 0x0158, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x0308, 0x0158, 2, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x0308, 0x0158, 3, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x0308, 0x0158, 4, 0x0374, 1, 0), + MX93_PAD_SD2_CMD__GPIO3_IO02 = IOMUX_PAD(0x0308, 0x0158, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0308, 0x0158, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x030C, 0x015C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x030C, 0x015C, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x030C, 0x015C, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x030C, 0x015C, 4, 0x0378, 1, 0), + MX93_PAD_SD2_DATA0__GPIO3_IO03 = IOMUX_PAD(0x030C, 0x015C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x030C, 0x015C, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0310, 0x0160, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0310, 0x0160, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x0310, 0x0160, 2, 0x0364, 3, 0), + MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x0310, 0x0160, 4, 0x037C, 1, 0), + MX93_PAD_SD2_DATA1__GPIO3_IO04 = IOMUX_PAD(0x0310, 0x0160, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0310, 0x0160, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0314, 0x0164, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0314, 0x0164, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x0314, 0x0164, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x0314, 0x0164, 4, 0x0380, 1, 0), + MX93_PAD_SD2_DATA2__GPIO3_IO05 = IOMUX_PAD(0x0314, 0x0164, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0314, 0x0164, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0318, 0x0168, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x0318, 0x0168, 1, 0x0408, 1, 0), + MX93_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x0318, 0x0168, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x0318, 0x0168, 4, 0x0384, 1, 0), + MX93_PAD_SD2_DATA3__GPIO3_IO06 = IOMUX_PAD(0x0318, 0x0168, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0318, 0x0168, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x031C, 0x016C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x031C, 0x016C, 1, 0x040C, 1, 0), + MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x031C, 0x016C, 4, 0x0388, 1, 0), + MX93_PAD_SD2_RESET_B__GPIO3_IO07 = IOMUX_PAD(0x031C, 0x016C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x031C, 0x016C, 6, 0x0000, 0, 0), + + MX93_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x0320, 0x0170, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x0320, 0x0170, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x0320, 0x0170, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__GPIO1_IO00 = IOMUX_PAD(0x0320, 0x0170, 5, 0x0000, 0, 0), + + MX93_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x0324, 0x0174, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x0324, 0x0174, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x0324, 0x0174, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__GPIO1_IO01 = IOMUX_PAD(0x0324, 0x0174, 5, 0x0000, 0, 0), + + MX93_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x0328, 0x0178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x0328, 0x0178, 1, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__GPIO1_IO02 = IOMUX_PAD(0x0328, 0x0178, 5, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 6, 0x0000, 0, 0), + + MX93_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x032C, 0x017C, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x032C, 0x017C, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x032C, 0x017C, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__GPIO1_IO03 = IOMUX_PAD(0x032C, 0x017C, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x0330, 0x0180, 0, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__S400_UART_RX = IOMUX_PAD(0x0330, 0x0180, 1, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x0330, 0x0180, 2, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x0330, 0x0180, 3, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__GPIO1_IO04 = IOMUX_PAD(0x0330, 0x0180, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x0334, 0x0184, 0, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__S400_UART_TX = IOMUX_PAD(0x0334, 0x0184, 1, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x0334, 0x0184, 2, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x0334, 0x0184, 3, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__GPIO1_IO05 = IOMUX_PAD(0x0334, 0x0184, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x0338, 0x0188, 0, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x0338, 0x0188, 1, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x0338, 0x0188, 2, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x0338, 0x0188, 3, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x0338, 0x0188, 4, 0x0448, 0, 0), + MX93_PAD_UART2_RXD__GPIO1_IO06 = IOMUX_PAD(0x0338, 0x0188, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x033C, 0x018C, 0, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x033C, 0x018C, 1, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x033C, 0x018C, 2, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x033C, 0x018C, 3, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__GPIO1_IO07 = IOMUX_PAD(0x033C, 0x018C, 5, 0x0000, 0, 0), + + MX93_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x0340, 0x0190, 0, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x0340, 0x0190, 1, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x0340, 0x0190, 4, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__GPIO1_IO08 = IOMUX_PAD(0x0340, 0x0190, 5, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x0340, 0x0190, 6, 0x0000, 0, 0), + + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 = IOMUX_PAD(0x0344, 0x0194, 0, 0x0438, 2, 0), + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x0344, 0x0194, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x0344, 0x0194, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x0344, 0x0194, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x0344, 0x0194, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 = IOMUX_PAD(0x0344, 0x0194, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x0344, 0x0194, 6, 0x0360, 0, 0), + + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 = IOMUX_PAD(0x0348, 0x0198, 0, 0x043C, 2, 0), + MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI = IOMUX_PAD(0x0348, 0x0198, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x0348, 0x0198, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x0348, 0x0198, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x0348, 0x0198, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x0348, 0x0198, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0348, 0x0198, 6, 0x0368, 1, 0), + + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x034C, 0x019C, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 = IOMUX_PAD(0x034C, 0x019C, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x034C, 0x019C, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x034C, 0x019C, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x034C, 0x019C, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x034C, 0x019C, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x0350, 0x01A0, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x0350, 0x01A0, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x0350, 0x01A0, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x0350, 0x01A0, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x0350, 0x01A0, 4, 0x0360, 1, 0), + MX93_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x0350, 0x01A0, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 = IOMUX_PAD(0x0354, 0x01A4, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x0354, 0x01A4, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x0354, 0x01A4, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x0354, 0x01A4, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x0354, 0x01A4, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x0354, 0x01A4, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 = IOMUX_PAD(0x0358, 0x01A8, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x0358, 0x01A8, 1, 0x0448, 1, 0), + MX93_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x0358, 0x01A8, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x0358, 0x01A8, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x0358, 0x01A8, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x0358, 0x01A8, 5, 0x0000, 0, 0), + + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x01AC, 0, 0x0000, 0, 0), + MX93_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x035C, 0x01AC, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX93_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h new file mode 100644 index 0000000000..292635982f --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 NXP + */ + +#ifndef __ARCH_IMX9_SYS_PROTO_H +#define __ARCH_NMX9_SYS_PROTO_H + +#include <asm/mach-imx/sys_proto.h> + +ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf); +ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); +extern unsigned long rom_pointer[]; +enum boot_device get_boot_device(void); +bool is_usb_boot(void); +int mix_power_init(enum mix_power_domain pd); +void soc_power_init(void); +bool m33_is_rom_kicked(void); +int m33_prepare(void); +#endif diff --git a/arch/arm/include/asm/arch-imx9/trdc.h b/arch/arm/include/asm/arch-imx9/trdc.h new file mode 100644 index 0000000000..7c984d9ce9 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/trdc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_TRDC_H +#define __ASM_ARCH_IMX9_TRDC_H + +int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, + u32 glbac_id, u32 glbac_val); +int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, + u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id); +int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, + u32 glbac_id, u32 glbac_val); +int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, + u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id); + +void trdc_early_init(void); +void trdc_init(void); + +#endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 085e12b5d4..8d25c32c3a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -90,10 +90,16 @@ struct arch_global_data { struct udevice *scu_dev; #endif -#ifdef CONFIG_ARCH_IMX8ULP +#ifdef CONFIG_IMX_SENTINEL struct udevice *s400_dev; + u32 soc_rev; + u32 lifecycle; + u32 uid[4]; #endif +#ifdef CONFIG_ARCH_IMX8ULP + bool m33_handshake_done; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index dcf9bd8966..cd2c6e73e0 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_IMX8M +#ifdef CONFIG_IMX93 +#define PAD_CTL_FSEL2 (0x2 << 7) +#define PAD_CTL_FSEL3 (0x3 << 7) +#define PAD_CTL_PUE (0x1 << 9) +#define PAD_CTL_PDE (0x1 << 10) +#define PAD_CTL_ODE (0x1 << 11) +#define PAD_CTL_HYS (0x1 << 12) +#define PAD_CTL_DSE(x) (((x) << 1) & 0x7f) + +#elif defined(CONFIG_IMX8M) #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h index 10d966d5d4..5db559c1ac 100644 --- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h +++ b/arch/arm/include/asm/mach-imx/mu_hal.h @@ -3,8 +3,8 @@ * Copyright 2021 NXP */ -#ifndef __IMX8ULP_MU_HAL_H__ -#define __IMX8ULP_MU_HAL_H__ +#ifndef __SNT_MU_HAL_H__ +#define __SNT_MU_HAL_H__ void mu_hal_init(ulong base); int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg); diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h new file mode 100644 index 0000000000..3862c5a39b --- /dev/null +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __S400_API_H__ +#define __S400_API_H__ + +#define AHAB_VERSION 0x6 +#define AHAB_CMD_TAG 0x17 +#define AHAB_RESP_TAG 0xe1 + +/* ELE commands */ +#define ELE_PING_REQ (0x01) +#define ELE_FW_AUTH_REQ (0x02) +#define ELE_RESTART_RST_TIMER_REQ (0x04) +#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21) +#define ELE_OEM_CNTN_AUTH_REQ (0x87) +#define ELE_VERIFY_IMAGE_REQ (0x88) +#define ELE_RELEASE_CONTAINER_REQ (0x89) +#define ELE_WRITE_SECURE_FUSE_REQ (0x91) +#define ELE_FWD_LIFECYCLE_UP_REQ (0x95) +#define ELE_READ_FUSE_REQ (0x97) +#define ELE_GET_FW_VERSION_REQ (0x9D) +#define ELE_RET_LIFECYCLE_UP_REQ (0xA0) +#define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_START_RNG (0xA3) +#define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_ENABLE_PATCH_REQ (0xC3) +#define ELE_RELEASE_RDC_REQ (0xC4) +#define ELE_GET_FW_STATUS_REQ (0xC5) +#define ELE_ENABLE_OTFAD_REQ (0xC6) +#define ELE_RESET_REQ (0xC7) +#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0) +#define ELE_POWER_DOWN_REQ (0xD1) +#define ELE_ENABLE_APC_REQ (0xD2) +#define ELE_ENABLE_RTC_REQ (0xD3) +#define ELE_DEEP_POWER_DOWN_REQ (0xD4) +#define ELE_STOP_RST_TIMER_REQ (0xD5) +#define ELE_WRITE_FUSE_REQ (0xD6) +#define ELE_RELEASE_CAAM_REQ (0xD7) +#define ELE_RESET_A35_CTX_REQ (0xD8) +#define ELE_MOVE_TO_UNSECURED_REQ (0xD9) +#define ELE_GET_INFO_REQ (0xDA) +#define ELE_ATTEST_REQ (0xDB) +#define ELE_RELEASE_PATCH_REQ (0xDC) +#define ELE_OTP_SEQ_SWITH_REQ (0xDD) + +/* ELE failure indications */ +#define ELE_ROM_PING_FAILURE_IND (0x0A) +#define ELE_FW_PING_FAILURE_IND (0x1A) +#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0) +#define ELE_BAD_HASH_FAILURE_IND (0xF1) +#define ELE_INVALID_LIFECYCLE_IND (0xF2) +#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3) +#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4) +#define ELE_BAD_VALUE_FAILURE_IND (0xF5) +#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6) +#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7) +#define ELE_BAD_VERSION_FAILURE_IND (0xF8) +#define ELE_INVALID_KEY_FAILURE_IND (0xF9) +#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA) +#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB) +#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC) +#define ELE_BAD_UID_FAILURE_IND (0xFD) +#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE) +#define ELE_MUST_SIGNED_FAILURE_IND (0xE0) +#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE) +#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF) +#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6) +#define ELE_WRONG_SIZE_FAILURE_IND (0xA7) +#define ELE_ENCRYPTION_FAILURE_IND (0xA8) +#define ELE_DECRYPTION_FAILURE_IND (0xA9) +#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA) +#define ELE_OTP_LOCKED_FAILURE_IND (0xAB) +#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD) +#define ELE_TIME_OUT_FAILURE_IND (0xB0) +#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1) +#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4) +#define ELE_DMA_FAILURE_IND (0xB5) +#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6) +#define ELE_MUST_ATTEST_FAILURE_IND (0xB7) +#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8) +#define ELE_CRC_ERROR_IND (0xB9) +#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB) +#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC) +#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD) +#define ELE_LOCKED_REG_FAILURE_IND (0xBE) +#define ELE_BAD_ID_FAILURE_IND (0xBF) +#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0) +#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1) +#define ELE_MSG_TRUNCATED_IND (0xC2) +#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3) +#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4) +#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5) +#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6) +#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0) +#define ELE_OUT_OF_MEMORY_IND (0xD1) +#define ELE_CSTM_FAILURE_IND (0xCF) +#define ELE_OLD_VERSION_FAILURE_IND (0xCE) +#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD) +#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB) +#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC) +#define ELE_ABORT_IND (0xFF) + +/* ELE IPC identifier */ +#define ELE_IPC_MU_RTD (0x1) +#define ELE_IPC_MU_APD (0x2) + +/* ELE Status*/ +#define ELE_SUCCESS_IND (0xD6) +#define ELE_FAILURE_IND (0x29) + +#define S400_MAX_MSG 255U + +struct sentinel_msg { + u8 version; + u8 size; + u8 command; + u8 tag; + u32 data[(S400_MAX_MSG - 1U)]; +}; + +struct sentinel_get_info_data{ + u32 hdr; + u32 soc; + u32 lc; + u32 uid[4]; + u32 sha256_rom_patch[8]; + u32 sha_fw[8]; +}; + +int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response); +int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); +int ahab_release_container(u32 *response); +int ahab_verify_image(u32 img_id, u32 *response); +int ahab_forward_lifecycle(u16 life_cycle, u32 *response); +int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); +int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); +int ahab_release_caam(u32 core_did, u32 *response); +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); +int ahab_dump_buffer(u32 *buffer, u32 buffer_length); +int ahab_get_info(struct sentinel_get_info_data *info, u32 *response); +int ahab_get_fw_status(u32 *status, u32 *response); +int ahab_release_m33_trout(void); +int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ahab_start_rng(void); +int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, + u32 max_output_size); +int ahab_write_secure_fuse(ulong signed_msg_blk, u32 *response); + +#endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 593a1cf404..04505d948c 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -32,6 +32,7 @@ struct bd_info; #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imx9() (is_soc_type(MXC_SOC_IMX9)) #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) @@ -83,6 +84,17 @@ struct bd_info; #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL)) +#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ + is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || is_cpu_type(MXC_CPU_IMX9322) || \ + is_cpu_type(MXC_CPU_IMX9321) || is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311)) +#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) +#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) +#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) +#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) +#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) +#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) +#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311)) + #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) @@ -151,7 +163,7 @@ struct rproc_att { u32 size; /* size of reg range */ }; -#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) +#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX9) struct rom_api { u16 ver; u16 tag; @@ -172,6 +184,13 @@ enum boot_dev_type_e { BT_DEV_TYPE_INVALID = 0xFF }; +enum boot_stage_type { + BT_STAGE_PRIMARY = 0x6, + BT_STAGE_SECONDARY = 0x9, + BT_STAGE_RECOVERY = 0xa, + BT_STAGE_USB = 0x5, +}; + #define QUERY_ROM_VER 1 #define QUERY_BT_DEV 2 #define QUERY_PAGE_SZ 3 diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ec0171e0e6..4e982892f8 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -3,6 +3,7 @@ * include/asm-arm/macro.h * * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * Copyright 2022 NXP */ #ifndef __ASM_ARM_MACRO_H__ @@ -356,6 +357,45 @@ lr .req x30 .endm #endif +/* + * Select code when configured for LE. + */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define CPU_LE(code...) +#else +#define CPU_LE(code...) code +#endif + +/* + * Pseudo-ops for PC-relative adr/ldr <reg>, <symbol> where + * <symbol> is within the range +/- 4 GB of the PC. + */ + /* + * @dst: destination register (64 bit wide) + * @sym: name of the symbol + */ + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + /* + * @dst: destination register (32 or 64 bit wide) + * @sym: name of the symbol + * @tmp: optional 64-bit scratch register to be used if <dst> is a + * 32-bit wide register, in which case it cannot be used to hold + * the address + */ + .macro ldr_l, dst, sym, tmp= + .ifb \tmp + adrp \dst, \sym + ldr \dst, [\dst, :lo12:\sym] + .else + adrp \tmp, \sym + ldr \dst, [\tmp, :lo12:\sym] + .endif + .endm + #endif /* CONFIG_ARM64 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index fecc0b6107..3fe77a5e49 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -81,6 +81,14 @@ config IMX_HAB This option enables the support for secure boot (HAB). See doc/imx/habv4/* for more details. +config IMX_SPL_FIT_FDT_SIGNATURE + bool "Enable to verify signature of FIT FDT" + depends on IMX_HAB + depends on ARCH_IMX8M + help + Enable SPL to verify signature of FIT FDT during FIT loading. + This needs additional signing to FIT FDT part. + config CSF_SIZE hex "Maximum size for Command Sequence File (CSF) binary" depends on IMX_HAB @@ -109,6 +117,7 @@ config CMD_DEKBLOB select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M select IMX_SECO_DEK_ENCAP if ARCH_IMX8 + select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and @@ -137,6 +146,12 @@ config IMX_SECO_DEK_ENCAP This enabled the DEK blob encapsulation with the SECO API. This option is only available on imx8. +config IMX_ELE_DEK_ENCAP + bool "Support the DEK blob encapsulation with ELE" + help + This enabled the DEK blob encapsulation with the ELE API. This option + is only available on imx8ulp and imx9. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB @@ -229,7 +244,7 @@ config DDRMC_VF610_CALIBRATION config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" - depends on IMX8MN || IMX8MP || IMX8ULP + depends on IMX8MN || IMX8MP || IMX8ULP || IMX9 config IMX_DCD_ADDR hex "DCD Blocks location on the image" @@ -275,6 +290,7 @@ config ANDROID_SUPPORT select SUPPORT_RAW_INITRD select LIBAVB select AVB_SUPPORT + imply IMX_SPL_FIT_FDT_SIGNATURE config ANDROID_AUTO_SUPPORT bool "Android Automotive features support" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 6dc02efe2c..4ebf95d2b3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,7 +5,7 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610)) obj-y = iomux-v3.o endif @@ -30,12 +30,12 @@ endif obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp imx9)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif -ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp)) +ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp imx9)) obj-y += dt_optee.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) @@ -89,6 +89,10 @@ ifeq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o endif +ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9)) +obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o +endif + PLUGIN = board/$(BOARDDIR)/plugin ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y) @@ -292,6 +296,7 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/ obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ +obj-$(CONFIG_ARCH_IMX9) += imx9/ obj-$(CONFIG_ARCH_IMXRT) += imxrt/ obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 701bf516df..9e69f2c505 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * * Command for encapsulating DEK blob */ @@ -20,6 +21,11 @@ #include <asm/arch/sci/sci.h> #include <asm/mach-imx/image.h> #endif +#ifdef CONFIG_IMX_ELE_DEK_ENCAP +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/image.h> +#endif + #include <cpu_func.h> /** @@ -284,6 +290,84 @@ error: } #endif /* CONFIG_IMX_SECO_DEK_ENCAP */ +#ifdef CONFIG_IMX_ELE_DEK_ENCAP + +#define DEK_BLOB_HDR_SIZE 8 +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_DEK_BLOB 0x01 +#define AHAB_ALG_AES 0x03 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + u8 in_size, out_size; + u8 *src_ptr, *dst_ptr; + struct generate_key_blob_hdr hdr; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = 0x0; + hdr.length_lsb = in_size; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = 0x0; /* Not used by the ELE */ + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Move input key and append blob header */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache */ + flush_dcache_range(src_addr, src_addr + in_size); + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Call ELE */ + if (ahab_generate_dek_blob(0x00, src_addr, dst_addr, out_size)) + return -1; + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + return 0; +} +#endif /* CONFIG_IMX_ELE_DEK_ENCAP */ + /** * do_dek_blob() - Handle the "dek_blob" command-line command * @cmdtp: Command data struct pointer diff --git a/arch/arm/mach-imx/cmd_qspihdr.c b/arch/arm/mach-imx/cmd_qspihdr.c index 6e2758664f..ef4a3cf113 100644 --- a/arch/arm/mach-imx/cmd_qspihdr.c +++ b/arch/arm/mach-imx/cmd_qspihdr.c @@ -235,6 +235,7 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) unsigned long addr; char *endp; void *tmp; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF + QSPI_HDR_TAG_OFF; @@ -266,7 +267,11 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) return 1; } } else { - spi_flash_read(flash, off, 4, &buf); + ret = spi_flash_read(flash, off, 4, &buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } if (buf == tag) { if (flag & FLAG_VERBOSE) @@ -398,6 +403,7 @@ static int do_qspihdr_dump(int argc, char * const argv[]) char *endp; void *tmp; void *buf; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF; @@ -431,7 +437,11 @@ static int do_qspihdr_dump(int argc, char * const argv[]) return 0; } - spi_flash_read(flash, off, HDR_LEN, buf); + ret = spi_flash_read(flash, off, HDR_LEN, buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } hdr_dump(buf); free(buf); diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c new file mode 100644 index 0000000000..192f90e6b1 --- /dev/null +++ b/arch/arm/mach-imx/ele_ahab.c @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/arch-imx/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/image.h> +#include <console.h> +#include <cpu_func.h> +#include <asm/mach-imx/ahab.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) + +#define AHAB_MAX_EVENTS 8 + +static char *ele_ipc_str[] = { + "IPC = MU RTD (0x1)\n", + "IPC = MU APD (0x2)\n", + "IPC = INVALID\n", + NULL +}; + +static char *ele_status_str[] = { + "STA = ELE_SUCCESS_IND (0xD6)\n", + "STA = ELE_FAILURE_IND (0x29)\n", + "STA = INVALID\n", + NULL +}; + +static char *ele_cmd_str[] = { + "CMD = ELE_PING_REQ (0x01)\n", + "CMD = ELE_FW_AUTH_REQ (0x02)\n", + "CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n", + "CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n", + "CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n", + "CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n", + "CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n", + "CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n", + "CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n", + "CMD = ELE_READ_FUSE_REQ (0x97)\n", + "CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n", + "CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n", + "CMD = ELE_GET_EVENTS_REQ (0xA2)\n", + "CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n", + "CMD = ELE_RELEASE_RDC_REQ (0xC4)\n", + "CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n", + "CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n", + "CMD = ELE_RESET_REQ (0xC7)\n", + "CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n", + "CMD = ELE_POWER_DOWN_REQ (0xD1)\n", + "CMD = ELE_ENABLE_APC_REQ (0xD2)\n", + "CMD = ELE_ENABLE_RTC_REQ (0xD3)\n", + "CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n", + "CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n", + "CMD = ELE_WRITE_FUSE_REQ (0xD6)\n", + "CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n", + "CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n", + "CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n", + "CMD = ELE_GET_INFO_REQ (0xDA)\n", + "CMD = ELE_ATTEST_REQ (0xDB)\n", + "CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n", + "CMD = ELE_OTP_SEQ_SWITH_REQ (0xDD)\n", + "CMD = INVALID\n", + NULL +}; + +static char *ele_ind_str[] = { + "IND = ELE_ROM_PING_FAILURE_IND (0x0A)\n", + "IND = ELE_FW_PING_FAILURE_IND (0x1A)\n", + "IND = ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)\n", + "IND = ELE_BAD_HASH_FAILURE_IND (0xF1)\n", + "IND = ELE_INVALID_LIFECYCLE_IND (0xF2)\n", + "IND = ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)\n", + "IND = ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)\n", + "IND = ELE_BAD_VALUE_FAILURE_IND (0xF5)\n", + "IND = ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)\n", + "IND = ELE_BAD_CONTAINER_FAILURE_IND (0xF7)\n", + "IND = ELE_BAD_VERSION_FAILURE_IND (0xF8)\n", + "IND = ELE_INVALID_KEY_FAILURE_IND (0xF9)\n", + "IND = ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)\n", + "IND = ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)\n", + "IND = ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)\n", + "IND = ELE_BAD_UID_FAILURE_IND (0xFD)\n", + "IND = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)\n", + "IND = ELE_MUST_SIGNED_FAILURE_IND (0xE0)\n", + "IND = ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)\n", + "IND = ELE_BAD_SRK_SET_FAILURE_IND (0xEF)\n", + "IND = ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)\n", + "IND = ELE_WRONG_SIZE_FAILURE_IND (0xA7)\n", + "IND = ELE_ENCRYPTION_FAILURE_IND (0xA8)\n", + "IND = ELE_DECRYPTION_FAILURE_IND (0xA9)\n", + "IND = ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)\n", + "IND = ELE_OTP_LOCKED_FAILURE_IND (0xAB)\n", + "IND = ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)\n", + "IND = ELE_TIME_OUT_FAILURE_IND (0xB0)\n", + "IND = ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)\n", + "IND = ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)\n", + "IND = ELE_DMA_FAILURE_IND (0xB5)\n", + "IND = ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)\n", + "IND = ELE_MUST_ATTEST_FAILURE_IND (0xB7)\n", + "IND = ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)\n", + "IND = ELE_CRC_ERROR_IND (0xB9)\n", + "IND = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)\n", + "IND = ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)\n", + "IND = ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)\n", + "IND = ELE_LOCKED_REG_FAILURE_IND (0xBE)\n", + "IND = ELE_BAD_ID_FAILURE_IND (0xBF)\n", + "IND = ELE_INVALID_OPERATION_FAILURE_IND (0xC0)\n", + "IND = ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)\n", + "IND = ELE_MSG_TRUNCATED_IND (0xC2)\n", + "IND = ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)\n", + "IND = ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)\n", + "IND = ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)\n", + "IND = ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)\n", + "IND = ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)\n", + "IND = ELE_OUT_OF_MEMORY_IND (0xD1)\n", + "IND = ELE_CSTM_FAILURE_IND (0xCF)\n", + "IND = ELE_OLD_VERSION_FAILURE_IND (0xCE)\n", + "IND = ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)\n", + "IND = ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)\n", + "IND = ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)\n", + "IND = ELE_ABORT_IND (0xFF)\n", + "IND = INVALID\n", + NULL +}; + +static u8 ele_cmd[] = { + ELE_PING_REQ, + ELE_FW_AUTH_REQ, + ELE_RESTART_RST_TIMER_REQ, + ELE_DUMP_DEBUG_BUFFER_REQ, + ELE_OEM_CNTN_AUTH_REQ, + ELE_VERIFY_IMAGE_REQ, + ELE_RELEASE_CONTAINER_REQ, + ELE_WRITE_SECURE_FUSE_REQ, + ELE_FWD_LIFECYCLE_UP_REQ, + ELE_READ_FUSE_REQ, + ELE_GET_FW_VERSION_REQ, + ELE_RET_LIFECYCLE_UP_REQ, + ELE_GET_EVENTS_REQ, + ELE_ENABLE_PATCH_REQ, + ELE_RELEASE_RDC_REQ, + ELE_GET_FW_STATUS_REQ, + ELE_ENABLE_OTFAD_REQ, + ELE_RESET_REQ, + ELE_UPDATE_OTP_CLKDIV_REQ, + ELE_POWER_DOWN_REQ, + ELE_ENABLE_APC_REQ, + ELE_ENABLE_RTC_REQ, + ELE_DEEP_POWER_DOWN_REQ, + ELE_STOP_RST_TIMER_REQ, + ELE_WRITE_FUSE_REQ, + ELE_RELEASE_CAAM_REQ, + ELE_RESET_A35_CTX_REQ, + ELE_MOVE_TO_UNSECURED_REQ, + ELE_GET_INFO_REQ, + ELE_ATTEST_REQ, + ELE_RELEASE_PATCH_REQ, + ELE_OTP_SEQ_SWITH_REQ +}; + +static u8 ele_ind[] = { + ELE_ROM_PING_FAILURE_IND, + ELE_FW_PING_FAILURE_IND, + ELE_BAD_SIGNATURE_FAILURE_IND, + ELE_BAD_HASH_FAILURE_IND, + ELE_INVALID_LIFECYCLE_IND, + ELE_PERMISSION_DENIED_FAILURE_IND, + ELE_INVALID_MESSAGE_FAILURE_IND, + ELE_BAD_VALUE_FAILURE_IND, + ELE_BAD_FUSE_ID_FAILURE_IND, + ELE_BAD_CONTAINER_FAILURE_IND, + ELE_BAD_VERSION_FAILURE_IND, + ELE_INVALID_KEY_FAILURE_IND, + ELE_BAD_KEY_HASH_FAILURE_IND, + ELE_NO_VALID_CONTAINER_FAILURE_IND, + ELE_BAD_CERTIFICATE_FAILURE_IND, + ELE_BAD_UID_FAILURE_IND, + ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND, + ELE_MUST_SIGNED_FAILURE_IND, + ELE_NO_AUTHENTICATION_FAILURE_IND, + ELE_BAD_SRK_SET_FAILURE_IND, + ELE_UNALIGNED_PAYLOAD_FAILURE_IND, + ELE_WRONG_SIZE_FAILURE_IND, + ELE_ENCRYPTION_FAILURE_IND, + ELE_DECRYPTION_FAILURE_IND, + ELE_OTP_PROGFAIL_FAILURE_IND, + ELE_OTP_LOCKED_FAILURE_IND, + ELE_OTP_INVALID_IDX_FAILURE_IND, + ELE_TIME_OUT_FAILURE_IND, + ELE_BAD_PAYLOAD_FAILURE_IND, + ELE_WRONG_ADDRESS_FAILURE_IND, + ELE_DMA_FAILURE_IND, + ELE_DISABLED_FEATURE_FAILURE_IND, + ELE_MUST_ATTEST_FAILURE_IND, + ELE_RNG_NOT_STARTED_FAILURE_IND, + ELE_CRC_ERROR_IND, + ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND, + ELE_INCONSISTENT_PAR_FAILURE_IND, + ELE_RNG_INST_FAILURE_FAILURE_IND, + ELE_LOCKED_REG_FAILURE_IND, + ELE_BAD_ID_FAILURE_IND, + ELE_INVALID_OPERATION_FAILURE_IND, + ELE_NON_SECURE_STATE_FAILURE_IND, + ELE_MSG_TRUNCATED_IND, + ELE_BAD_IMAGE_NUM_FAILURE_IND, + ELE_BAD_IMAGE_ADDR_FAILURE_IND, + ELE_BAD_IMAGE_PARAM_FAILURE_IND, + ELE_BAD_IMAGE_TYPE_FAILURE_IND, + ELE_CORRUPTED_SRK_FAILURE_IND, + ELE_OUT_OF_MEMORY_IND, + ELE_CSTM_FAILURE_IND, + ELE_OLD_VERSION_FAILURE_IND, + ELE_WRONG_BOOT_MODE_FAILURE_IND, + ELE_APC_ALREADY_ENABLED_FAILURE_IND, + ELE_RTC_ALREADY_ENABLED_FAILURE_IND, + ELE_ABORT_IND +}; + +static u8 ele_ipc[] = { + ELE_IPC_MU_RTD, + ELE_IPC_MU_APD +}; + +static u8 ele_status[] = { + ELE_SUCCESS_IND, + ELE_FAILURE_IND +}; + +static inline u32 get_idx(u8 *list, u8 tgt, u32 size) +{ + u32 i; + + for (i = 0; i < size; i++) { + if (list[i] == tgt) + return i; + } + + return i; /* last str is invalid */ +} + +static void display_ahab_auth_ind(u32 event) +{ + u8 resp_ind = (event >> 8) & 0xff; + + printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]); +} + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + u32 resp; + memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + flush_dcache_range(IMG_CONTAINER_BASE, + IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); + + err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, + &resp); + if (err) { + printf("Authenticate container hdr failed, return %d, resp 0x%x\n", + err, resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_auth_release(void) +{ + int err; + u32 resp; + + err = ahab_release_container(&resp); + if (err) { + printf("Error: release container failed, resp 0x%x!\n", resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + int err; + u32 resp; + + err = ahab_verify_image(image_index, &resp); + if (err) { + printf("Authenticate img %d failed, return %d, resp 0x%x\n", + image_index, err, resp); + display_ahab_auth_ind(resp); + + return -EIO; + } + + return 0; +} + +static inline bool check_in_dram(ulong addr) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + if (addr >= bd->bi_dram[i].start && + addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + return true; + } + } + + return false; +} + +int authenticate_os_container(ulong addr) +{ + struct container_hdr *phdr; + int i, ret = 0; + int err; + u16 length; + struct boot_img_t *img; + unsigned long s, e; + + if (addr % 4) { + puts("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_dram(addr)) { + puts("Error: Image's address is invalid\n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 || phdr->version != 0x0) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + + err = ahab_auth_cntr_hdr(phdr, length); + if (err) { + ret = -EIO; + goto exit; + } + + debug("Verify images\n"); + + /* Copy images to dest address */ + for (i = 0; i < phdr->num_images; i++) { + img = (struct boot_img_t *)(addr + + sizeof(struct container_hdr) + + i * sizeof(struct boot_img_t)); + + debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", + i, (uint32_t) img->dst, img->offset + addr, img->size); + + memcpy((void *)img->dst, (const void *)(img->offset + addr), + img->size); + + s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; + + flush_dcache_range(s, e); + + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; + } + +exit: + debug("ahab_auth_release, 0x%x\n", ret); + ahab_auth_release(); + + return ret; +} + +static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + printf("Authenticate OS container at 0x%lx\n", addr); + + if (authenticate_os_container(addr)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB\n\n"); + break; + case 0x4: + printf("NXP Provisioned\n\n"); + break; + case 0x8: + printf("OEM Open\n\n"); + break; + case 0x20: + printf("OEM closed\n\n"); + break; + case 0x40: + printf("Field Return OEM\n\n"); + break; + case 0x80: + printf("Field Return NXP\n\n"); + break; + case 0x100: + printf("OEM Locked\n\n"); + break; + case 0x200: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} + +static int confirm_close(void) +{ + puts("Warning: Please ensure your sample is in NXP closed state, " + "OEM SRK hash has been fused, \n" + " and you are able to boot a signed image successfully " + "without any SECO events reported.\n" + " If not, your sample will be unrecoverable.\n" + "\nReally perform this operation? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Ahab close aborted\n"); + return 0; +} + +static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err; + u32 resp; + u32 lc; + + if (!confirm_close()) + return -EACCES; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3ff; + + if (lc != 0x8) { + puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n"); + display_life_cycle(lc); + return -EPERM; + } + + err = ahab_forward_lifecycle(8, &resp); + if (err != 0) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + printf("Change to OEM closed successfully\n"); + + return 0; +} + +int ahab_dump(void) +{ + u32 buffer[32]; + int ret, i = 0; + + do { + ret = ahab_dump_buffer(buffer, 32); + if (ret < 0) { + printf("Error in dump AHAB log\n"); + return -EIO; + } + + if (ret == 1) { + break; + } else { + for (i = 0; i < ret; i++) + printf("0x%x\n", buffer[i]); + } + } while (ret >= 21); + + return 0; +} + +static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return ahab_dump(); +} + +static void display_event(u32 event) +{ + printf("\n\t0x%08x\n", event); + printf("\t%s", ele_ipc_str[get_idx(ele_ipc, + (event >> 24) & 0xFF, ARRAY_SIZE(ele_ipc))]); + printf("\t%s", ele_cmd_str[get_idx(ele_cmd, + (event >> 16) & 0xFF, ARRAY_SIZE(ele_cmd))]); + printf("\t%s", ele_ind_str[get_idx(ele_ind, + (event >> 8) & 0xFF, ARRAY_SIZE(ele_ind))]); + printf("\t%s", ele_status_str[get_idx(ele_status, + event & 0xFF, ARRAY_SIZE(ele_status))]); +} + +static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 lc, i; + u32 events[AHAB_MAX_EVENTS]; + u32 cnt = AHAB_MAX_EVENTS; + int ret; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3ff; + + display_life_cycle(lc); + + ret = ahab_get_events(events, &cnt, NULL); + if (ret) { + printf("Get ELE EVENTS error %d\n", ret); + return CMD_RET_FAILURE; + } + + if (!cnt) { + puts("\n\tNo Events Found!\n"); + return 0; + } + + for (i = 0; i < cnt; i++) + display_event(events[i]); + + return 0; +} + +static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ahab_write_secure_fuse(addr, &response)) { + printf("Program secure fuse failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Program secure fuse completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + + +U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, + "autenticate OS container via AHAB", + "addr\n" + "addr - OS container hex address\n" +); + +U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, + "Change AHAB lifecycle to OEM closed", + "" +); + +U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, + "Dump AHAB log for debug", + "" +); + +U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, + "display AHAB lifecycle only", + "" +); + +U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog, + "Program secure fuse via signed message block", + "addr\n" + "addr - Signed message block for secure fuse\n" +); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index b857a48da1..367410b154 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -191,39 +191,41 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) unsigned long offset = 0, sec_set_off = 0; bool sec_boot = false; - sec_boot = check_secondary_cnt_set(&sec_set_off); - if (sec_boot) - printf("Secondary set selected\n"); - else - printf("Primary set selected\n"); - - if (dev_type == MMC_DEV) { - struct mmc *mmc = (struct mmc *)dev; + if (dev_type == ROM_API_DEV) { + offset = (unsigned long)dev; + } else { + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + printf("Secondary set selected\n"); + else + printf("Primary set selected\n"); - if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { - offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; - } else { - u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + if (dev_type == MMC_DEV) { + struct mmc *mmc = (struct mmc *)dev; - if (part == 1 || part == 2) { - if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) - offset = CONTAINER_HDR_MMCSD_OFFSET; - else - offset = CONTAINER_HDR_EMMC_OFFSET; - } else { + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; + } else { + u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == 1 || part == 2) { + if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) + offset = CONTAINER_HDR_MMCSD_OFFSET; + else + offset = CONTAINER_HDR_EMMC_OFFSET; + } else { + offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; + } } + } else if (dev_type == QSPI_DEV) { + offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET; + } else if (dev_type == NAND_DEV) { + offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET; + } else if (dev_type == QSPI_NOR_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; + } else if (dev_type == RAM_DEV) { + offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET; } - } else if (dev_type == QSPI_DEV) { - offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET; - } else if (dev_type == NAND_DEV) { - offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET; - } else if (dev_type == QSPI_NOR_DEV) { - offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; - } else if (dev_type == ROM_API_DEV) { - offset = (unsigned long)dev; - } else if (dev_type == RAM_DEV) { - offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET; } debug("container set offset 0x%lx\n", offset); diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b2b8ade0bd..7abcfeca86 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -176,6 +176,7 @@ config TARGET_IMX8DXL_EVK bool "Support i.MX8DXL EVK board" select BOARD_LATE_INIT select IMX8DXL + select CRYPTO_SHA2_ARM64_CE select FSL_CAAM select FSL_BLOB select ARCH_MISC_INIT diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 3c3c4cdc4f..deb18a3bb2 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2022 NXP */ #include <common.h> @@ -16,6 +16,7 @@ #include <asm/mach-imx/image.h> #include <console.h> #include <cpu_func.h> +#include <crypto/sha2.h> #include <asm/mach-imx/ahab.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) #define SECO_PT 2U +#define AHAB_HASH_TYPE_MASK 0x00000700 +#define AHAB_HASH_TYPE_SHA256 0 int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { @@ -130,6 +133,9 @@ int authenticate_os_container(ulong addr) u16 length; struct boot_img_t *img; unsigned long s, e; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + u8 hash_value[SHA256_DIGEST_SIZE]; +#endif if (addr % 4) { puts("Error: Image's address is not 4 byte aligned\n"); @@ -179,9 +185,23 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) { + sha256_ce((void *)img->dst, img->size, hash_value); + err = memcmp(&img->hash, &hash_value, SHA256_DIGEST_SIZE); + if (err) { + printf("img %d hash comparison failed, error %d\n", i, err); + ret = -EIO; + goto exit; + } + } else { +#endif ret = ahab_verify_cntr_image(img, i); if (ret) goto exit; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + } +#endif } exit: diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 10fcada0cb..a94cd0df40 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -33,6 +33,10 @@ #include <asm/mach-imx/imx_vservice.h> #include <usb/ci_udc.h> +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + DECLARE_GLOBAL_DATA_PTR; #define BT_PASSOVER_TAG 0x504F diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 456073873d..a225a9784f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -120,6 +120,24 @@ config TARGET_IMX8MM_DDR4_EVK select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MM_AB2 + bool "imx8mm LPDDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MM_DDR4_AB2 + bool "imx8mm DDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" select IMX8MM @@ -179,6 +197,33 @@ config TARGET_IMX8MN_DDR3_EVK select FSL_BLOB select SPL_CRYPTO if SPL +config TARGET_IMX8MN_AB2 + bool "imx8mn LPDDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MN_DDR4_AB2 + bool "imx8mn DDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MN_DDR3L_AB2 + bool "imx8mn DDR3L Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR3L + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" select BINMAN @@ -305,6 +350,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/engicam/imx8mm/Kconfig" source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mq_val/Kconfig" +source "board/freescale/imx8mm_ab2/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mm_val/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d6be307e6e..203c52d1d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -83,7 +83,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 74e0c1d199..c2f6acdde7 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -747,7 +747,7 @@ bool is_usb_boot(void) { return get_boot_device() == USB_BOOT; } -#ifdef CONFIG_SERIAL_TAG +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) void get_board_serial(struct tag_serialnr *serialnr) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -1761,6 +1761,16 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; switch (dev) { + case USB_BOOT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) + return ENVL_NAND; + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + return ENVL_UNKNOWN; case QSPI_BOOT: if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 1e465ab720..e82347ed68 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -40,12 +40,22 @@ config TARGET_IMX8ULP_9X9_EVK select IMX8ULP_DRAM select FSL_CAAM select FSL_BLOB - select MISC select ARCH_MISC_INIT select SPL_CRYPTO_SUPPORT if SPL +config TARGET_IMX8ULP_WATCH + bool "imx8ulp_watch" + select IMX8ULP + select SUPPORT_SPL + select IMX8ULP_DRAM + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL + endchoice source "board/freescale/imx8ulp_evk/Kconfig" +source "board/freescale/imx8ulp_watch/Kconfig" endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index f7692cf3a7..2c9938fcdf 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,7 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -obj-$(CONFIG_AHAB_BOOT) += ahab.o ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/ diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c deleted file mode 100644 index 93957f74e0..0000000000 --- a/arch/arm/mach-imx/imx8ulp/ahab.c +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 NXP - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/s400_api.h> -#include <asm/mach-imx/sys_proto.h> -#include <asm/arch-imx/cpu.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/image.h> -#include <console.h> -#include <cpu_func.h> -#include <asm/mach-imx/ahab.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define IMG_CONTAINER_BASE (0x22010000UL) -#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) - -#define AHAB_NO_AUTHENTICATION_IND 0xee -#define AHAB_BAD_KEY_HASH_IND 0xfa -#define AHAB_INVALID_KEY_IND 0xf9 -#define AHAB_BAD_SIGNATURE_IND 0xf0 -#define AHAB_BAD_HASH_IND 0xf1 - -static void display_ahab_auth_ind(u32 event) -{ - u8 resp_ind = (event >> 8) & 0xff; - - switch (resp_ind) { - case AHAB_NO_AUTHENTICATION_IND: - printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_KEY_HASH_IND: - printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_INVALID_KEY_IND: - printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_SIGNATURE_IND: - printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_HASH_IND: - printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind); - break; - default: - printf("Unknown Indicator (0x%02X)\n\n", resp_ind); - break; - } -} - -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) -{ - int err; - u32 resp; - memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - - flush_dcache_range(IMG_CONTAINER_BASE, - IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); - - err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, - &resp); - if (err) { - printf("Authenticate container hdr failed, return %d, resp 0x%x\n", - err, resp); - display_ahab_auth_ind(resp); - } - - return err; -} - -int ahab_auth_release(void) -{ - int err; - u32 resp; - - err = ahab_release_container(&resp); - if (err) { - printf("Error: release container failed, resp 0x%x!\n", resp); - display_ahab_auth_ind(resp); - } - - return err; -} - -int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) -{ - int err; - u32 resp; - - err = ahab_verify_image(image_index, &resp); - if (err) { - printf("Authenticate img %d failed, return %d, resp 0x%x\n", - image_index, err, resp); - display_ahab_auth_ind(resp); - return -EIO; - } - - return 0; -} - -static inline bool check_in_dram(ulong addr) -{ - int i; - struct bd_info *bd = gd->bd; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) - return true; - } - } - - return false; -} - -int authenticate_os_container(ulong addr) -{ - struct container_hdr *phdr; - int i, ret = 0; - int err; - u16 length; - struct boot_img_t *img; - unsigned long s, e; - - if (addr % 4) { - puts("Error: Image's address is not 4 byte aligned\n"); - return -EINVAL; - } - - if (!check_in_dram(addr)) { - puts("Error: Image's address is invalid\n"); - return -EINVAL; - } - - phdr = (struct container_hdr *)addr; - if (phdr->tag != 0x87 || phdr->version != 0x0) { - printf("Error: Wrong container header\n"); - return -EFAULT; - } - - if (!phdr->num_images) { - printf("Error: Wrong container, no image found\n"); - return -EFAULT; - } - - length = phdr->length_lsb + (phdr->length_msb << 8); - - debug("container length %u\n", length); - - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { - ret = -EIO; - goto exit; - } - - debug("Verify images\n"); - - /* Copy images to dest address */ - for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + - sizeof(struct container_hdr) + - i * sizeof(struct boot_img_t)); - - debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", - i, (uint32_t) img->dst, img->offset + addr, img->size); - - memcpy((void *)img->dst, (const void *)(img->offset + addr), - img->size); - - s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); - e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; - - flush_dcache_range(s, e); - - ret = ahab_verify_cntr_image(img, i); - if (ret) - goto exit; - } - -exit: - debug("ahab_auth_release, 0x%x\n", ret); - ahab_auth_release(); - - return ret; -} - -static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - ulong addr; - - if (argc < 2) - return CMD_RET_USAGE; - - addr = simple_strtoul(argv[1], NULL, 16); - - printf("Authenticate OS container at 0x%lx\n", addr); - - if (authenticate_os_container(addr)) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -static void display_life_cycle(u32 lc) -{ - printf("Lifecycle: 0x%08X, ", lc); - switch (lc) { - case 0x1: - printf("BLANK\n\n"); - break; - case 0x2: - printf("FAB\n\n"); - break; - case 0x4: - printf("NXP Provisioned\n\n"); - break; - case 0x8: - printf("OEM Open\n\n"); - break; - case 0x10: - printf("OEM Secure World Closed\n\n"); - break; - case 0x20: - printf("OEM closed\n\n"); - break; - case 0x40: - printf("Field Return OEM\n\n"); - break; - case 0x80: - printf("Field Return NXP\n\n"); - break; - case 0x100: - printf("OEM Locked\n\n"); - break; - case 0x200: - printf("BRICKED\n\n"); - break; - default: - printf("Unknown\n\n"); - break; - } -} - -static int confirm_close(void) -{ - puts("Warning: Please ensure your sample is in NXP closed state, " - "OEM SRK hash has been fused, \n" - " and you are able to boot a signed image successfully " - "without any SECO events reported.\n" - " If not, your sample will be unrecoverable.\n" - "\nReally perform this operation? <y/N>\n"); - - if (confirm_yesno()) - return 1; - - puts("Ahab close aborted\n"); - return 0; -} - -static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - int err; - u32 resp; - - if (!confirm_close()) - return -EACCES; - - err = ahab_forward_lifecycle(8, &resp); - if (err != 0) { - printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; - } - - printf("Change to OEM closed successfully\n"); - - return 0; -} - -int ahab_dump(void) -{ - u32 buffer[32]; - int ret, i = 0; - - do { - ret = ahab_dump_buffer(buffer, 32); - if (ret < 0) { - printf("Error in dump AHAB log\n"); - return -EIO; - } - - if (ret == 1) { - break; - } else { - for (i = 0; i < ret; i++) - printf("0x%x\n", buffer[i]); - } - } while (ret >= 21); - - return 0; -} - -static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - return ahab_dump(); -} - -static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u32 lc; - - lc = readl(FSB_BASE_ADDR + 0x41c); - lc &= 0x3ff; - - display_life_cycle(lc); - return 0; -} - -U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, - "autenticate OS container via AHAB", - "addr\n" - "addr - OS container hex address\n" -); - -U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, - "Change AHAB lifecycle to OEM closed", - "" -); - -U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, - "Dump AHAB log for debug", - "" -); - -U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, - "display AHAB lifecycle only", - "" -); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 3913b17051..b19268c822 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -136,39 +136,34 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7)); clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F); - - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */ - } else { - setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */ - } - + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); /* PFD1 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16); + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 16); /* PFD2 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24); - setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 24); /* PFD3 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x03010000); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */ + else + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x01000000); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */ clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); @@ -179,6 +174,17 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23)); clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31)); + /* NIC_AP: + * OD source PLL3 PFD0, 324M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21)); + } + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28)); /* nicclk select pll3 pfd0 */ while (!(readl(&cgc1_regs->nicclk) & BIT(27))) @@ -218,18 +224,9 @@ void cgc2_pll4_init(bool pll4_reset) /* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21); /* 99Mhz for NIC_LPAV */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); /* 198Mhz for NIC_LPAV */ - } else { - setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ - clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); - } - setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */ - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 16); /* 316.8Mhz */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396Mhz */ clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31)); @@ -241,9 +238,22 @@ void cgc2_pll4_init(bool pll4_reset) clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31)); clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); - while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) - ; + /* NIC_LPAV: + * OD source PLL4 PFD1, 316.8M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); + } + + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); + while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) + ; + } } void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd) diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index b4240c83a1..17dff404fb 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -183,37 +183,20 @@ void clock_init_late(void) */ cgc1_pll3_init(540672000); - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } else { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD3_DIV1); /* 389M for OD, 194M for LD/ND*/ + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND */ + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND*/ + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); /* enable MU0_MUB clock before access the register of MU0_MUB */ pcc_clock_enable(3, MU0_B_PCC3_SLOT, true); @@ -432,6 +415,8 @@ void reset_lcdclk(void) pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true); } +/* PLL4 PFD0 max frequency */ +#define PLL4_PFD0_MAX_RATE 600000 /*khz*/ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) { u8 pcd, best_pcd = 0; @@ -447,10 +432,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; + if (parent_rate > PLL4_PFD0_MAX_RATE) + continue; + parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index e2eca0633e..f5423ec7b9 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -8,8 +8,8 @@ #include <asm/types.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/mu_hal.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/mu_hal.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/rdc.h> #include <div64.h> @@ -184,14 +184,14 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; - struct imx8ulp_s400_msg msg; + struct sentinel_msg msg; int ret; u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ; msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ mu_hal_init(s_mu_base); @@ -276,6 +276,36 @@ void xrdc_init_mda(void) void xrdc_init_mrc(void) { + /* Re-config MRC3 for SRAM0 in case protected by S400 */ + xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000); + xrdc_config_mrc_dx_perm(3, 0, 0, 1); + xrdc_config_mrc_dx_perm(3, 0, 1, 1); + xrdc_config_mrc_dx_perm(3, 0, 4, 1); + xrdc_config_mrc_dx_perm(3, 0, 5, 1); + xrdc_config_mrc_dx_perm(3, 0, 6, 1); + xrdc_config_mrc_dx_perm(3, 0, 7, 1); + xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF); + + /* Clear other 3 regions of MRC3 to invalid */ + xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0); + + /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */ + xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(4, 0, 1, 1); + xrdc_config_mrc_dx_perm(4, 0, 7, 1); + xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF); + + xrdc_config_mrc_w0_w1(5, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(5, 0, 1, 1); + xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF); + + /* Set MRC6 for DDR access from Sentinel */ + xrdc_config_mrc_w0_w1(6, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(6, 0, 4, 1); + xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF); + /* The MRC8 is for SRAM1 */ xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000); /* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index dc1fa70e3c..6e20b11801 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -13,8 +13,8 @@ #include <efi_loader.h> #include <spl.h> #include <asm/arch/rdc.h> -#include <asm/arch/s400_api.h> -#include <asm/arch/mu_hal.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/mu_hal.h> #include <cpu_func.h> #include <asm/setup.h> #include <dm.h> @@ -152,9 +152,18 @@ int board_usb_gadget_port_auto(void) } #endif +static void set_cpu_info(struct sentinel_get_info_data *info) +{ + gd->arch.soc_rev = info->soc; + gd->arch.lifecycle = info->lc; + memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); +} + u32 get_cpu_rev(void) { - return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; + u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; + + return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev); } enum bt_mode get_boot_mode(void) @@ -177,14 +186,70 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - u32 gp6 = 0; + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 gp6 = 0; + + /* DGO_GP6 */ + gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); + if (gp6 & (1 << 5)) + return true; + + return false; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x1) + return true; + + return false; + } +} + +bool rdc_enabled_in_boot(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 val = 0; + int ret; + bool rdc_en = true; /* Default assume DBD_EN is set */ - /* DGO_GP6 */ - gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); - if (gp6 & (1 << 5)) - return true; + /* Read DBD_EN fuse */ + ret = fuse_read(8, 1, &val); + if (!ret) + rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/ + + return rdc_en; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x2) + return true; + + return false; + } +} + +static void spl_pass_boot_info(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + bool m33_booted = m33_image_booted(); + bool rdc_en = rdc_enabled_in_boot(); + u32 val = 0; + + if (m33_booted) + val |= 0x1; + + if (rdc_en) + val |= 0x2; + + writel(val, SIM1_BASE_ADDR); + } +} - return false; +bool is_m33_handshake_necessary(void) +{ + /* Only need handshake in u-boot */ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return (m33_image_booted() || rdc_enabled_in_boot()); + else + return false; } int m33_image_handshake(ulong timeout_ms) @@ -290,7 +355,7 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); -#if defined(CONFIG_IMX_PMC_TEMPERATURE) +#if defined(CONFIG_SCMI_THERMAL) struct udevice *udev; int ret, temp; @@ -632,33 +697,65 @@ static void set_core0_reset_vector(u32 entry) setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); } -static int trdc_set_access(void) +/* Not used now */ +int trdc_set_access(void) { /* * TRDC mgr + 4 MBC + 2 MRC. - * S400 should already configure when release RDC - * A35 only map non-secure region for pbridge0 and 1, set sec_access to false */ - trdc_mbc_set_access(2, 7, 0, 49, false); - trdc_mbc_set_access(2, 7, 0, 50, false); - trdc_mbc_set_access(2, 7, 0, 51, false); - trdc_mbc_set_access(2, 7, 0, 52, false); - trdc_mbc_set_access(2, 7, 0, 53, false); - trdc_mbc_set_access(2, 7, 0, 54, false); - - /* CGC0: PBridge0 slot 47 */ + trdc_mbc_set_access(2, 7, 0, 49, true); + trdc_mbc_set_access(2, 7, 0, 50, true); + trdc_mbc_set_access(2, 7, 0, 51, true); + trdc_mbc_set_access(2, 7, 0, 52, true); + trdc_mbc_set_access(2, 7, 0, 53, true); + trdc_mbc_set_access(2, 7, 0, 54, true); + + /* 0x1fff8000 used for resource table by remoteproc */ + trdc_mbc_set_access(0, 7, 2, 31, false); + + /* CGC0: PBridge0 slot 47 and PCC0 slot 48 */ trdc_mbc_set_access(2, 7, 0, 47, false); + trdc_mbc_set_access(2, 7, 0, 48, false); + + /* PCC1 */ + trdc_mbc_set_access(2, 7, 1, 17, false); + trdc_mbc_set_access(2, 7, 1, 34, false); /* Iomuxc0: : PBridge1 slot 33 */ trdc_mbc_set_access(2, 7, 1, 33, false); /* flexspi0 */ + trdc_mbc_set_access(2, 7, 0, 57, false); trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); /* tpm0: PBridge1 slot 21 */ trdc_mbc_set_access(2, 7, 1, 21, false); /* lpi2c0: PBridge1 slot 24 */ trdc_mbc_set_access(2, 7, 1, 24, false); + + /* Allow M33 to access TRDC MGR */ + trdc_mbc_set_access(2, 6, 0, 49, true); + trdc_mbc_set_access(2, 6, 0, 50, true); + trdc_mbc_set_access(2, 6, 0, 51, true); + trdc_mbc_set_access(2, 6, 0, 52, true); + trdc_mbc_set_access(2, 6, 0, 53, true); + trdc_mbc_set_access(2, 6, 0, 54, true); + + /* Set SAI0 for eDMA 0, NS */ + trdc_mbc_set_access(2, 0, 1, 28, false); + + /* Set SSRAM for eDMA0 access */ + trdc_mbc_set_access(0, 0, 2, 0, false); + trdc_mbc_set_access(0, 0, 2, 1, false); + trdc_mbc_set_access(0, 0, 2, 2, false); + trdc_mbc_set_access(0, 0, 2, 3, false); + trdc_mbc_set_access(0, 0, 2, 4, false); + trdc_mbc_set_access(0, 0, 2, 5, false); + trdc_mbc_set_access(0, 0, 2, 6, false); + trdc_mbc_set_access(0, 0, 2, 7, false); + + writel(0x800000a0, 0x28031840); + return 0; } @@ -705,10 +802,6 @@ void set_lpav_qos(void) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - u32 val = 0; - int ret; - bool rdc_en = true; /* Default assume DBD_EN is set */ - /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -725,29 +818,21 @@ int arch_cpu_init(void) /* Disable wdog */ init_wdog(); - /* Read DBD_EN fuse */ - ret = fuse_read(8, 1, &val); - if (!ret) - rdc_en = !!(val & 0x4000); - if (get_boot_mode() == SINGLE_BOOT) { - if (rdc_en) - release_rdc(RDC_TRDC); - - trdc_set_access(); - lpav_configure(false); } else { lpav_configure(true); } /* Release xrdc, then allow A35 to write SRAM2 */ - if (rdc_en) + if (rdc_enabled_in_boot()) release_rdc(RDC_XRDC); xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); clock_init_early(); + + spl_pass_boot_info(); } else { /* reconfigure core0 reset vector to ROM */ set_core0_reset_vector(0x1000); @@ -756,10 +841,36 @@ int arch_cpu_init(void) return 0; } +int checkcpu(void) +{ + if (is_m33_handshake_necessary()) { + if (!gd->arch.m33_handshake_done) { + puts("M33 Sync: Timeout, Boot Stop!\n"); + hang(); + } else { + puts("M33 Sync: OK\n"); + } + } + return 0; +} + int arch_cpu_init_dm(void) { struct udevice *devp; int node, ret; + u32 res; + struct sentinel_get_info_data info; + + if (!IS_ENABLED(CONFIG_SPL_BUILD) && is_m33_handshake_necessary()) { + /* Start handshake with M33 to ensure TRDC configuration completed */ + ret = m33_image_handshake(1000); + if (!ret) { + gd->arch.m33_handshake_done = true; + } else { + gd->arch.m33_handshake_done = false; + return 0; /* Skip and go through to panic in checkcpu as console is ready then */ + } + } node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu"); @@ -769,6 +880,16 @@ int arch_cpu_init_dm(void) return ret; } + ret = ahab_get_info(&info, &res); + if (ret) { + printf("ahab_get_info failed %d\n", ret); + /* fallback to A0.1 revision */ + memset((void *)&info, 0, sizeof(struct sentinel_get_info_data)); + info.soc = 0xa000084d; + } + + set_cpu_info(&info); + return 0; } @@ -856,7 +977,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc; u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev) { /* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */ - if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en()) + if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && + card_emmc_is_boot_part_en()) image_offset = 0; return image_offset; diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index c24bc079ec..ee215a4c76 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -6,6 +6,7 @@ #include <log.h> #include <asm/io.h> #include <linux/delay.h> +#include <asm/arch/sys_proto.h> #include "upower_soc_defs.h" #include "upower_api.h" @@ -13,6 +14,24 @@ #define UPOWER_AP_MU1_ADDR 0x29280000 +#define PS_RTD BIT(0) +#define PS_DSP BIT(1) +#define PS_A35_0 BIT(2) +#define PS_A35_1 BIT(3) +#define PS_L2 BIT(4) +#define PS_FAST_NIC BIT(5) +#define PS_APD_PERIPH BIT(6) +#define PS_GPU3D BIT(7) +#define PS_HIFI4 BIT(8) +#define PS_DDR GENMASK(12, 9) +#define PS_PXP_EPDC BIT(13) +#define PS_MIPI_DSI BIT(14) +#define PS_MIPI_CSI BIT(15) +#define PS_NIC_LPAV BIT(16) +#define PS_FUSION_AO BIT(17) +#define PS_FUSE BIT(18) +#define PS_UPOWER BIT(19) + static struct MU_tag *muptr = (struct MU_tag *)UPOWER_AP_MU1_ADDR; extern void upwr_txrx_isr(void); @@ -123,6 +142,7 @@ int upower_init(void) u32 fw_major, fw_minor, fw_vfixes; u32 soc_id; int status; + upwr_resp_t err_code; uint32_t swton; uint64_t memon; @@ -155,27 +175,92 @@ int upower_init(void) } } while(0); - swton = 0xfff80; + swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR | + PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI; ret = upwr_pwm_power_on(&swton, NULL /* no memories */, NULL /* no callback */); if (ret) printf("Turn on switches fail %d\n", ret); else - printf("Turn on switches ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on switches...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on switches ok\n"); - memon = 0x3FFFFFFFFFFFFCUL; + /* + * Ascending Order -> bit [0:54) + * CA35 Core 0 L1 cache + * CA35 Core 1 L1 cache + * L2 Cache 0 + * L2 Cache 1 + * L2 Cache victim/tag + * CAAM Secure RAM + * DMA1 RAM + * FlexSPI2 FIFO, Buffer + * SRAM0 + * AD ROM + * USB0 TX/RX RAM + * uSDHC0 FIFO RAM + * uSDHC1 FIFO RAM + * uSDHC2 FIFO and USB1 TX/RX RAM + * GIC RAM + * ENET TX FIXO + * Reserved(Brainshift) + * DCNano Tile2Linear and RGB Correction + * DCNano Cursor and FIFO + * EPDC LUT + * EPDC FIFO + * DMA2 RAM + * GPU2D RAM Group 1 + * GPU2D RAM Group 2 + * GPU3D RAM Group 1 + * GPU3D RAM Group 2 + * HIFI4 Caches, IRAM, DRAM + * ISI Buffers + * MIPI-CSI FIFO + * MIPI-DSI FIFO + * PXP Caches, Buffers + * SRAM1 + * Casper RAM + * DMA0 RAM + * FlexCAN RAM + * FlexSPI0 FIFO, Buffer + * FlexSPI1 FIFO, Buffer + * CM33 Cache + * PowerQuad RAM + * ETF RAM + * Sentinel PKC, Data RAM1, Inst RAM0/1 + * Sentinel ROM + * uPower IRAM/DRAM + * uPower ROM + * CM33 ROM + * SSRAM Partition 0 + * SSRAM Partition 1 + * SSRAM Partition 2,3,4 + * SSRAM Partition 5 + * SSRAM Partition 6 + * SSRAM Partition 7_a(128KB) + * SSRAM Partition 7_b(64KB) + * SSRAM Partition 7_c(64KB) + * Sentinel Data RAM0, Inst RAM2 + */ + /* MIPI-CSI FIFO BIT28 not set */ + memon = 0x3FFFFFEFFFFFFCUL; ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon /* no memories */, NULL /* no callback */); if (ret) printf("Turn on memories fail %d\n", ret); else - printf("Turn on memories ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on memories...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on memories ok\n"); mdelay(1); @@ -183,28 +268,34 @@ int upower_init(void) if (ret) printf("Clear DDR retention fail %d\n", ret); else - printf("Clear DDR retention ok\n"); + printf("Clearing DDR retention...\n"); upower_wait_resp(); - - ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000); + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Clear DDR retention ok\n"); - /* Enable AFBB for AP domain */ - bias.apply = BIAS_APPLY_APD; - bias.dommode = AFBB_BIAS_MODE; - ret = upwr_pwm_chng_dom_bias(&bias, NULL); + if (is_soc_rev(CHIP_REV_1_0)) { + /* Enable AFBB for AP domain */ + bias.apply = BIAS_APPLY_APD; + bias.dommode = AFBB_BIAS_MODE; + ret = upwr_pwm_chng_dom_bias(&bias, NULL); - if (ret) - printf("Enable AFBB for APD bias fail %d\n", ret); - else - printf("Enable AFBB for APD bias ok\n"); + if (ret) + printf("Enable AFBB for APD bias fail %d\n", ret); + else + printf("Enabling AFBB for APD bias...\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); - if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); + if (ret != UPWR_REQ_OK) + printf("Enable AFBB fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Enable AFBB for APD bias ok\n"); + + } return 0; } diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig new file mode 100644 index 0000000000..f4fc1ac5ce --- /dev/null +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -0,0 +1,46 @@ +if ARCH_IMX9 + +config AHAB_BOOT + bool "Support i.MX9 AHAB features" + help + This option enables the support for AHAB secure boot. + +config IMX9_LOW_DRIVE_MODE + bool "Configure to i.MX9 low drive mode" + help + This option enables the settings for iMX9 low drive mode. + +config IMX9 + bool + select ARCH_EARLY_INIT_R + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + +config IMX93 + bool + select IMX9 + select ARMV8_SPL_EXCEPTION_VECTORS + +config SYS_SOC + default "imx9" + +choice + prompt "NXP i.MX9 board select" + optional + +config TARGET_IMX93_11X11_EVK + bool "imx93_11x11_evk" + select IMX93 + +config TARGET_IMX93_9X9_QSB + bool "imx93_9x9_qsb" + select IMX93 + select IMX9_LPDDR4X + +endchoice + +source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_qsb/Kconfig" + +endif + diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile new file mode 100644 index 0000000000..e1b09ab534 --- /dev/null +++ b/arch/arm/mach-imx/imx9/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2022 NXP + +obj-y += lowlevel_init.o +obj-y += soc.o clock.o clock_root.o trdc.o + +#ifndef CONFIG_SPL_BUILD +obj-y += imx_bootaux.o +#endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c new file mode 100644 index 0000000000..909a770e1c --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock.c @@ -0,0 +1,947 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <div64.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; + +static struct imx_intpll_rate_table imx9_intpll_tbl[] = { + INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ + INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */ + INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ + INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ + INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ +}; + +static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { + FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ + FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ + FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ + FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), + FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), + FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ + FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ + FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), +}; + +/* return in khz */ +static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl; + u32 pll_status; + u32 div; + int rdiv, mfi, mfn, mfd; + int clk = 24000; + + ctrl = readl(®->ctrl.reg); + pll_status = readl(®->pll_status); + div = readl(®->div.reg); + + if (!(ctrl & PLL_CTRL_POWERUP)) + return 0; + + if (!(pll_status & PLL_STATUS_PLL_LOCK)) + return 0; + + mfi = (div & GENMASK(24, 16)) >> 16; + rdiv = (div & GENMASK(15, 13)) >> 13; + + if (rdiv == 0) + rdiv = 1; + + if (fracpll) { + mfn = (int)readl(®->num.reg); + mfn >>= 2; + mfd = (int)(readl(®->denom.reg) & GENMASK(29, 0)); + + clk = clk * (mfi * mfd + mfn) / mfd / rdiv; + } else { + clk = clk * mfi / rdiv; + } + + return (u32)clk; +} + +/* return in khz */ +static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl = readl(®->ctrl.reg); + u32 div; + + if (ctrl & PLL_CTRL_CLKMUX_BYPASS) + return 24000; + + if (!(ctrl & PLL_CTRL_CLKMUX_EN)) + return 0; + + div = readl(®->div.reg); + div &= 0xff; /* odiv */ + + if (div == 0) + div = 2; + else if (div == 1) + div = 3; + + return decode_pll_vco(reg, fracpll) / div; +} + +/* return in khz */ +static u32 decode_pll_pfd(struct ana_pll_reg *reg, + struct ana_pll_dfs *dfs_reg, bool div2, bool fracpll) +{ + u32 pllvco = decode_pll_vco(reg, fracpll); + u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg); + u32 dfs_div = readl(&dfs_reg->dfs_div.reg); + u32 mfn, mfi; + u32 output; + + if (dfs_ctrl & PLL_DFS_CTRL_BYPASS) + return pllvco; + + if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) || + (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) || + (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT))) + return 0; + + mfn = dfs_div & GENMASK(2, 0); + mfi = (dfs_div & GENMASK(15, 8)) >> 8; + + if (mfn > 3) + return 0; /* valid mfn 0-3 */ + + if (mfi == 0 || mfi == 1) + return 0; /* valid mfi 2-255 */ + + output = (pllvco * 5) / (mfi * 5 + mfn); + + if (div2) + return output >> 1; + + return output; +} + +static u32 decode_pll(enum ccm_clk_src pll) +{ + switch (pll) { + case ARM_PLL_CLK: + return decode_pll_out(&ana_regs->arm_pll, false); + case SYS_PLL_PG: + return decode_pll_out(&ana_regs->sys_pll, false); + case SYS_PLL_PFD0: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], false, true); + case SYS_PLL_PFD0_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], true, true); + case SYS_PLL_PFD1: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], false, true); + case SYS_PLL_PFD1_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], true, true); + case SYS_PLL_PFD2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], false, true); + case SYS_PLL_PFD2_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], true, true); + case AUDIO_PLL_CLK: + return decode_pll_out(&ana_regs->audio_pll, true); + case DRAM_PLL_CLK: + return decode_pll_out(&ana_regs->dram_pll, true); + case VIDEO_PLL_CLK: + return decode_pll_out(&ana_regs->video_pll, true); + default: + printf("Invalid clock source to decode\n"); + break; + } + + return 0; +} + +int configure_intpll(enum ccm_clk_src pll, u32 freq) +{ + int i; + struct imx_intpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + + for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) { + if (freq == imx9_intpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_intpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_intpll_tbl[i]; + + /* ROM has configured SYS PLL and PFD, no need for it */ + switch (pll) { + case ARM_PLL_CLK: + reg = &ana_regs->arm_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | + ((rate->rdiv << 13 ) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* wait 5us */ + udelay(5); +#endif + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + udelay(100); +#endif + + pll_status = readl(®->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set); + + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + + +int configure_fracpll(enum ccm_clk_src pll, u32 freq) +{ + int i; + struct imx_fracpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + + for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) { + if (freq == imx9_fracpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_fracpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_fracpll_tbl[i]; + + switch (pll) { + case SYS_PLL_PG: + reg = &ana_regs->sys_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | + ((rate->rdiv << 13 ) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg); + + /* Set SPREAD_SPECRUM enable to 0 */ + writel(PLL_SS_EN, ®->ss.reg_clr); + + /* Program NUMERATOR and DENOMINATOR */ + writel((rate->mfn << 2), ®->num.reg); + writel((rate->mfd & GENMASK(29, 0)), ®->denom.reg); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* wait 5us */ + udelay(5); +#endif + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + udelay(100); +#endif + + pll_status = readl(®->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* check the MFN is updated */ + pll_status = readl(®->pll_status); + if ((pll_status & ~0x3) != (rate->mfn << 2)) { + debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n", + pll_status, rate->mfn); + return -EIO; + } +#endif + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + +int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en) +{ + struct ana_pll_dfs *dfs; + struct ana_pll_reg *reg; + u32 dfs_status; + u32 index; + + if (mfn > 3) + return -EINVAL; /* valid mfn 0-3 */ + + if (mfi < 2 || mfi > 255) + return -EINVAL; /* valid mfi 2-255 */ + + switch (pll_pfg) { + case SYS_PLL_PFD0: + reg = &ana_regs->sys_pll; + index = 0; + break; + case SYS_PLL_PFD1: + reg = &ana_regs->sys_pll; + index = 1; + break; + case SYS_PLL_PFD2: + reg = &ana_regs->sys_pll; + index = 2; + break; + default: + return -EPERM; + } + + dfs = ®->dfs[index]; + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set); + + /* disable DFS and output */ + writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT | + PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr); + + writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)), + &dfs->dfs_div.reg); + + writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set); + if (div2_en) + writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set); + writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* + * As HW expert said: after enabling the DFS, clock will start + * coming after 6 cycles output clock period. + * 5us is much bigger than expected, so it will be safe + */ + udelay(5); +#endif + + dfs_status = readl(®->dfs_status); + + if (!(dfs_status & (1 << index))) { + debug("DFS lock failed\n"); + return -EIO; + } + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr); + + return 0; +} + +int update_fracpll_mfn(enum ccm_clk_src pll, int mfn) +{ + struct ana_pll_reg *reg; + bool repoll = false; + u32 pll_status; + int count = 20; + + switch (pll) { + case AUDIO_PLL_CLK: + reg = &ana_regs->audio_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + printf("Invalid pll %u for update FRAC PLL MFN\n", pll); + return -EINVAL; + } + + if (readl(®->pll_status) & PLL_STATUS_PLL_LOCK) + repoll = true; + + mfn <<= 2; + writel(mfn, ®->num); + + if (repoll) { + do { + pll_status = readl(®->pll_status); + udelay(5); + count--; + } while (((pll_status & ~0x3) != (u32)mfn) && count > 0); + + if (count <= 0) { + printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n", + pll_status, mfn); + return -EIO; + } + } + + return 0; +} + +int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn) +{ + struct ana_pll_dfs *dfs; + u32 val; + u32 index; + + switch (pll_pfd) { + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + index = 0; + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + index = 1; + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + index = 2; + break; + default: + printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd); + return -EINVAL; + } + + dfs = &ana_regs->sys_pll.dfs[index]; + + val = readl(&dfs->dfs_div.reg); + val &= ~0x3; + val |= mfn & 0x3; + writel(val, &dfs->dfs_div.reg); + + return 0; +} + +/* return in khz */ +u32 get_clk_src_rate(enum ccm_clk_src source) +{ + u32 ctrl; + bool clk_on; + + switch (source) { + case ARM_PLL_CLK: + ctrl = readl(&ana_regs->arm_pll.ctrl.reg); + case AUDIO_PLL_CLK: + ctrl = readl(&ana_regs->audio_pll.ctrl.reg); + break; + case DRAM_PLL_CLK: + ctrl = readl(&ana_regs->dram_pll.ctrl.reg); + break; + case VIDEO_PLL_CLK: + ctrl = readl(&ana_regs->video_pll.ctrl.reg); + break; + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg); + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg); + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg); + break; + case OSC_24M_CLK: + return 24000; + default: + printf("Invalid clock source to get rate\n"); + return 0; + } + + if (ctrl & PLL_CTRL_HW_CTRL_SEL) { + /* When using HW ctrl, check OSCPLL */ + clk_on = ccm_clk_src_is_clk_on(source); + if (clk_on) + return decode_pll(source); + else + return 0; + } else { + /* controlled by pll registers */ + return decode_pll(source); + } +} + +u32 get_arm_core_clk(void) +{ + u32 val; + ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val); + + if (val & SHARED_GPR_A55_CLK_SEL_PLL) + return decode_pll(ARM_PLL_CLK) * 1000; + + return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT); +} + +void set_arm_core_max_clk(void) +{ + u32 speed; + + /* Increase ARM clock to max rate according to speed grade */ + speed = get_cpu_speed_grade_hz(); + + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, speed); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + +void set_arm_core_low_drive_clk(void) +{ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 900000000); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_arm_core_clk(); + case MXC_IPG_CLK: + return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT); + case MXC_CSPI_CLK: + return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT); + case MXC_ESDHC_CLK: + return ccm_clk_root_get_rate(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return ccm_clk_root_get_rate(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return ccm_clk_root_get_rate(USDHC3_CLK_ROOT); + case MXC_UART_CLK: + return ccm_clk_root_get_rate(LPUART1_CLK_ROOT); + case MXC_FLEXSPI_CLK: + return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT); + default: + return -1; + }; + + return -1; +}; + +int enable_i2c_clk(unsigned char enable, u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + if (enable) { + /* 24M */ + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_I2C1 + i2c_num, true); + } else { + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + } + + return 0; +} + +u32 imx_get_i2cclk(u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num); +} + +u32 get_lpuart_clk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + +void init_uart_clk(u32 index) +{ + switch(index) { + case LPUART1_CLK_ROOT: + /* 24M */ + ccm_lpcg_on(CCGR_URT1, false); + ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_URT1, true); + break; + default: + break; + } +} + +void init_clk_usdhc(u32 index) +{ + u32 div; + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + div = 3; /* 266.67 Mhz */ + else + div = 2; /* 400 Mhz */ + + switch (index) { + case 0: + ccm_lpcg_on(CCGR_USDHC1, 0); + ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC1, 1); + break; + case 1: + ccm_lpcg_on(CCGR_USDHC2, 0); + ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC2, 1); + break; + case 2: + ccm_lpcg_on(CCGR_USDHC3, 0); + ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC3, 1); + break; + default: + return; + }; +} + +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + ccm_lpcg_on(CCGR_USBC, 1); + } else { + ccm_lpcg_on(CCGR_USBC, 0); + } +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(ulong pll_val) +{ + configure_fracpll(DRAM_PLL_CLK, pll_val); +} + +void dram_enable_bypass(ulong clk_val) +{ + switch (clk_val) { + case MHZ(400): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); + break; + case MHZ(333): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3); + break; + case MHZ(200): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4); + break; + case MHZ(100): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8); + break; + default: + printf("No matched freq table %lu\n", clk_val); + return; + } + + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from PLL to CCM */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM); +} + +void dram_disable_bypass(void) +{ + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from CCM to PLL */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); +} +#endif + +void bus_clock_init_low_drive(void) +{ + /* Set A55 clk to 500M */ + ccm_clk_root_cfg(ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2); + /* Set A55 periphal to 200M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 133M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 133M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* WAKEUP_AXI to 200M */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + /* NIC to 250M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD0, 4); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +void bus_clock_init(void) +{ + /* Set A55 periphal to 333M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 200M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 200M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for generating MII clock at 2.5M */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + /* NIC to 400M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +int clock_init(void) +{ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + bus_clock_init_low_drive(); + set_arm_core_low_drive_clk(); + } else { + bus_clock_init(); + } + + /* allow for non-secure access */ + int i; + for (i = 0; i < OSCPLL_END; i++) + ccm_clk_src_tz_access(i, true, false, false); + + for (i = 0; i < CLK_ROOT_NUM; i++) + ccm_clk_root_tz_access(i, true, false, false); + + for (i = 0; i < CCGR_NUM; i++) + ccm_lpcg_tz_access(i, true, false, false); + + for (i = 0; i < SHARED_GPR_NUM; i++) + ccm_shared_gpr_tz_access(i, true, false, false); + + return 0; +} + +int set_clk_eqos(enum enet_freq type) +{ + u32 eqos_post_div; + + switch (type) { + case ENET_125MHZ: + eqos_post_div = 2; /* 250M clock */ + break; + case ENET_50MHZ: + eqos_post_div = 5; /* 100M clock */ + break; + case ENET_25MHZ: + eqos_post_div = 10; /* 50M clock*/ + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENETQOS, false); + + ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div); + ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + + /* enable clock */ + ccm_lpcg_on(CCGR_ENETQOS, true); + + return 0; +} + +u32 imx_get_eqos_csr_clk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +u32 imx_get_fecclk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +int set_clk_enet(enum enet_freq type) +{ + u32 div; + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENET1, false); + + switch (type) { + case ENET_125MHZ: + div = 2; /* 250Mhz */ + break; + case ENET_50MHZ: + div = 5; /* 100Mhz */ + break; + case ENET_25MHZ: + div = 10; /* 50Mhz */ + break; + default: + return -EINVAL; + } + + ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div); + ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20); +#endif + + /* enable clock */ + ccm_lpcg_on(CCGR_ENET1, true); + + return 0; +} + +void mxs_set_lcdclk(u32 base_addr, u32 freq) +{ + u32 div, i, krate, temp; + u32 best = 0, best_div = 0, best_pll = 0; + + debug("%s to set rate to %dkhz\n", __func__, freq); + + for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) { + krate = imx9_fracpll_tbl[i].rate / 1000; + div = (krate + freq - 1) / freq; + + if (div > 256) + continue; + + temp = krate / div; + if (best == 0 || temp > best) { + best = temp; + best_div = div; + best_pll = imx9_fracpll_tbl[i].rate; + } + } + + if (best == 0) { + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq); + return; + } + + /* Select to video PLL */ + debug("%s, best_pll = %u, div = %u\n", __func__, best_pll, best_div); + + configure_fracpll(VIDEO_PLL_CLK, best_pll); + ccm_clk_root_cfg(MEDIA_DISP_PIX_CLK_ROOT, VIDEO_PLL_CLK, best_div); +} + +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + + freq = decode_pll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(DRAM_PLL_CLK); + printf("DRAM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0); + printf("SYS_PLL_PFD0 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0_DIV2); + printf("SYS_PLL_PFD0_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1); + printf("SYS_PLL_PFD1 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1_DIV2); + printf("SYS_PLL_PFD1_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2); + printf("SYS_PLL_PFD2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2_DIV2); + printf("SYS_PLL_PFD2_DIV2 %8d MHz\n", freq / 1000); + freq = mxc_get_clock(MXC_ARM_CLK); + printf("ARM CORE %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_IPG_CLK); + printf("IPG %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_UART_CLK); + printf("UART3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_ESDHC_CLK); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_FLEXSPI_CLK); + printf("FLEXSPI %8d MHz\n", freq / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); +#endif + diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c new file mode 100644 index 0000000000..5748e28ff0 --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/ccm_regs.h> +#include <asm/global_data.h> +#include <linux/iopoll.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; + +static enum ccm_clk_src clk_root_mux[][4] = { + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/ + { OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */ +}; + +static struct clk_root_map clk_root_array[] = { + { ARM_A55_PERIPH_CLK_ROOT, 0 }, + { ARM_A55_MTR_BUS_CLK_ROOT, 2 }, + { ARM_A55_CLK_ROOT, 0 }, + { M33_CLK_ROOT, 2 }, + { SENTINEL_CLK_ROOT, 2 }, + { BUS_WAKEUP_CLK_ROOT, 2 }, + { BUS_AON_CLK_ROOT, 2 }, + { WAKEUP_AXI_CLK_ROOT, 0 }, + { SWO_TRACE_CLK_ROOT, 2 }, + { M33_SYSTICK_CLK_ROOT, 2 }, + { FLEXIO1_CLK_ROOT, 2 }, + { FLEXIO2_CLK_ROOT, 2 }, + { LPIT1_CLK_ROOT, 2 }, + { LPIT2_CLK_ROOT, 2 }, + { LPTMR1_CLK_ROOT, 2 }, + { LPTMR2_CLK_ROOT, 2 }, + { TPM1_CLK_ROOT, 3 }, + { TPM2_CLK_ROOT, 3 }, + { TPM3_CLK_ROOT, 3 }, + { TPM4_CLK_ROOT, 3 }, + { TPM5_CLK_ROOT, 3 }, + { TPM6_CLK_ROOT, 3 }, + { FLEXSPI1_CLK_ROOT, 0 }, + { CAN1_CLK_ROOT, 2 }, + { CAN2_CLK_ROOT, 2 }, + { LPUART1_CLK_ROOT, 2 }, + { LPUART2_CLK_ROOT, 2 }, + { LPUART3_CLK_ROOT, 2 }, + { LPUART4_CLK_ROOT, 2 }, + { LPUART5_CLK_ROOT, 2 }, + { LPUART6_CLK_ROOT, 2 }, + { LPUART7_CLK_ROOT, 2 }, + { LPUART8_CLK_ROOT, 2 }, + { LPI2C1_CLK_ROOT, 2 }, + { LPI2C2_CLK_ROOT, 2 }, + { LPI2C3_CLK_ROOT, 2 }, + { LPI2C4_CLK_ROOT, 2 }, + { LPI2C5_CLK_ROOT, 2 }, + { LPI2C6_CLK_ROOT, 2 }, + { LPI2C7_CLK_ROOT, 2 }, + { LPI2C8_CLK_ROOT, 2 }, + { LPSPI1_CLK_ROOT, 2 }, + { LPSPI2_CLK_ROOT, 2 }, + { LPSPI3_CLK_ROOT, 2 }, + { LPSPI4_CLK_ROOT, 2 }, + { LPSPI5_CLK_ROOT, 2 }, + { LPSPI6_CLK_ROOT, 2 }, + { LPSPI7_CLK_ROOT, 2 }, + { LPSPI8_CLK_ROOT, 2 }, + { I3C1_CLK_ROOT, 2 }, + { I3C2_CLK_ROOT, 2 }, + { USDHC1_CLK_ROOT, 0 }, + { USDHC2_CLK_ROOT, 0 }, + { USDHC3_CLK_ROOT, 0 }, + { SAI1_CLK_ROOT, 4 }, + { SAI2_CLK_ROOT, 4 }, + { SAI3_CLK_ROOT, 4 }, + { CCM_CKO1_CLK_ROOT, 6 }, + { CCM_CKO2_CLK_ROOT, 7 }, + { CCM_CKO3_CLK_ROOT, 6 }, + { CCM_CKO4_CLK_ROOT, 7 }, + { HSIO_CLK_ROOT, 2 }, + { HSIO_USB_TEST_60M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_80M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_480M_CLK_ROOT, 0 }, + { NIC_CLK_ROOT, 0 }, + { NIC_APB_CLK_ROOT, 2 }, + { ML_APB_CLK_ROOT, 2 }, + { ML_CLK_ROOT, 0 }, + { MEDIA_AXI_CLK_ROOT, 0 }, + { MEDIA_APB_CLK_ROOT, 2 }, + { MEDIA_LDB_CLK_ROOT, 5 }, + { MEDIA_DISP_PIX_CLK_ROOT, 5 }, + { CAM_PIX_CLK_ROOT, 5 }, + { MIPI_TEST_BYTE_CLK_ROOT, 5 }, + { MIPI_PHY_CFG_CLK_ROOT, 5 }, + { DRAM_ALT_CLK_ROOT, 0 }, + { DRAM_APB_CLK_ROOT, 1 }, + { ADC_CLK_ROOT, 2 }, + { PDM_CLK_ROOT, 4 }, + { TSTMR1_CLK_ROOT, 2 }, + { TSTMR2_CLK_ROOT, 2 }, + { MQS1_CLK_ROOT, 4 }, + { MQS2_CLK_ROOT, 4 }, + { AUDIO_XCVR_CLK_ROOT, 1 }, + { SPDIF_CLK_ROOT, 4 }, + { ENET_CLK_ROOT, 1 }, + { ENET_TIMER1_CLK_ROOT, 2 }, + { ENET_TIMER2_CLK_ROOT, 2 }, + { ENET_REF_CLK_ROOT, 1 }, + { ENET_REF_PHY_CLK_ROOT, 2 }, + { I3C1_SLOW_CLK_ROOT, 2 }, + { I3C2_SLOW_CLK_ROOT, 2 }, + { USB_PHY_BURUNIN_CLK_ROOT, 2 }, + { PAL_CAME_SCAN_CLK_ROOT, 8 }, +}; + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_oscplls[oscpll].direct); + else + writel(0, &ccm_reg->clk_oscplls[oscpll].direct); + + return 0; +} + +/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */ +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) { + writel(authen | CCM_AUTHEN_AUTO_CTRL, + &ccm_reg->clk_oscplls[oscpll].authen); + } else + writel((authen & ~CCM_AUTHEN_AUTO_CTRL), + &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */ + if (authen & CCM_AUTHEN_AUTO_CTRL) + return -EPERM; + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, + &ccm_reg->clk_oscplls[oscpll].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), + &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (oscpll >= OSCPLL_END || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1); + } else { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0); + } + + return 0; +} + +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll) +{ + return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1); +} + +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div) +{ + int i; + int ret; + u32 mux, status; + + if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0) + return -EINVAL; + + mux = clk_root_array[clk_root_id].mux_type; + + for (i = 0; i < 4; i++) { + if (src == clk_root_mux[mux][i]) + break; + } + + if (i == 4) { + printf("Invalid source [%u] for this clk root\n", src); + return -EINVAL; + } + + writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control); + + ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status, + !(status & CLK_ROOT_STATUS_CHANGING), 200000); + if (ret) + printf("%s: failed, status: 0x%x\n", __func__, + readl(&ccm_reg->clk_roots[clk_root_id].status0)); + + return ret; +}; + +u32 ccm_clk_root_get_rate(u32 clk_root_id) +{ + u32 mux, status, div, rate; + enum ccm_clk_src src; + + if (clk_root_id >= CLK_ROOT_NUM) + return 0; + + status = readl(&ccm_reg->clk_roots[clk_root_id].control); + + if (status & CLK_ROOT_STATUS_OFF) + return 0; /* clock is off */ + + mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT; + div = status & CLK_ROOT_DIV_MASK; + src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux]; + + rate = get_clk_src_rate(src) * 1000; + + return rate / (div + 1); /* return in hz */ +} + +int ccm_clk_root_tz_access(u32 clk_root_id, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (clk_root_id >= CLK_ROOT_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_roots[clk_root_id].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_roots[clk_root_id].authen); + + return 0; +} + +int ccm_lpcg_on(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_lpcgs[lpcg].direct); + else + writel(0, &ccm_reg->clk_lpcgs[lpcg].direct); + + return 0; + +} + +int ccm_lpcg_lpm(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, + &ccm_reg->clk_lpcgs[lpcg].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), + &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (lpcg >= CCGR_NUM || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1); + } else { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0); + } + + return 0; +} + +bool ccm_lpcg_is_clk_on(u32 lpcg) +{ + return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1); +} + +int ccm_lpcg_tz_access(u32 lpcg, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_shared_gpr_set(u32 gpr, u32 val) +{ + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + +int ccm_shared_gpr_get(u32 gpr, u32 *val) +{ + if (gpr >= SHARED_GPR_NUM || !val) + return -EINVAL; + + *val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + + +int ccm_shared_gpr_tz_access(u32 gpr, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen); + + return 0; +} diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c new file mode 100644 index 0000000000..721e77193e --- /dev/null +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <asm/mach-imx/sys_proto.h> +#include <command.h> +#include <elf.h> +#include <imx_sip.h> +#include <linux/arm-smccc.h> +#include <linux/compiler.h> +#include <cpu_func.h> + +int arch_auxiliary_core_check_up(u32 core_id) +{ + struct arm_smccc_res res; + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, + 0, 0, 0, 0, &res); + + return res.a0; +} + +int arch_auxiliary_core_down(u32 core_id) +{ + struct arm_smccc_res res; + + printf("## Stopping auxiliary core\n"); + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0, + 0, 0, 0, 0, &res); + + return 0; +} + +int arch_auxiliary_core_up(u32 core_id, ulong addr) +{ + struct arm_smccc_res res; + u32 stack, pc; + + if (!addr) + return -EINVAL; + + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + + printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, + 0, 0, 0, 0, &res); + + return 0; +} + +/* + * To i.MX6SX and i.MX7D, the image supported by bootaux needs + * the reset vector at the head for the image, with SP and PC + * as the first two words. + * + * Per the cortex-M reference manual, the reset vector of M4/M7 needs + * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses + * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset + * vector with getting the PC and SP from image and filling them to + * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself. + * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4/M7 TCMUL/IDTCM. + */ +static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + int ret, up; + u32 core = 0; + u32 stop = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + if (argc > 3) + stop = simple_strtoul(argv[3], NULL, 10); + + up = arch_auxiliary_core_check_up(core); + if (up) { + printf("## Auxiliary core is already up\n"); + return CMD_RET_SUCCESS; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + if (!addr) + return CMD_RET_FAILURE; + + ret = arch_auxiliary_core_up(core, addr); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret, up; + + up = arch_auxiliary_core_check_up(0); + if (!up) { + printf("## Auxiliary core is already down\n"); + return CMD_RET_SUCCESS; + } + + ret = arch_auxiliary_core_down(0); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux, + "Start auxiliary core", + "<address> [<core>]\n" + " - start auxiliary core [<core>] (default 0),\n" + " at address <address>\n" +); + +U_BOOT_CMD( + bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, + "Start auxiliary core", + "<address> [<core>]\n" + " - start auxiliary core [<core>] (default 0),\n" + " at address <address>\n" +); diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S new file mode 100644 index 0000000000..1dc1dbfcdd --- /dev/null +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 256 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: +#ifndef CONFIG_SPL_BUILD + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 +#endif + /* Returns */ + b save_boot_params_ret diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c new file mode 100644 index 0000000000..02edced9aa --- /dev/null +++ b/arch/arm/mach-imx/imx9/soc.c @@ -0,0 +1,1186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/arch/imx-regs.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/syscounter.h> +#include <asm/armv8/mmu.h> +#include <dm/uclass.h> +#include <env.h> +#include <env_internal.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/bitops.h> +#include <asm/setup.h> +#include <asm/bootm.h> +#include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/optee.h> +#include <linux/delay.h> +#include <fuse.h> +#include <imx_thermal.h> +#include <thermal.h> +#include <imx_sip.h> +#include <linux/arm-smccc.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rom_api *g_rom_api = (struct rom_api *)0x1980; + +enum boot_device get_boot_device(void) +{ + volatile gd_t *pgd = gd; + int ret; + u32 boot; + u16 boot_type; + u8 boot_instance; + enum boot_device boot_dev = SD1_BOOT; + + ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, + ((uintptr_t)&boot) ^ QUERY_BT_DEV); + set_gd(pgd); + + if (ret != ROM_API_OKAY) { + puts("ROMAPI: failure at query_boot_info\n"); + return -1; + } + + boot_type = boot >> 16; + boot_instance = (boot >> 8) & 0xff; + + switch (boot_type) { + case BT_DEV_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BT_DEV_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BT_DEV_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BT_DEV_TYPE_FLEXSPINOR: + boot_dev = QSPI_BOOT; + break; + case BT_DEV_TYPE_USB: + boot_dev = boot_instance + USB_BOOT; + break; + default: + break; + } + + debug("boot dev %d\n", boot_dev); + + return boot_dev; +} + +bool is_usb_boot(void) +{ + enum boot_device bt_dev = get_boot_device(); + return (bt_dev == USB_BOOT || bt_dev == USB2_BOOT); +} + +void disconnect_from_pc(void) +{ + enum boot_device bt_dev = get_boot_device(); + + if (bt_dev == USB_BOOT) + writel(0x0, USB1_BASE_ADDR + 0x140); + else if (bt_dev == USB2_BOOT) + writel(0x0, USB2_BASE_ADDR + 0x140); + + return; +} + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_get_env_dev(void) +{ + volatile gd_t *pgd = gd; + int ret; + u32 boot; + u16 boot_type; + u8 boot_instance; + + ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, + ((uintptr_t)&boot) ^ QUERY_BT_DEV); + set_gd(pgd); + + if (ret != ROM_API_OKAY) { + puts("ROMAPI: failure at query_boot_info\n"); + return CONFIG_SYS_MMC_ENV_DEV; + } + + boot_type = boot >> 16; + boot_instance = (boot >> 8) & 0xff; + + debug("boot_type %d, instance %d\n", boot_type, boot_instance); + + /* If not boot from sd/mmc, use default value */ + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + + return board_mmc_get_env_dev(boot_instance); + +} +#endif + +#ifdef CONFIG_USB_PORT_AUTO +int board_usb_gadget_port_auto(void) +{ + enum boot_device bt_dev = get_boot_device(); + int usb_boot_index = 0; + + if (bt_dev == USB2_BOOT) + usb_boot_index = 1; + + printf("auto usb %d\n", usb_boot_index); + + return usb_boot_index; +} +#endif + +u32 get_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + u32 grade; + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + val >>= 6; + val &= 0xf; + + speed = 2300000000 - val * 100000000; + + if (is_imx93()) { + grade = get_cpu_temp_grade(NULL, NULL); + if (grade == TEMP_INDUSTRIAL) + max_speed = 1500000000; + else + max_speed = 1700000000; + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + } + + return speed; +} + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + + val >>= 4; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + +static void set_cpu_info(struct sentinel_get_info_data *info) +{ + gd->arch.soc_rev = info->soc; + gd->arch.lifecycle = info->lc; + memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); +} + +static u32 get_cpu_variant_type(u32 type) +{ + /* word 19 */ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + bool npu_disable = !!(val & BIT(13)); + bool core1_disable = !!(val & BIT(15)); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val2 & pack_9x9_fused) == pack_9x9_fused) + type = MXC_CPU_IMX9322; + + if (npu_disable && core1_disable) + return type + 3; + else if (npu_disable) + return type + 2; + else if (core1_disable) + return type + 1; + + return type; +} + +u32 get_cpu_rev(void) +{ + u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; + return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) | + (CHIP_REV_1_0 + rev); +} + +#define UNLOCK_WORD 0xD928C520 /* unlock word */ +#define REFRESH_WORD 0xB480A602 /* refresh word */ + +static void disable_wdog(void __iomem *wdog_base) +{ + u32 val_cs = readl(wdog_base + 0x00); + + if (!(val_cs & 0x80)) + return; + + /* default is 32bits cmd */ + writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */ + + if (!(val_cs & 0x800)) { + writel(UNLOCK_WORD, (wdog_base + 0x04)); + while (!(readl(wdog_base + 0x00) & 0x800)) + ; + } + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */ + + while (!(readl(wdog_base + 0x00) & 0x400)) + ; +} + +void init_wdog(void) +{ + u32 src_val; + + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + disable_wdog((void __iomem *)WDG5_BASE_ADDR); + + src_val = readl(0x54460018); /* reset mask */ + src_val &= ~0x1c; + writel(src_val, 0x54460018); +} + +static struct mm_region imx93_mem_map[] = { + { + /* ROM */ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* TCM */ + .virt = 0x201c0000UL, + .phys = 0x201c0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCRAM */ + .virt = 0x20480000UL, + .phys = 0x20480000UL, + .size = 0xA0000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Flexible Serial Peripheral Interface */ + .virt = 0x28000000UL, + .phys = 0x28000000UL, + .size = 0x30000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* empty entrie to split table entry 5 if needed when TEEs are used */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx93_mem_map; + +static unsigned int imx9_find_dram_entry_in_mem_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++) + if (imx93_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + return i; + + hang(); /* Entry not found, this must never happen. */ +} + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch + * If OPTEE does not run, still update the MMU table according to dram banks structure + * to set correct dram size from board_phys_sdram_size + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx93_mem_map for DRAM1 + */ + int entry = imx9_find_dram_entry_in_mem_map(); + u64 attrs = imx93_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && + entry < ARRAY_SIZE(imx93_mem_map)) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx93_mem_map[entry].phys, imx93_mem_map[entry].size); + i++; entry++; + } + + icache_enable(); + dcache_enable(); +} + +__weak int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = PHYS_SDRAM_SIZE; + +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + +int dram_init(void) +{ + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size, sdram_b2_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + sdram_b2_size = sdram_size - 0x80000000; + } else { + sdram_b1_size = sdram_size; + sdram_b2_size = 0; + } + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_b1_size; + } + + if (sdram_b2_size) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = 0x100000000UL; + gd->bd->bi_dram[bank].size = sdram_b2_size; + } + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size; + ret = board_phys_sdram_size(&sdram_size); + if (!ret) { + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + } else { + sdram_b1_size = sdram_size; + } + + if (rom_pointer[1]) { + /* We will relocate u-boot to Top of dram1. Tee position has two cases: + * 1. At the top of dram1, Then return the size removed optee size. + * 2. In the middle of dram1, return the size of dram1. + */ + if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size)) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + } + + return sdram_b1_size; + } else { + return PHYS_SDRAM_SIZE; + } +} + + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + u32 val[2] = {}; + int ret; + + if (dev_id == 0) { + ret = fuse_read(39, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 8; + mac[1] = val[1]; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + + } else { + ret = fuse_read(39, 5, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 24; + mac[1] = val[1] >> 16; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + } + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: + memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); +} + +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX93: + return "93(52)";/* iMX93 Dual core with NPU */ + case MXC_CPU_IMX9351: + return "93(51)";/* iMX93 Single core with NPU */ + case MXC_CPU_IMX9332: + return "93(32)";/* iMX93 Dual core without NPU */ + case MXC_CPU_IMX9331: + return "93(31)";/* iMX93 Single core without NPU */ + case MXC_CPU_IMX9322: + return "93(22)";/* iMX93 9x9 Dual core */ + case MXC_CPU_IMX9321: + return "93(21)";/* iMX93 9x9 Single core */ + case MXC_CPU_IMX9312: + return "93(12)";/* iMX93 9x9 Dual core without NPU */ + case MXC_CPU_IMX9311: + return "93(11)";/* iMX93 9x9 Single core without NPU */ + default: + return "??"; + } +} + +#define SRC_SRSR_RESET_CAUSE_NUM 16 +const char *reset_cause[SRC_SRSR_RESET_CAUSE_NUM] = { + "POR ", + "JTAG ", + "IPP USER ", + "WDOG1 ", + "WDOG2 ", + "WDOG3 ", + "WDOG4 ", + "WDOG5 ", + "TEMPSENSE ", + "CSU ", + "JTAG_SW ", + "M33_REQ ", + "M33_LOCKUP " + "UNK ", + "UNK ", + "UNK ", +}; + +static void save_reset_cause(void) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr = readl(&src->srsr); + writel(srsr, &src->srsr); /* clear srsr in sec mode */ + + /* Save value to GPR1 to pass to nonsecure */ + writel(srsr, &src->gpr[0]); +} + +static const char *get_reset_cause(u32 *srsr_ret) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr; + u32 i; + + srsr = readl(&src->gpr[0]); + if (srsr_ret) + *srsr_ret = srsr; + + for (i = SRC_SRSR_RESET_CAUSE_NUM; i > 0; i--) { + if (srsr & (1 << (i - 1))) + return reset_cause[i - 1]; + } + + return "unknown reset"; +} + +int print_cpuinfo(void) +{ + u32 cpurev, max_freq; + int minc, maxc; + u32 ssrs_ret; + + cpurev = get_cpu_rev(); + + printf("CPU: i.MX%s rev%d.%d", + get_imx_type((cpurev & 0x1FF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); + + max_freq = get_cpu_speed_grade_hz(); + if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { + printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + } else { + printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + } + + puts("CPU: "); + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + puts("Automotive temperature grade "); + break; + case TEMP_INDUSTRIAL: + puts("Industrial temperature grade "); + break; + case TEMP_EXTCOMMERCIAL: + puts("Extended Consumer temperature grade "); + break; + default: + puts("Consumer temperature grade "); + break; + } + printf("(%dC to %dC)", minc, maxc); + +#if defined(CONFIG_IMX_TMU) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + + if (!ret) + printf(" at %dC", temp); + else + debug(" - invalid sensor data\n"); + } else { + debug(" - invalid sensor device\n"); + } +#endif + puts("\n"); + + printf("Reset cause: %s", get_reset_cause(&ssrs_ret)); + printf("(0x%x)\n", ssrs_ret); + + return 0; +} + +void build_info(void) +{ + u32 fw_version, sha1, res, status; + int ret; + + printf("\nBuildInfo:\n"); + + ret = ahab_get_fw_status(&status, &res); + if (ret) { + printf(" - ELE firmware status failed %d, 0x%x\n", ret, res); + } else if ((status & 0xff) == 1) { + ret = ahab_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf(" - ELE firmware version failed %d, 0x%x\n", ret, res); + } else { + printf(" - ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000ff00)) >> 8, + (fw_version & (0x000000ff)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } + } else { + printf(" - ELE firmware not included\n"); + } + puts("\n"); +} + +int arch_misc_init(void) +{ + build_info(); + return 0; +} + +static int delete_fdt_nodes(void *blob, const char *const nodes_path[], int size_array) +{ + int i = 0; + int rc; + int nodeoff; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path[i]); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path[i], fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path[i]); + } + } + + return 0; +} + +static int disable_npu_nodes(void *blob) +{ + static const char * const nodes_path_npu[] = { + "/ethosu", + "/reserved-memory/ethosu_region@C0000000" + }; + + return delete_fdt_nodes(blob, nodes_path_npu, ARRAY_SIZE(nodes_path_npu)); +} + +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/cpu-thermal/cooling-maps/map0" + }; + + int nodeoff, cnt, i, ret, j; + u32 cooling_dev[6]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 6); + if (cnt < 0) + continue; + + if (cnt != 6) + printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt); + + for (j = 0; j < cnt; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (6 - disabled_cores * 3)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static int disable_cpu_nodes(void *blob, u32 disabled_cores) +{ + u32 i = 0; + int rc; + int nodeoff; + char nodes_path[32]; + + for (i = 1; i <= disabled_cores; i++) { + + sprintf(nodes_path, "/cpus/cpu@%u00", i); + + nodeoff = fdt_path_offset(blob, nodes_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path, fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path); + } + } + + disable_thermal_cpu_nodes(blob, disabled_cores); + + return 0; +} + +struct low_drive_freq_entry { + const char *node_path; + u32 clk; + u32 new_rate; +}; + +static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 new_rate) +{ +#define MAX_ASSIGNED_CLKS 8 + int cnt, j; + u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/ + + cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates", + assignedclks, MAX_ASSIGNED_CLKS); + if (cnt > 0) { + if (cnt <= clk_index) + return -ENOENT; + + if (assignedclks[clk_index] <= new_rate) + return 0; + + assignedclks[clk_index] = new_rate; + for (j = 0; j < cnt; j++) + assignedclks[j] = cpu_to_fdt32(assignedclks[j]); + + return fdt_setprop(fdt, node_off, "assigned-clock-rates", &assignedclks, cnt * sizeof(u32)); + } + + return -ENOENT; +} + +static int low_drive_freq_update(void *blob) +{ + int nodeoff, ret; + int i; + + /* Update kernel dtb clocks for low drive mode */ + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 2, 200000000}, + {"/soc@0/bus@42800000/camera/isi@4ae40000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(blob, table[i].node_path); + if (nodeoff >= 0) { + ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, table[i].new_rate); + if (!ret) + printf("%s freq updated\n", table[i].node_path); + } + } + + return 0; +} + +#ifdef CONFIG_OF_BOARD_FIXUP +#ifndef CONFIG_SPL_BUILD +int board_fix_fdt(void *fdt) +{ + /* Update u-boot dtb clocks for low drive mode */ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + int nodeoff; + int i; + + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(fdt, table[i].node_path); + if (nodeoff >= 0) + low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk, table[i].new_rate); + } + } + + return 0; +} +#endif +#endif + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311()) + disable_cpu_nodes(blob, 1); + + if (is_imx9332() || is_imx9331() || is_imx9312() || is_imx9311()) + disable_npu_nodes(blob); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + low_drive_freq_update(blob); + + return ft_add_optee_node(blob, bd); +} + +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +void get_board_serial(struct tag_serialnr *serialnr) +{ + printf("UID: 0x%x 0x%x 0x%x 0x%x\n", + gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]); + + serialnr->low = gd->arch.uid[0]; + serialnr->high = gd->arch.uid[3]; +} +#endif + +int arch_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Disable wdog */ + init_wdog(); + + clock_init(); + + trdc_early_init(); + + /* Save SRC SRSR to GPR1 and clear it */ + save_reset_cause(); + } + + return 0; +} + +int arch_cpu_init_dm(void) +{ + struct udevice *devp; + int node, ret; + u32 res; + struct sentinel_get_info_data info; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + if (ret) + return ret; + + ret = ahab_get_info(&info, &res); + if (ret) + return ret; + + set_cpu_info(&info); + + return 0; +} + +#ifdef CONFIG_ARCH_EARLY_INIT_R +int arch_early_init_r(void) +{ + struct udevice *devp; + int node, ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + if (ret) { + printf("could not get S400 mu %d\n", ret); + return ret; + } + + return 0; +} +#endif + +int timer_init(void) +{ +#ifdef CONFIG_SPL_BUILD + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; + unsigned long freq = readl(&sctr->cntfid0); + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_device dev = get_boot_device(); + enum env_location env_loc = ENVL_UNKNOWN; + + if (prio) + return env_loc; + + switch (dev) { +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH + case QSPI_BOOT: + env_loc = ENVL_SPI_FLASH; + break; +#endif +#ifdef CONFIG_ENV_IS_IN_MMC + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + env_loc = ENVL_MMC; + break; +#endif + default: +#if defined(CONFIG_ENV_IS_NOWHERE) + env_loc = ENVL_NOWHERE; +#endif + break; + } + + return env_loc; +} + +int mix_power_init(enum mix_power_domain pd) +{ + enum src_mix_slice_id mix_id; + enum src_mem_slice_id mem_id; + struct src_mix_slice_regs *mix_regs; + struct src_mem_slice_regs *mem_regs; + struct src_general_regs *global_regs; + u32 scr, val; + + switch (pd) { + case MIX_PD_MEDIAMIX: + mix_id = SRC_MIX_MEDIA; + mem_id = SRC_MEM_MEDIA; + scr = BIT(5); + + /* Enable S400 handshake */ + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + + setbits_le32(&s_regs->lp_handshake[0], BIT(13)); + break; + case MIX_PD_MLMIX: + mix_id = SRC_MIX_ML; + mem_id = SRC_MEM_ML; + scr = BIT(4); + break; + case MIX_PD_DDRMIX: + mix_id = SRC_MIX_DDRMIX; + mem_id = SRC_MEM_DDRMIX; + scr = BIT(6); + break; + default: + return -EINVAL; + } + + mix_regs = (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (mix_id + 1)); + mem_regs = (struct src_mem_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x3800 + 0x400 * mem_id); + global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + + /* Allow NS to set it */ + setbits_le32(&mix_regs->authen_ctrl, BIT(9)); + + clrsetbits_le32(&mix_regs->psw_ack_ctrl[0], BIT(28), BIT(29)); + + /* mix reset will be held until boot core write this bit to 1 */ + setbits_le32(&global_regs->scr, scr); + + /* Enable mem in Low power auto sequence */ + setbits_le32(&mem_regs->mem_ctrl, BIT(2)); + + /* Set the power down state */ + val = readl(&mix_regs->func_stat); + if (val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT) { + /* The mix is default power off, power down it to make PDN_SFT bit + * aligned with FUNC STAT + */ + setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + + /* Since PSW_STAT is 1, can't be used for power off status (SW_CTRL BIT31 set)) */ + /* Check the MEM STAT change to ensure SSAR is completed */ + while (!(val & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT)) { + val = readl(&mix_regs->func_stat); + } + + /* wait few ipg clock cycles to ensure FSM done and power off status is correct */ + /* About 5 cycles at 24Mhz, 1us is enough */ + udelay(1); + } else { + /* The mix is default power on, Do mix power cycle */ + setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + while (!(val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT)) { + val = readl(&mix_regs->func_stat); + } + } + + /* power on */ + clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT) { + val = readl(&mix_regs->func_stat); + } + + return 0; +} + +void disable_isolation(void) +{ + struct src_general_regs *global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + /* clear isolation for usbphy, dsi, csi*/ + writel(0x0, &global_regs->sp_iso_ctrl); +} + +void soc_power_init(void) +{ + mix_power_init(MIX_PD_MEDIAMIX); + mix_power_init(MIX_PD_MLMIX); + + disable_isolation(); +} + +bool m33_is_rom_kicked(void) +{ + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + + if (!(readl(&s_regs->m33_cfg) & BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK)) + return true; + + return false; +} + +int m33_prepare(void) +{ + struct src_mix_slice_regs *mix_regs = + (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1)); + struct src_general_regs *global_regs = + (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + u32 val; + + /* Allow NS to set it */ + setbits_le32(&mix_regs->authen_ctrl, BIT(9)); + + if (m33_is_rom_kicked()) + return -EPERM; + + /* Release reset of M33 */ + setbits_le32(&global_regs->scr, BIT(0)); + + /* Check the reset released in M33 MIX func stat */ + val = readl(&mix_regs->func_stat); + while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) { + val = readl(&mix_regs->func_stat); + } + + /* Because CPUWAIT is default set, so M33 won't run, Clear it when kick M33 */ + /* Release Sentinel TROUT */ + ahab_release_m33_trout(); + + /* Mask WDOG1 IRQ from A55, we use it for M33 reset */ + setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6)); + + /* Turn on WDOG1 clock */ + ccm_lpcg_on(CCGR_WDG1, 1); + + /* Set sentinel LP handshake for M33 reset */ + setbits_le32(&s_regs->lp_handshake[0], BIT(6)); + + /* Clear M33 TCM for ECC */ + memset((void *)(ulong)0x201e0000, 0, 0x40000); + + return 0; +} diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c new file mode 100644 index 0000000000..bb137a7912 --- /dev/null +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <div64.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/mu_hal.h> + +#define DID_NUM 16 +#define MBC_MAX_NUM 4 +#define MRC_MAX_NUM 2 +#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF) +#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F) + +struct mbc_mem_dom { + u32 mem_glbcfg[4]; + u32 nse_blk_index; + u32 nse_blk_set; + u32 nse_blk_clr; + u32 nsr_blk_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + u32 mem0_blk_cfg_w[64]; + u32 mem0_blk_nse_w[16]; + u32 mem1_blk_cfg_w[8]; + u32 mem1_blk_nse_w[2]; + u32 mem2_blk_cfg_w[8]; + u32 mem2_blk_nse_w[2]; + u32 mem3_blk_cfg_w[8]; + u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ + u32 reserved[2]; +}; + +struct mrc_rgn_dom { + u32 mrc_glbcfg[4]; + u32 nse_rgn_indirect; + u32 nse_rgn_set; + u32 nse_rgn_clr; + u32 nse_rgn_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + u32 rgn_nse; + u32 reserved2[15]; +}; + +struct mda_inst { + u32 mda_w[8]; +}; + +struct trdc_mgr { + u32 trdc_cr; + u32 res0[59]; + u32 trdc_hwcfg0; + u32 trdc_hwcfg1; + u32 res1[450]; + struct mda_inst mda[8]; + u32 res2[15808]; +}; + +struct trdc_mbc { + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc { + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + + +int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids, u8 did, u8 pe, u8 pidm, u8 pid) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + u32 val = readl(mda_w); + + if (val & BIT(29)) /* non-cpu */ + return -EINVAL; + + val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) | ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) | (did & 0xf); + + writel(val, mda_w); + + return 0; +} + +int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, bool did_bypass, u8 sa, u8 pa, u8 did) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + u32 val = readl(mda_w); + + if (!(val & BIT(29))) /* cpu */ + return -EINVAL; + + val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf); + if (did_bypass) + val |= BIT(8); + + writel(val, mda_w); + + return 0; +} + +static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + + if (mbc_x >= mbc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_x; +} + +static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0); + + if (mrc_x >= mrc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x; +} + +int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + debug("mbc 0x%lx\n", (ulong)mbc_dom); + + writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]); + + return 0; +} + +int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w, *nse_w; + u32 index, offset, val; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + debug("mbc 0x%lx\n", (ulong)mbc_dom); + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = readl((void __iomem *)cfg_w); + + val &= ~(0xFU << offset); + + /* MBC0-3 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MBC0_MEMN_GLBAC0 + */ + if (sec_access) { + val |= ((0x0 | (glbac_id & 0x7)) << offset); + writel(val, (void __iomem *)cfg_w); + } else { + val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */ + writel(val, (void __iomem *)cfg_w); + } + + return 0; +} + +int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + debug("mrc_dom 0x%lx\n", (ulong)mrc_dom); + + writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]); + + return 0; +} + +int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + u32 *desc_w; + u32 start, end; + u32 i, free = 8;; + bool vld, hit = false; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mrc_dom = &mrc_base->mrc_dom[dom_x]; + + addr_start &= ~0x3fff; + addr_end &= ~0x3fff; + + debug("mrc_dom 0x%lx\n", (ulong)mrc_dom); + + for (i = 0; i < 8; i++) { + desc_w = &mrc_dom->rgn_desc_words[i][0]; + + debug("desc_w 0x%lx\n", (ulong)desc_w); + + start = readl((void __iomem *)desc_w) & (~0x3fff); + end = readl((void __iomem *)(desc_w + 1)); + vld = end & 0x1; + end = end & (~0x3fff); + + if (start == 0 && end == 0 && !vld && free >= 8) + free = i; + + /* Check all the region descriptors, even overlap */ + if (addr_start >= end || addr_end <= start || !vld) + continue; + + /* MRC0,1 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MRCx_MEMN_GLBAC0 + */ + if (sec_access) { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1)); + } + + if (addr_start >= start && addr_end <= end) + hit = true; + } + + if (!hit) { + if (free >= 8) + return -EFAULT; + + desc_w = &mrc_dom->rgn_desc_words[free][0]; + + debug("free desc_w 0x%lx\n", (ulong)desc_w); + debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1); + + if (sec_access) { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(addr_end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1)); + } + } + + return 0; +} + +bool trdc_mrc_enabled(ulong trdc_base) +{ + return (!!(readl((void __iomem *)trdc_base) & 0x8000)); +} + +bool trdc_mbc_enabled(ulong trdc_base) +{ + return (!!(readl((void __iomem *)trdc_base) & 0x4000)); +} + +int release_rdc(u8 xrdc) +{ + ulong s_mu_base = 0x47520000UL; + struct sentinel_msg msg; + int ret; + u32 rdc_id; + + switch (xrdc) { + case 0: + rdc_id = 0x74; + break; + case 1: + rdc_id = 0x78; + break; + case 2: + rdc_id = 0x82; + break; + case 3: + rdc_id = 0x86; + break; + default: + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_RELEASE_RDC_REQ; + msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */ + + mu_hal_init(s_mu_base); + mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); + mu_hal_sendmsg(s_mu_base, 1, msg.data[0]); + + ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); + if (!ret) { + ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); + if (!ret) { + if ((msg.data[0] & 0xff) == 0xd6) + return 0; + } + + return -EIO; + } + + return ret; +} + +void trdc_early_init(void) +{ + int ret = 0, i; + ret |= release_rdc(0); + ret |= release_rdc(2); + ret |= release_rdc(1); + ret |= release_rdc(3); + + if (!ret) { + /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */ + trdc_mbc_set_control(0x49010000, 3, 0, 0x7700); + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0); + } + } +} + +void trdc_init(void) +{ + /* TRDC mega */ + if (trdc_mrc_enabled(0x49010000)) { + + /* DDR */ + trdc_mrc_set_control(0x49010000, 0, 0, 0x7777); + + /* S400*/ + trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0); + + /* MTR */ + trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0); + + /* M33 */ + trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0); + + /* A55*/ + trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0); + + /* For USDHC1 to DDR, USDHC1 is default force to non-secure */ + trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0); + + /* For USDHC2 to DDR, USDHC2 is default force to non-secure */ + trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0); + + /* eDMA */ + trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0); + + /*CoreSight, TestPort*/ + trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0); + + /* DAP */ + trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0); + + /*SoC masters */ + trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0); + + /*USB*/ + trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0); + + } +} + +#if DEBUG +int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + printf("mbc_dom %u glbac %u: 0x%x\n", mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id])); + + return 0; +} + +int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w; + + if (mbc_base == 0) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[word]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[word]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[word]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[word]; + break; + default: + return -EINVAL; + }; + + printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n", mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w)); + + return 0; +} + +int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + printf("mrc_dom %u glbac %u: 0x%x\n", mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id])); + + return 0; +} + +void trdc_dump(void) +{ + u32 i; + printf("TRDC AONMIX MBC\n"); + + trdc_mbc_control_dump(0x44270000, 0, 0); + trdc_mbc_control_dump(0x44270000, 1, 0); + + for (i = 0; i < 11; i++) { + trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i); + } + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i); + } + + for (i = 0; i < 4; i++) { + trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i); + } + for (i = 0; i < 4; i++) { + trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i); + } + + printf("TRDC WAKEUP MBC\n"); + + trdc_mbc_control_dump(0x42460000, 0, 0); + trdc_mbc_control_dump(0x42460000, 1, 0); + + for (i = 0; i < 15; i++) { + trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i); + } + trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0); + trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0); + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i); + } + trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0); + trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0); + trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0); + + printf("TRDC NICMIX MBC\n"); + + trdc_mbc_control_dump(0x49010000, 0, 0); + trdc_mbc_control_dump(0x49010000, 1, 0); + trdc_mbc_control_dump(0x49010000, 2, 0); + trdc_mbc_control_dump(0x49010000, 3, 0); + + for (i = 0; i < 7; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i); + } + + for (i = 0; i < 6; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i); + } + + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i); + } + + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i); + } + + for (i = 0; i < 3; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i); + } + + for (i = 0; i < 3; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i); + } +} +#endif diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 7012ae9d7b..0c2987dece 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -10,6 +10,10 @@ #include <asm/mach-imx/boot_mode.h> #include <env.h> +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + __weak int board_mmc_get_env_dev(int devno) { return devno; diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index c24d8279ed..a171e7b54d 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2022 NXP */ #include <common.h> @@ -10,6 +10,11 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/module_fuse.h> #include <linux/errno.h> +#include <command.h> +#include <hexdump.h> +#include <dm.h> +#include <malloc.h> +#include <rng.h> static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) @@ -300,6 +305,48 @@ add_status: } } + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) { + /*Random number generation through RNG driver*/ + struct udevice *dev; + void *buf; + char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; + int ret = 0; + int nodeoff = fdt_node_offset_by_compatible(blob, -1, "fsl,imx28-dcp"); + + if (nodeoff < 0) { + printf("node to update the SoC serial number is not found.\n"); + return nodeoff; + } + rc = uclass_get_device(UCLASS_RNG, 0, &dev); + if (rc || !dev) { + printf("No RNG device\n"); + return rc; + } + + buf = malloc(16); + if (!buf) { + printf("Out of memory\n"); + return -ENOMEM; + } + + for (int i = 0; i < 2; i++) { + ret = dm_rng_read(dev, buf, 16); + if (ret) { + printf("Reading RNG failed\n"); + goto err; + } + + ret = fdt_setprop(blob, nodeoff, keys[i], buf, 16); + if (ret < 0) { + printf("WARNING: could not set %s key handle %s.\n", keys[i], fdt_strerror(ret)); + goto err; + } + } +err: + free(buf); + return ret; + } + return 0; } #endif diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 3e538754d9..9bf16119c2 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -31,6 +31,8 @@ #include <hang.h> #include <cpu_func.h> #include <env.h> +#include<dm/device-internal.h> +#include<dm/lists.h> DECLARE_GLOBAL_DATA_PTR; @@ -1005,6 +1007,20 @@ int arch_misc_init(void) if (ret) printf("Failed to initialize caam_jr: %d\n", ret); } + + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) { + struct udevice *dev; + int ret; + + ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL); + if (ret) + printf("Couldn't bind dcp rng driver (%d)\n", ret); + + ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev); + if (ret) + printf("Failed to initialize dcp rng: %d\n", ret); + } + setup_serial_number(); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index ea709d15a5..fe33a7b611 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -21,6 +21,8 @@ #include <g_dnl.h> #include <linux/libfdt.h> #include <mmc.h> +#include <image.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -148,7 +150,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9) /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { @@ -184,7 +186,7 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_USB_GADGET int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { - put_unaligned(0x0151, &dev->idProduct); + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct); return 0; } @@ -314,7 +316,10 @@ ulong board_spl_fit_size_align(ulong size) */ size = ALIGN(size, 0x1000); - size += CONFIG_CSF_SIZE; + size += 2 * CONFIG_CSF_SIZE; + + if (size > CONFIG_SYS_BOOTM_LEN) + panic("spl: ERROR: image too big\n"); return size; } @@ -347,6 +352,42 @@ int dram_init_banksize(void) } #endif +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) && IS_ENABLED(CONFIG_IMX_HAB) && \ + !IS_ENABLED(CONFIG_SPL_FIT_SIGNATURE) +static int spl_verify_fit_hash(const void *fit) +{ + unsigned long size; + u8 value[SHA256_SUM_LEN]; + int value_len; + ulong fit_hash; + +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { + fit_hash = roundup((unsigned long)&_end + + fdt_totalsize(gd->fdt_blob), 4) + 0x18000; + } +#else + fit_hash = (unsigned long)&_end + 0x18000; +#endif + + size = fdt_totalsize(fit); + + if (calculate_hash(fit, size, "sha256", value, &value_len)) { + printf("Unsupported hash algorithm\n"); + return -1; + } + + if (value_len != SHA256_SUM_LEN) { + printf("Bad hash value len\n"); + return -1; + } else if (memcmp(value, (const void *)fit_hash, value_len) != 0) { + printf("Bad hash value\n"); + return -1; + } + + return 0; +} + /* * read the address where the IVT header must sit * from IVT image header, loaded from SPL into @@ -361,6 +402,30 @@ void *spl_load_simple_fit_fix_load(const void *fit) unsigned long size; u8 *tmp = (u8 *)fit; + if (IS_ENABLED(CONFIG_IMX_HAB)) { + if (IS_ENABLED(CONFIG_IMX_SPL_FIT_FDT_SIGNATURE)) { + u32 offset = ALIGN(fdt_totalsize(fit), 0x1000); + + if (imx_hab_authenticate_image((uintptr_t)fit, + offset + 2 * CSF_PAD_SIZE, + offset + CSF_PAD_SIZE)) { +#ifdef CONFIG_ANDROID_SUPPORT + printf("spl: ERROR: FIT FDT authentication unsuccessful\n"); + return NULL; +#else + panic("spl: ERROR: FIT FDT authentication unsuccessful\n"); +#endif + } + } else { + int ret = spl_verify_fit_hash(fit); + + if (ret && imx_hab_is_enabled()) + panic("spl: ERROR: FIT hash verify unsuccessful\n"); + + debug("spl_verify_fit_hash %d\n", ret); + } + } + offset = ALIGN(fdt_totalsize(fit), 0x1000); size = ALIGN(fdt_totalsize(fit), 4); size = board_spl_fit_size_align(size); @@ -379,6 +444,7 @@ void *spl_load_simple_fit_fix_load(const void *fit) return (void *)new; } +#endif #if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN) int board_handle_rdc_config(void *fdt_addr, const char *config_name, void *dst_addr) diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index ff4a87132b..c0e8bed958 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -263,7 +263,7 @@ static u32 img_header_size(void) static int img_info_size(void *img_hdr) { #ifdef CONFIG_SPL_LOAD_FIT - return fit_get_size(img_hdr); + return board_spl_fit_size_align(fit_get_size(img_hdr)); #elif defined CONFIG_SPL_LOAD_IMX_CONTAINER struct container_hdr *container = img_hdr; @@ -408,10 +408,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, { volatile gd_t *pgd = gd; int ret; - u32 boot; + u32 boot, bstage; ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, ((uintptr_t)&boot) ^ QUERY_BT_DEV); + ret |= g_rom_api->query_boot_infor(QUERY_BT_STAGE, &bstage, + ((uintptr_t)&bstage) ^ QUERY_BT_STAGE); set_gd(pgd); if (ret != ROM_API_OKAY) { @@ -419,6 +421,25 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, return -1; } + printf("Boot Stage: "); + + switch (bstage) { + case BT_STAGE_PRIMARY: + printf("Primary boot\n"); + break; + case BT_STAGE_SECONDARY: + printf("Secondary boot\n"); + break; + case BT_STAGE_RECOVERY: + printf("Recovery boot\n"); + break; + case BT_STAGE_USB: + printf("USB boot\n"); + break; + default: + printf("Unknow (0x%x)\n", bstage); + } + if (is_boot_from_stream_device(boot)) return spl_romapi_load_image_stream(spl_image, bootdev); diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 77d5ca722c..f4ceb21469 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -3,6 +3,7 @@ config CHAIN_OF_TRUST imply CMD_BLOB imply CMD_HASH if ARM select FSL_CAAM + select ARCH_MISC_INIT select SPL_BOARD_INIT if (ARM && SPL) select SPL_HASH if (ARM && SPL) select SHA_HW_ACCEL diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 6f1a0ca91b..18854df253 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -68,7 +68,7 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o obj-$(CONFIG_MXC_EPDC) += epdc_setup.o -ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610 imx8ulp)) +ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610 imx8ulp imx9)) obj-y += mmc.o endif ifdef CONFIG_FSL_FASTBOOT diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 7ffb315bc9..1b9733cf83 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP */ #include <common.h> @@ -113,11 +114,6 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); #endif -#ifdef CONFIG_FSL_CAAM - if (sec_init() < 0) - fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); -#endif - /* * dm_init_and_scan() is called as part of common SPL framework, so no * need to call it again but in case of powerpc platforms which currently diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 34875d0b8f..569a8c4655 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2021 NXP + * Copyright 2021-2022 NXP */ #include <common.h> @@ -20,6 +20,7 @@ #ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif +#include <dm/lists.h> #define SHA256_BITS 256 #define SHA256_BYTES (256/8) @@ -806,6 +807,13 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) prop.num_bits = key_len * 8; prop.exp_len = key_len; +#if defined(CONFIG_SPL_BUILD) + ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL); + if (ret) { + printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret); + return -EINVAL; + } +#endif ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); if (ret) { printf("RSA: Can't find Modular Exp implementation\n"); diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c index f7d5d328fa..3726ba978b 100644 --- a/board/freescale/common/tcpc.c +++ b/board/freescale/common/tcpc.c @@ -35,7 +35,7 @@ int tcpc_set_cc_to_source(struct tcpc_port *port) uint8_t valb; int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | @@ -54,7 +54,7 @@ int tcpc_set_cc_to_sink(struct tcpc_port *port) uint8_t valb; int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; valb = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | @@ -72,7 +72,7 @@ int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity pol uint8_t valb; int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1); @@ -101,7 +101,7 @@ int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, uint8_t valb_cc, cc2, cc1; int err; - if (port == NULL || polarity == NULL || state == NULL) + if (port == NULL || port->i2c_dev == NULL || polarity == NULL || state == NULL) return -EINVAL; err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1); @@ -220,7 +220,7 @@ int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask) { int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2); @@ -236,7 +236,7 @@ int tcpc_fault_status_mask(struct tcpc_port *port, uint8_t fault_mask) { int err = 0; - if (!port) + if (!port || port->i2c_dev == NULL) return -EINVAL; err = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS_MASK, &fault_mask, 1); @@ -250,7 +250,7 @@ int tcpc_send_command(struct tcpc_port *port, uint8_t command) { int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1); @@ -269,7 +269,7 @@ int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, int err; ulong start; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value); @@ -310,7 +310,7 @@ int tcpc_setup_dfp_mode(struct tcpc_port *port) enum typec_cc_state state; int ret; - if ((port == NULL) || (port->i2c_dev == NULL)) + if (port == NULL) return -EINVAL; if (tcpc_pd_sink_check_charging(port)) { @@ -377,7 +377,7 @@ int tcpc_setup_ufp_mode(struct tcpc_port *port) enum typec_cc_state state; int ret; - if ((port == NULL) || (port->i2c_dev == NULL)) + if (port == NULL) return -EINVAL; /* Check if the PD charge is working. If not, need to configure CC role for UFP */ @@ -477,7 +477,7 @@ static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *ms uint8_t cnt; uint16_t val; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; /* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */ @@ -514,7 +514,7 @@ static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *m uint8_t valb; uint16_t val = 0; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; if (msg_p == NULL || bytes <= 0) @@ -796,7 +796,7 @@ bool tcpc_pd_sink_check_charging(struct tcpc_port *port) enum typec_cc_polarity pol; enum typec_cc_state state; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return false; /* Check the CC status, must be sink */ @@ -834,7 +834,7 @@ static int tcpc_pd_sink_disable(struct tcpc_port *port) uint8_t valb; int err; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; port->pd_state = UNATTACH; @@ -877,7 +877,7 @@ static int tcpc_pd_sink_init(struct tcpc_port *port) enum typec_cc_polarity pol; enum typec_cc_state state; - if (port == NULL) + if (port == NULL || port->i2c_dev == NULL) return -EINVAL; port->pd_state = UNATTACH; diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c index 55f1e1ee77..eaf8b8e0d8 100644 --- a/board/freescale/imx8dxl_evk/imx8dxl_evk.c +++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c @@ -69,8 +69,8 @@ static iomux_cfg_t gpmi_nand_pads[] = { SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), - SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_RESET_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), @@ -328,7 +328,10 @@ int board_late_init(void) if (fdt_file && !strcmp(fdt_file, "undefined")) { #if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK) - env_set("fdt_file", "imx8dxl-ddr3l-evk.dtb"); + if (m4_booted) + env_set("fdt_file", "imx8dxl-ddr3l-evk-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dxl-ddr3l-evk.dtb"); #else if (m4_booted) env_set("fdt_file", "imx8dxl-evk-rpmsg.dtb"); diff --git a/board/freescale/imx8dxl_evk/spl.c b/board/freescale/imx8dxl_evk/spl.c index cb78ecf512..fdf966919d 100644 --- a/board/freescale/imx8dxl_evk/spl.c +++ b/board/freescale/imx8dxl_evk/spl.c @@ -27,11 +27,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) case MMC1_BOOT: return BOOT_DEVICE_MMC1; case SD2_BOOT: -#ifdef CONFIG_TARGET_IMX8DXL_DDR3_EVK - return BOOT_DEVICE_MMC1; -#else return BOOT_DEVICE_MMC2_2; -#endif case FLEXSPI_BOOT: return BOOT_DEVICE_SPI; case NAND_BOOT: diff --git a/board/freescale/imx8mm_ab2/Kconfig b/board/freescale/imx8mm_ab2/Kconfig new file mode 100644 index 0000000000..dbc7cbbebf --- /dev/null +++ b/board/freescale/imx8mm_ab2/Kconfig @@ -0,0 +1,29 @@ +if TARGET_IMX8MM_AB2 || TARGET_IMX8MM_DDR4_AB2 || \ + TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 || \ + TARGET_IMX8MN_DDR3L_AB2 + +config SYS_BOARD + default "imx8mm_ab2" + +config SYS_VENDOR + default "freescale" + +if IMX8MM +config SYS_CONFIG_NAME + default "imx8mm_ab2" + +config IMX_CONFIG + default "board/freescale/imx8mm_ab2/imximage-8mm.cfg" +endif + +if IMX8MN +config SYS_CONFIG_NAME + default "imx8mn_ab2" + +config IMX_CONFIG + default "board/freescale/imx8mm_ab2/imximage-8mn.cfg" +endif + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mm_ab2/MAINTAINERS b/board/freescale/imx8mm_ab2/MAINTAINERS new file mode 100644 index 0000000000..a8b847bcd2 --- /dev/null +++ b/board/freescale/imx8mm_ab2/MAINTAINERS @@ -0,0 +1,8 @@ +i.MX8M Mini and Nano Audio Board 2.0 +M: Adrian Alonso <adrian.alonso@nxp.com> +S: Maintained +F: board/freescale/imx8mm_ab2/ +F: include/configs/imx8mm_ab2.h +F: include/configs/imx8mn_ab2.h +F: configs/imx8mm_ab2_defconfig +F: configs/imx8mn_ab2_defconfig diff --git a/board/freescale/imx8mm_ab2/Makefile b/board/freescale/imx8mm_ab2/Makefile new file mode 100644 index 0000000000..0a540e2a1c --- /dev/null +++ b/board/freescale/imx8mm_ab2/Makefile @@ -0,0 +1,21 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_ab2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o +obj-$(CONFIG_TARGET_IMX8MM_DDR4_AB2) += ddr4_imx8mm_som.o +ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som_ld.o +obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som_ld.o +else +obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som.o +obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som.o +obj-$(CONFIG_TARGET_IMX8MN_DDR3L_AB2) += ddr3l_imx8mn_som.o +endif +endif diff --git a/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c new file mode 100644 index 0000000000..14d18cb491 --- /dev/null +++ b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c @@ -0,0 +1,944 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h> + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x20 }, + { 0x3d400000, 0xa1040001 }, + { 0x3d400064, 0x61008c }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x1000b }, + { 0x3d4000dc, 0x1d700004 }, + { 0x3d4000e0, 0x180000 }, + { 0x3d4000e4, 0x90000 }, + { 0x3d4000f0, 0x0 }, + { 0x3d4000f4, 0xee5 }, + { 0x3d400100, 0xc101b0e }, + { 0x3d400104, 0x30314 }, + { 0x3d400108, 0x4060509 }, + { 0x3d40010c, 0x2006 }, + { 0x3d400110, 0x6020306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d400120, 0x909 }, + { 0x3d400180, 0x40800020 }, + { 0x3d400184, 0xc350 }, + { 0x3d400190, 0x3868203 }, + { 0x3d400194, 0x20303 }, + { 0x3d4001b4, 0x603 }, + { 0x3d400198, 0x7000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001a0, 0x400018 }, + { 0x3d4001a4, 0x5003c }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400240, 0x600060c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x7ab50b07 }, + { 0x3d400254, 0x22 }, + { 0x3d40025c, 0x7b00665e }, + { 0x3d400264, 0xb0000040 }, + { 0x3d40026c, 0x50000a0c }, + { 0x3d400300, 0x17 }, + { 0x3d40036c, 0x10000 }, + { 0x3d400404, 0x3051 }, + { 0x3d400408, 0x61d2 }, + { 0x3d400494, 0xe00 }, + { 0x3d400498, 0x7ff }, + { 0x3d40049c, 0xe00 }, + { 0x3d4004a0, 0x7ff }, + { 0x3d402064, 0x28003b }, + { 0x3d4020dc, 0x12200004 }, + { 0x3d4020e0, 0x0 }, + { 0x3d402100, 0x7090b07 }, + { 0x3d402104, 0x20209 }, + { 0x3d402108, 0x3030407 }, + { 0x3d40210c, 0x2006 }, + { 0x3d402110, 0x3020203 }, + { 0x3d402114, 0x3030202 }, + { 0x3d402120, 0x909 }, + { 0x3d402180, 0x40800020 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x20303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xee5 }, + { 0x3d400028, 0x1 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x3ff }, + { 0x1015f, 0x3ff }, + { 0x1105f, 0x3ff }, + { 0x1115f, 0x3ff }, + { 0x11005f, 0x3ff }, + { 0x11015f, 0x3ff }, + { 0x11105f, 0x3ff }, + { 0x11115f, 0x3ff }, + { 0x55, 0x3ff }, + { 0x1055, 0x3ff }, + { 0x2055, 0x3ff }, + { 0x3055, 0x3ff }, + { 0x4055, 0xff }, + { 0x5055, 0xff }, + { 0x6055, 0x3ff }, + { 0x7055, 0x3ff }, + { 0x8055, 0x3ff }, + { 0x9055, 0x3ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x120024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x208 }, + { 0x1014d, 0x208 }, + { 0x1104d, 0x208 }, + { 0x1114d, 0x208 }, + { 0x11004d, 0x208 }, + { 0x11014d, 0x208 }, + { 0x11104d, 0x208 }, + { 0x11114d, 0x208 }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x0 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0xa7 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x32c }, + { 0x10043, 0x581 }, + { 0x10143, 0x581 }, + { 0x11043, 0x581 }, + { 0x11143, 0x581 }, + { 0x1200b2, 0x32c }, + { 0x110043, 0x581 }, + { 0x110143, 0x581 }, + { 0x111043, 0x581 }, + { 0x111143, 0x581 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2,0x0}, + {0x1200b2,0x0}, + {0x2200b2,0x0}, + {0x0200cb,0x0}, + {0x010043,0x0}, + {0x110043,0x0}, + {0x210043,0x0}, + {0x010143,0x0}, + {0x110143,0x0}, + {0x210143,0x0}, + {0x011043,0x0}, + {0x111043,0x0}, + {0x211043,0x0}, + {0x011143,0x0}, + {0x111143,0x0}, + {0x211143,0x0}, + {0x000080,0x0}, + {0x100080,0x0}, + {0x200080,0x0}, + {0x001080,0x0}, + {0x101080,0x0}, + {0x201080,0x0}, + {0x002080,0x0}, + {0x102080,0x0}, + {0x202080,0x0}, + {0x003080,0x0}, + {0x103080,0x0}, + {0x203080,0x0}, + {0x004080,0x0}, + {0x104080,0x0}, + {0x204080,0x0}, + {0x005080,0x0}, + {0x105080,0x0}, + {0x205080,0x0}, + {0x006080,0x0}, + {0x106080,0x0}, + {0x206080,0x0}, + {0x007080,0x0}, + {0x107080,0x0}, + {0x207080,0x0}, + {0x008080,0x0}, + {0x108080,0x0}, + {0x208080,0x0}, + {0x009080,0x0}, + {0x109080,0x0}, + {0x209080,0x0}, + {0x010080,0x0}, + {0x110080,0x0}, + {0x210080,0x0}, + {0x010180,0x0}, + {0x110180,0x0}, + {0x210180,0x0}, + {0x010081,0x0}, + {0x110081,0x0}, + {0x210081,0x0}, + {0x010181,0x0}, + {0x110181,0x0}, + {0x210181,0x0}, + {0x010082,0x0}, + {0x110082,0x0}, + {0x210082,0x0}, + {0x010182,0x0}, + {0x110182,0x0}, + {0x210182,0x0}, + {0x010083,0x0}, + {0x110083,0x0}, + {0x210083,0x0}, + {0x010183,0x0}, + {0x110183,0x0}, + {0x210183,0x0}, + {0x011080,0x0}, + {0x111080,0x0}, + {0x211080,0x0}, + {0x011180,0x0}, + {0x111180,0x0}, + {0x211180,0x0}, + {0x011081,0x0}, + {0x111081,0x0}, + {0x211081,0x0}, + {0x011181,0x0}, + {0x111181,0x0}, + {0x211181,0x0}, + {0x011082,0x0}, + {0x111082,0x0}, + {0x211082,0x0}, + {0x011182,0x0}, + {0x111182,0x0}, + {0x211182,0x0}, + {0x011083,0x0}, + {0x111083,0x0}, + {0x211083,0x0}, + {0x011183,0x0}, + {0x111183,0x0}, + {0x211183,0x0}, + {0x0100d0,0x0}, + {0x1100d0,0x0}, + {0x2100d0,0x0}, + {0x0101d0,0x0}, + {0x1101d0,0x0}, + {0x2101d0,0x0}, + {0x0100d1,0x0}, + {0x1100d1,0x0}, + {0x2100d1,0x0}, + {0x0101d1,0x0}, + {0x1101d1,0x0}, + {0x2101d1,0x0}, + {0x0100d2,0x0}, + {0x1100d2,0x0}, + {0x2100d2,0x0}, + {0x0101d2,0x0}, + {0x1101d2,0x0}, + {0x2101d2,0x0}, + {0x0100d3,0x0}, + {0x1100d3,0x0}, + {0x2100d3,0x0}, + {0x0101d3,0x0}, + {0x1101d3,0x0}, + {0x2101d3,0x0}, + {0x0110d0,0x0}, + {0x1110d0,0x0}, + {0x2110d0,0x0}, + {0x0111d0,0x0}, + {0x1111d0,0x0}, + {0x2111d0,0x0}, + {0x0110d1,0x0}, + {0x1110d1,0x0}, + {0x2110d1,0x0}, + {0x0111d1,0x0}, + {0x1111d1,0x0}, + {0x2111d1,0x0}, + {0x0110d2,0x0}, + {0x1110d2,0x0}, + {0x2110d2,0x0}, + {0x0111d2,0x0}, + {0x1111d2,0x0}, + {0x2111d2,0x0}, + {0x0110d3,0x0}, + {0x1110d3,0x0}, + {0x2110d3,0x0}, + {0x0111d3,0x0}, + {0x1111d3,0x0}, + {0x2111d3,0x0}, + {0x010068,0x0}, + {0x010168,0x0}, + {0x010268,0x0}, + {0x010368,0x0}, + {0x010468,0x0}, + {0x010568,0x0}, + {0x010668,0x0}, + {0x010768,0x0}, + {0x010868,0x0}, + {0x010069,0x0}, + {0x010169,0x0}, + {0x010269,0x0}, + {0x010369,0x0}, + {0x010469,0x0}, + {0x010569,0x0}, + {0x010669,0x0}, + {0x010769,0x0}, + {0x010869,0x0}, + {0x01006a,0x0}, + {0x01016a,0x0}, + {0x01026a,0x0}, + {0x01036a,0x0}, + {0x01046a,0x0}, + {0x01056a,0x0}, + {0x01066a,0x0}, + {0x01076a,0x0}, + {0x01086a,0x0}, + {0x01006b,0x0}, + {0x01016b,0x0}, + {0x01026b,0x0}, + {0x01036b,0x0}, + {0x01046b,0x0}, + {0x01056b,0x0}, + {0x01066b,0x0}, + {0x01076b,0x0}, + {0x01086b,0x0}, + {0x011068,0x0}, + {0x011168,0x0}, + {0x011268,0x0}, + {0x011368,0x0}, + {0x011468,0x0}, + {0x011568,0x0}, + {0x011668,0x0}, + {0x011768,0x0}, + {0x011868,0x0}, + {0x011069,0x0}, + {0x011169,0x0}, + {0x011269,0x0}, + {0x011369,0x0}, + {0x011469,0x0}, + {0x011569,0x0}, + {0x011669,0x0}, + {0x011769,0x0}, + {0x011869,0x0}, + {0x01106a,0x0}, + {0x01116a,0x0}, + {0x01126a,0x0}, + {0x01136a,0x0}, + {0x01146a,0x0}, + {0x01156a,0x0}, + {0x01166a,0x0}, + {0x01176a,0x0}, + {0x01186a,0x0}, + {0x01106b,0x0}, + {0x01116b,0x0}, + {0x01126b,0x0}, + {0x01136b,0x0}, + {0x01146b,0x0}, + {0x01156b,0x0}, + {0x01166b,0x0}, + {0x01176b,0x0}, + {0x01186b,0x0}, + {0x01008c,0x0}, + {0x11008c,0x0}, + {0x21008c,0x0}, + {0x01018c,0x0}, + {0x11018c,0x0}, + {0x21018c,0x0}, + {0x01008d,0x0}, + {0x11008d,0x0}, + {0x21008d,0x0}, + {0x01018d,0x0}, + {0x11018d,0x0}, + {0x21018d,0x0}, + {0x01008e,0x0}, + {0x11008e,0x0}, + {0x21008e,0x0}, + {0x01018e,0x0}, + {0x11018e,0x0}, + {0x21018e,0x0}, + {0x01008f,0x0}, + {0x11008f,0x0}, + {0x21008f,0x0}, + {0x01018f,0x0}, + {0x11018f,0x0}, + {0x21018f,0x0}, + {0x01108c,0x0}, + {0x11108c,0x0}, + {0x21108c,0x0}, + {0x01118c,0x0}, + {0x11118c,0x0}, + {0x21118c,0x0}, + {0x01108d,0x0}, + {0x11108d,0x0}, + {0x21108d,0x0}, + {0x01118d,0x0}, + {0x11118d,0x0}, + {0x21118d,0x0}, + {0x01108e,0x0}, + {0x11108e,0x0}, + {0x21108e,0x0}, + {0x01118e,0x0}, + {0x11118e,0x0}, + {0x21118e,0x0}, + {0x01108f,0x0}, + {0x11108f,0x0}, + {0x21108f,0x0}, + {0x01118f,0x0}, + {0x11118f,0x0}, + {0x21118f,0x0}, + {0x0100c0,0x0}, + {0x1100c0,0x0}, + {0x2100c0,0x0}, + {0x0101c0,0x0}, + {0x1101c0,0x0}, + {0x2101c0,0x0}, + {0x0102c0,0x0}, + {0x1102c0,0x0}, + {0x2102c0,0x0}, + {0x0103c0,0x0}, + {0x1103c0,0x0}, + {0x2103c0,0x0}, + {0x0104c0,0x0}, + {0x1104c0,0x0}, + {0x2104c0,0x0}, + {0x0105c0,0x0}, + {0x1105c0,0x0}, + {0x2105c0,0x0}, + {0x0106c0,0x0}, + {0x1106c0,0x0}, + {0x2106c0,0x0}, + {0x0107c0,0x0}, + {0x1107c0,0x0}, + {0x2107c0,0x0}, + {0x0108c0,0x0}, + {0x1108c0,0x0}, + {0x2108c0,0x0}, + {0x0100c1,0x0}, + {0x1100c1,0x0}, + {0x2100c1,0x0}, + {0x0101c1,0x0}, + {0x1101c1,0x0}, + {0x2101c1,0x0}, + {0x0102c1,0x0}, + {0x1102c1,0x0}, + {0x2102c1,0x0}, + {0x0103c1,0x0}, + {0x1103c1,0x0}, + {0x2103c1,0x0}, + {0x0104c1,0x0}, + {0x1104c1,0x0}, + {0x2104c1,0x0}, + {0x0105c1,0x0}, + {0x1105c1,0x0}, + {0x2105c1,0x0}, + {0x0106c1,0x0}, + {0x1106c1,0x0}, + {0x2106c1,0x0}, + {0x0107c1,0x0}, + {0x1107c1,0x0}, + {0x2107c1,0x0}, + {0x0108c1,0x0}, + {0x1108c1,0x0}, + {0x2108c1,0x0}, + {0x0100c2,0x0}, + {0x1100c2,0x0}, + {0x2100c2,0x0}, + {0x0101c2,0x0}, + {0x1101c2,0x0}, + {0x2101c2,0x0}, + {0x0102c2,0x0}, + {0x1102c2,0x0}, + {0x2102c2,0x0}, + {0x0103c2,0x0}, + {0x1103c2,0x0}, + {0x2103c2,0x0}, + {0x0104c2,0x0}, + {0x1104c2,0x0}, + {0x2104c2,0x0}, + {0x0105c2,0x0}, + {0x1105c2,0x0}, + {0x2105c2,0x0}, + {0x0106c2,0x0}, + {0x1106c2,0x0}, + {0x2106c2,0x0}, + {0x0107c2,0x0}, + {0x1107c2,0x0}, + {0x2107c2,0x0}, + {0x0108c2,0x0}, + {0x1108c2,0x0}, + {0x2108c2,0x0}, + {0x0100c3,0x0}, + {0x1100c3,0x0}, + {0x2100c3,0x0}, + {0x0101c3,0x0}, + {0x1101c3,0x0}, + {0x2101c3,0x0}, + {0x0102c3,0x0}, + {0x1102c3,0x0}, + {0x2102c3,0x0}, + {0x0103c3,0x0}, + {0x1103c3,0x0}, + {0x2103c3,0x0}, + {0x0104c3,0x0}, + {0x1104c3,0x0}, + {0x2104c3,0x0}, + {0x0105c3,0x0}, + {0x1105c3,0x0}, + {0x2105c3,0x0}, + {0x0106c3,0x0}, + {0x1106c3,0x0}, + {0x2106c3,0x0}, + {0x0107c3,0x0}, + {0x1107c3,0x0}, + {0x2107c3,0x0}, + {0x0108c3,0x0}, + {0x1108c3,0x0}, + {0x2108c3,0x0}, + {0x0110c0,0x0}, + {0x1110c0,0x0}, + {0x2110c0,0x0}, + {0x0111c0,0x0}, + {0x1111c0,0x0}, + {0x2111c0,0x0}, + {0x0112c0,0x0}, + {0x1112c0,0x0}, + {0x2112c0,0x0}, + {0x0113c0,0x0}, + {0x1113c0,0x0}, + {0x2113c0,0x0}, + {0x0114c0,0x0}, + {0x1114c0,0x0}, + {0x2114c0,0x0}, + {0x0115c0,0x0}, + {0x1115c0,0x0}, + {0x2115c0,0x0}, + {0x0116c0,0x0}, + {0x1116c0,0x0}, + {0x2116c0,0x0}, + {0x0117c0,0x0}, + {0x1117c0,0x0}, + {0x2117c0,0x0}, + {0x0118c0,0x0}, + {0x1118c0,0x0}, + {0x2118c0,0x0}, + {0x0110c1,0x0}, + {0x1110c1,0x0}, + {0x2110c1,0x0}, + {0x0111c1,0x0}, + {0x1111c1,0x0}, + {0x2111c1,0x0}, + {0x0112c1,0x0}, + {0x1112c1,0x0}, + {0x2112c1,0x0}, + {0x0113c1,0x0}, + {0x1113c1,0x0}, + {0x2113c1,0x0}, + {0x0114c1,0x0}, + {0x1114c1,0x0}, + {0x2114c1,0x0}, + {0x0115c1,0x0}, + {0x1115c1,0x0}, + {0x2115c1,0x0}, + {0x0116c1,0x0}, + {0x1116c1,0x0}, + {0x2116c1,0x0}, + {0x0117c1,0x0}, + {0x1117c1,0x0}, + {0x2117c1,0x0}, + {0x0118c1,0x0}, + {0x1118c1,0x0}, + {0x2118c1,0x0}, + {0x0110c2,0x0}, + {0x1110c2,0x0}, + {0x2110c2,0x0}, + {0x0111c2,0x0}, + {0x1111c2,0x0}, + {0x2111c2,0x0}, + {0x0112c2,0x0}, + {0x1112c2,0x0}, + {0x2112c2,0x0}, + {0x0113c2,0x0}, + {0x1113c2,0x0}, + {0x2113c2,0x0}, + {0x0114c2,0x0}, + {0x1114c2,0x0}, + {0x2114c2,0x0}, + {0x0115c2,0x0}, + {0x1115c2,0x0}, + {0x2115c2,0x0}, + {0x0116c2,0x0}, + {0x1116c2,0x0}, + {0x2116c2,0x0}, + {0x0117c2,0x0}, + {0x1117c2,0x0}, + {0x2117c2,0x0}, + {0x0118c2,0x0}, + {0x1118c2,0x0}, + {0x2118c2,0x0}, + {0x0110c3,0x0}, + {0x1110c3,0x0}, + {0x2110c3,0x0}, + {0x0111c3,0x0}, + {0x1111c3,0x0}, + {0x2111c3,0x0}, + {0x0112c3,0x0}, + {0x1112c3,0x0}, + {0x2112c3,0x0}, + {0x0113c3,0x0}, + {0x1113c3,0x0}, + {0x2113c3,0x0}, + {0x0114c3,0x0}, + {0x1114c3,0x0}, + {0x2114c3,0x0}, + {0x0115c3,0x0}, + {0x1115c3,0x0}, + {0x2115c3,0x0}, + {0x0116c3,0x0}, + {0x1116c3,0x0}, + {0x2116c3,0x0}, + {0x0117c3,0x0}, + {0x1117c3,0x0}, + {0x2117c3,0x0}, + {0x0118c3,0x0}, + {0x1118c3,0x0}, + {0x2118c3,0x0}, + {0x010020,0x0}, + {0x110020,0x0}, + {0x210020,0x0}, + {0x011020,0x0}, + {0x111020,0x0}, + {0x211020,0x0}, + {0x02007d,0x0}, + {0x12007d,0x0}, + {0x22007d,0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1d70 }, + { 0x54030, 0x4 }, + { 0x54031, 0x18 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1220 }, + { 0x54030, 0x4 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x26 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 667, }, +}; + diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c new file mode 100644 index 0000000000..2f80b9832b --- /dev/null +++ b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c @@ -0,0 +1,1265 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0xaa }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x9200d2 }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x814 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1409010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x40005e }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x14 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x4030205 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x3030d04 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1005010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x1205f, 0x2fd }, + { 0x1215f, 0x2fd }, + { 0x1305f, 0x2fd }, + { 0x1315f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x11205f, 0x2fd }, + { 0x11215f, 0x2fd }, + { 0x11305f, 0x2fd }, + { 0x11315f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x1204d, 0x1a }, + { 0x1214d, 0x1a }, + { 0x1304d, 0x1a }, + { 0x1314d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x11204d, 0x1a }, + { 0x11214d, 0x1a }, + { 0x11304d, 0x1a }, + { 0x11314d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x12049, 0xe38 }, + { 0x12149, 0xe38 }, + { 0x13049, 0xe38 }, + { 0x13149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x112049, 0xe38 }, + { 0x112149, 0xe38 }, + { 0x113049, 0xe38 }, + { 0x113149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x5 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x12043, 0x5b1 }, + { 0x12143, 0x5b1 }, + { 0x13043, 0x5b1 }, + { 0x13143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x112043, 0x5b1 }, + { 0x112143, 0x5b1 }, + { 0x113043, 0x5b1 }, + { 0x113143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x14 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xf }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x630 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x630 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x630 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x630 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x630 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x630 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x630 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x630 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x630 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xa }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x2 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x7 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x10 }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x8140 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x10 }, + { 0x900a8, 0x8138 }, + { 0x900a9, 0x10c }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7c8 }, + { 0x900ac, 0x101 }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x0 }, + { 0x900af, 0x8 }, + { 0x900b0, 0x8 }, + { 0x900b1, 0x448 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0xf }, + { 0x900b4, 0x7c0 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x47 }, + { 0x900b7, 0x630 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x8 }, + { 0x900ba, 0x618 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0xe0 }, + { 0x900be, 0x109 }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x7c8 }, + { 0x900c1, 0x109 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x8140 }, + { 0x900c4, 0x10c }, + { 0x900c5, 0x0 }, + { 0x900c6, 0x1 }, + { 0x900c7, 0x8 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x8 }, + { 0x900cb, 0x8 }, + { 0x900cc, 0x7c8 }, + { 0x900cd, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2c }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c new file mode 100644 index 0000000000..84114a3e8a --- /dev/null +++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + + /* performance setting */ + { 0x3d400250, 0x00001f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x900003ff }, + { 0x3d40026c, 0x200003ff }, + { 0x3d400494, 0x01000e00 }, + { 0x3d400498, 0x03ff0000 }, + { 0x3d40049c, 0x01000e00 }, + { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; + diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c new file mode 100644 index 0000000000..a3577efd0b --- /dev/null +++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c @@ -0,0 +1,1056 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x6100dc }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0x2340105 }, + { 0x3d4000e0, 0x0 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x410 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0xd0c1b0d }, + { 0x3d400104, 0x30313 }, + { 0x3d400108, 0x508060a }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x6030306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d40011c, 0x404 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x20308 }, + { 0x3d40012c, 0x1406010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x30d4 }, + { 0x3d400190, 0x38b8204 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb04 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x600061c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x7300b473 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d40036c, 0x10 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100009 }, + { 0x3d4004a0, 0x2 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 1066, }, +}; diff --git a/board/freescale/imx8mm_ab2/imx8mm_ab2.c b/board/freescale/imx8mm_ab2/imx8mm_ab2.c new file mode 100644 index 0000000000..e788bff3e1 --- /dev/null +++ b/board/freescale/imx8mm_ab2/imx8mm_ab2.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <miiphy.h> +#include <netdev.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <power/regulator.h> +#if defined(CONFIG_IMX8MM) +#include <asm/arch/imx8mm_pins.h> +#else +#include <asm/arch/imx8mn_pins.h> +#endif +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> +#include <asm-generic/gpio.h> +#include <asm/mach-imx/dma.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <spl.h> +#include <usb.h> +#include "../common/tcpc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define PWR_EN_5V0 IMX_GPIO_NR(1, 7) +#define PWR_EN_ANA IMX_GPIO_NR(1, 10) +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +#if defined(CONFIG_IMX8MM) +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_5v0[] = { + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_ana[] = { + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if defined(CONFIG_IMX8MN) +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_5v0[] = { + IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwr_en_ana[] = { + IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_NAND_MXS +static void setup_gpmi_nand(void) +{ + init_nand_clk(); +} +#endif + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(1); + + imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0)); + gpio_request(PWR_EN_5V0, "pwr_en_5v0"); + gpio_direction_output(PWR_EN_5V0, 1); + + imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana)); + gpio_request(PWR_EN_ANA, "pwr_en_ana"); + gpio_direction_output(PWR_EN_ANA, 0); + + return 0; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0); + + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /* i2c2*/ + .addr = 0x1d, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +static int setup_typec(void) +{ + int ret; + + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", __func__, ret); + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + imx8m_usb_power(index, true); + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(&port1); + else + tcpc_setup_ufp_mode(&port1); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (init == USB_INIT_HOST) + ret = tcpc_disable_src_vbus(&port1); + + imx8m_usb_power(index, false); + + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + enum typec_cc_polarity pol; + enum typec_cc_state state; + int ret = 0; + + tcpc_setup_ufp_mode(&port1); + ret = tcpc_get_cc_status(&port1, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_DM_REGULATOR + regulators_enable_boot_on(false); +#endif + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) + env_set("board_name", "AB2"); + + if (IS_ENABLED(CONFIG_IMX8MM)) + env_set("board_rev", "iMX8MM"); + else { + env_set("board_rev", "iMX8MN"); + env_set("board", "imx8mn_ab2"); + } + + return 0; +} diff --git a/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg new file mode 100644 index 0000000000..fcace8a93a --- /dev/null +++ b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +BOOT_FROM fspi +LOADER u-boot-spl-ddr.bin 0x7E2000 diff --git a/board/freescale/imx8mm_ab2/imximage-8mm.cfg b/board/freescale/imx8mm_ab2/imximage-8mm.cfg new file mode 100644 index 0000000000..20061521f2 --- /dev/null +++ b/board/freescale/imx8mm_ab2/imximage-8mm.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/freescale/imx8mm_ab2/imximage-8mn.cfg b/board/freescale/imx8mm_ab2/imximage-8mn.cfg new file mode 100644 index 0000000000..0edda9c5e0 --- /dev/null +++ b/board/freescale/imx8mm_ab2/imximage-8mn.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x912000 diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c new file mode 100644 index 0000000000..664c08e718 --- /dev/null +++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c @@ -0,0 +1,1855 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + + /* performance setting */ + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + + /* P1: 400mts */ + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + + /* p2: 100mts */ + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c new file mode 100644 index 0000000000..8929bc6d26 --- /dev/null +++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c @@ -0,0 +1,1585 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c new file mode 100644 index 0000000000..aa23c35094 --- /dev/null +++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c @@ -0,0 +1,1440 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x111 }, + { 0x3d400024, 0x1f400 }, + { 0x3d400064, 0x300070 }, + { 0x3d4000d0, 0xc002030f }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0xa40012 }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x10100d11 }, + { 0x3d400104, 0x3041a }, + { 0x3d40010c, 0x606000 }, + { 0x3d400110, 0x8040408 }, + { 0x3d400114, 0x2030606 }, + { 0x3d400118, 0x1010004 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20300 }, + { 0x3d400134, 0xa100002 }, + { 0x3d400138, 0x73 }, + { 0x3d400144, 0x500028 }, + { 0x3d400180, 0x190000c }, + { 0x3d400184, 0x14030d4 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4898204 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x904 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x4070f0f }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x11 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x11 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, + { 0x2200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x7c8 }, + { 0x90187, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 400, 100, }, +}; diff --git a/board/freescale/imx8mm_ab2/spl.c b/board/freescale/imx8mm_ab2/spl.c new file mode 100644 index 0000000000..fe38a2a04a --- /dev/null +++ b/board/freescale/imx8mm_ab2/spl.c @@ -0,0 +1,473 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <cpu_func.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/clock.h> +#if defined(CONFIG_IMX8MM) +#include <asm/arch/imx8mm_pins.h> +#endif +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/arch/ddr.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <power/bd71837.h> +#include <power/bd71837.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <linux/delay.h> +#include <fsl_sec.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ +#ifdef CONFIG_SPL_BOOTROM_SUPPORT + return BOOT_DEVICE_BOOTROM; +#else + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#if defined(CONFIG_IMX8MM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4) +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 8}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} +#endif + +#if CONFIG_IS_ENABLED(POWER_LEGACY) +#define I2C_PMIC 0 +#ifdef CONFIG_POWER_PCA9450 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_pca9450_init(I2C_PMIC, 0x25); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set DVS1 to 0.8v for suspend */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x10); + + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + pmic_reg_write(p, PCA9450_BUCK3OUT_DVS0, 0x1C); + + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(p, PCA9450_BUCK3CTRL, 0x4a); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#else +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD718XX_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + +#ifndef CONFIG_IMX8M_LPDDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); +#endif + + /* lock the PMIC regs */ + pmic_reg_write(p, BD718XX_REGLOCK, 0x11); + + return 0; +} +#endif +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + +#if defined(CONFIG_IMX8MM) + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + /* Set DVS1 to 0.8v for suspend */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); +#endif /* CONFIG_IMX8MM */ + +#if defined(CONFIG_IMX8MN) +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_AB2) + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + + /* Disable the BUCK2 */ + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); + + /* Set NVCC_DRAM to 1.35v */ + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); +#else + /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + /* Set DVS1 to 0.75v for low-v suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0xC); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* enable LDO4 to 1.2v */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); +#endif /* CONFIG_IMX8MN */ + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#endif /* DM_PMIC_PCA9450 */ + +#if CONFIG_IS_ENABLED(DM_PMIC_BD71837) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@4b", &dev); + if (ret == -ENODEV) { + puts("No pmic@4b\n"); + return 0; + } + if (ret != 0) + return ret; + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + /* unlock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + +#if defined(CONFIG_IMX8MM) + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); +#ifdef CONFIG_IMX8M_DDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); +#endif +#endif /* CONFIG_IMX8MM */ + +#if defined(CONFIG_IMX8MN) + /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */ + pmic_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0xf); +#ifdef CONFIG_IMX8M_DDR4 + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xf); +#endif + /* Set VDD_SOC 0.85v for suspend */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_SUSP, 0xf); +#ifdef CONFIG_IMX8M_DDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); +#endif +#endif /* CONFIG_IMX8MN */ + + /* lock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + + return 0; +} +#endif /* DM_PMIC_BD71837 */ + +void spl_board_init(void) +{ +#if defined(CONFIG_IMX8MN) + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %d\n", ret); + } +#else + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + if (sec_init()) + printf("\nsec_init failed!\n"); + } +#endif + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + +#if defined(CONFIG_IMX8MN) + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } +#endif + + enable_tzc380(); + +#if defined(CONFIG_IMX8MM) + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} + +#if defined(CONFIG_IMX8MN) +#ifdef CONFIG_SPL_MMC +#define UBOOT_RAW_SECTOR_OFFSET 0x40 +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + u32 boot_dev = spl_boot_device(); + switch (boot_dev) { + case BOOT_DEVICE_MMC1: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; + } + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +} +#endif +#endif diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index d3ef12bf5b..39f6d6281c 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ #include <common.h> +#include <efi_loader.h> #include <env.h> #include <init.h> #include <miiphy.h> @@ -70,6 +71,23 @@ static void setup_gpmi_nand(void) } #endif +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MM-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", + .images = fw_images, +}; + +u8 num_image_type_guids = ARRAY_SIZE(fw_images); +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index 92601393cb..be7bdec635 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <efi_loader.h> #include <env.h> #include <init.h> #include <asm/global_data.h> @@ -70,6 +71,23 @@ static void setup_gpmi_nand(void) } #endif +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MN-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .images = fw_images, +}; + +u8 num_image_type_guids = ARRAY_SIZE(fw_images); +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 346ea16744..c183dc9f4b 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <efi_loader.h> #include <env.h> #include <errno.h> #include <init.h> @@ -51,6 +52,23 @@ static void setup_gpmi_nand(void) } #endif +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .images = fw_images, +}; + +u8 num_image_type_guids = ARRAY_SIZE(fw_images); +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 81a961883f..f470e6c7f5 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <efi_loader.h> #include <env.h> #include <init.h> #include <malloc.h> @@ -45,6 +46,23 @@ static iomux_v3_cfg_t const uart_pads[] = { IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MQ-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", + .images = fw_images, +}; + +u8 num_image_type_guids = ARRAY_SIZE(fw_images); +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index 7bf35928da..1dccc07fb9 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -51,7 +51,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001b0, 0x11 }, { 0x3d4001b4, 0x170a }, { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, + { 0x3d4001c4, 0x0 }, { 0x3d4000f4, 0x639 }, { 0x3d400108, 0x70e1617 }, { 0x3d400200, 0x15 }, @@ -337,6 +337,7 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20113, 0x5 }, { 0x20114, 0x0 }, { 0x20115, 0x1 }, + { 0x20021, 0x0 }, }; /* ddr phy trained csr */ @@ -1730,12 +1731,12 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x90011, 0xdfbd }, { 0x90012, 0x60 }, { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, + { 0x20010, 0x00 }, + { 0x20011, 0x0 }, + { 0x120010, 0x00 }, + { 0x120011, 0x0 }, + { 0x220010, 0x00 }, + { 0x220011, 0x0 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 94242e7025..3632e53544 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -318,12 +318,6 @@ void spl_board_prepare_for_boot(void) struct imx_rdc_cfg rdc_cfg[] = { RDC_MDAn(RDC_MDA_DCSS, DID2), - /* memory region */ - RDC_MEM_REGIONn(1, 0x00000000, 0xA0000000, LCK|ENA|D3R|D3W|D2R|/*D2W|*/D1R|D1W|D0R|D0W), - RDC_MEM_REGIONn(2, 0xA0000000, 0xB0000000, LCK|ENA|D3R|D3W|D2R|D2W|D1R|D1W|/*D0R|*/D0W), - RDC_MEM_REGIONn(3, 0xB0000000, 0xBE000000, LCK|ENA|D3R|D3W|D2R|/*D2W|*/D1R|D1W|D0R|D0W), - RDC_MEM_REGIONn(4, 0xBE000000, 0xC0000000, LCK|ENA|D3R|D3W|D2R|/*D2W|D1R|D1W|*/D0R|D0W), - RDC_MEM_REGIONn(5, 0xC0000000, 0xFFFFFFFF, LCK|ENA|D3R|D3W|D2R|/*D2W|*/D1R|D1W|D0R|D0W), {0}, }; diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 4f4006a759..3a6bd1da5a 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -164,7 +164,6 @@ void reset_lsm6dsx(uint8_t i2c_bus, uint8_t addr) int board_init(void) { - int sync = -ENODEV; #if defined(CONFIG_NXP_FSPI) || defined(CONFIG_FSL_FSPI_NAND) setup_flexspi(); @@ -177,13 +176,8 @@ int board_init(void) setup_fec(); #endif - if (m33_image_booted()) { - sync = m33_image_handshake(1000); - printf("M33 Sync: %s\n", sync? "Timeout": "OK"); - } - /* When sync with M33 is failed, use local driver to set for video */ - if (sync != 0 && IS_ENABLED(CONFIG_DM_VIDEO)) { + if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_DM_VIDEO)) { mipi_dsi_mux_panel(); mipi_dsi_panel_backlight(); } @@ -216,9 +210,39 @@ int board_late_init(void) #ifdef CONFIG_FSL_FASTBOOT #ifdef CONFIG_ANDROID_RECOVERY +static iomux_cfg_t const recovery_pad[] = { + IMX8ULP_PAD_PTF7__PTF7 | MUX_PAD_CTRL(PAD_CTL_IBE_ENABLE), +}; int is_recovery_key_pressing(void) { - return 0; /*TODO*/ + int ret; + struct gpio_desc desc; + + imx8ulp_iomux_setup_multiple_pads(recovery_pad, ARRAY_SIZE(recovery_pad)); + + ret = dm_gpio_lookup_name("GPIO3_7", &desc); + if (ret) { + printf("%s lookup GPIO3_7 failed ret = %d\n", __func__, ret); + return 0; + } + + ret = dm_gpio_request(&desc, "recovery"); + if (ret) { + printf("%s request recovery pad failed ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + ret = dm_gpio_get_value(&desc); + if (ret < 0) { + printf("%s error in retrieving GPIO value ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_free(desc.dev, &desc); + + return !ret; } #endif /*CONFIG_ANDROID_RECOVERY*/ #endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c index 1878ca593a..e9edb87128 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0604c8, 0x8000f00 }, /* 306 */ { 0x2e0604cc, 0xa08 }, /* 307 */ { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x102 }, /* 309 */ - { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ { 0x2e0604dc, 0x40400 }, /* 311 */ { 0x2e0604e0, 0x4040000 }, /* 312 */ { 0x2e0604e4, 0x4000000 }, /* 313 */ diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c index 4240eaa44b..5feb77f3e7 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c @@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0604c8, 0x8000f00 }, /* 306 */ { 0x2e0604cc, 0xa08 }, /* 307 */ { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x102 }, /* 309 */ - { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ { 0x2e0604dc, 0x40400 }, /* 311 */ { 0x2e0604e0, 0x4040000 }, /* 312 */ { 0x2e0604e4, 0x4000000 }, /* 313 */ diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c b/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c index 2dc4031d98..1bb09ff761 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c @@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0604c8, 0x8000f00 }, /* 306 */ { 0x2e0604cc, 0xa08 }, /* 307 */ { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x102 }, /* 309 */ - { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ { 0x2e0604dc, 0x40400 }, /* 311 */ { 0x2e0604e0, 0x4040000 }, /* 312 */ { 0x2e0604e4, 0x4000000 }, /* 313 */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index 78dd44d369..0cbce593fd 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -21,7 +21,7 @@ #include <asm/arch/rdc.h> #include <asm/arch/upower.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/clock.h> #include <asm/arch/pcc.h> @@ -123,14 +123,11 @@ void spl_board_init(void) { struct udevice *dev; u32 res; - int node, ret; + int ret; - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu"); - ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &dev); - if (ret) { + ret = arch_cpu_init_dm(); + if (ret) return; - } - device_probe(dev); board_early_init_f(); @@ -172,6 +169,8 @@ void spl_board_init(void) /* Asks S400 to release CAAM for A35 core */ ret = ahab_release_caam(7, &res); if (!ret) { + if (((res >> 8) & 0xff) == ELE_NON_SECURE_STATE_FAILURE_IND) + printf("Warning: CAAM is in non-secure state, 0x%x\n", res); /* Only two UCLASS_MISC devicese are present on the platform. There * are MU and CAAM. Here we initialize CAAM once it's released by @@ -183,6 +182,16 @@ void spl_board_init(void) printf("Failed to initialize caam_jr: %d\n", ret); } } + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ahab_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } } void board_init_f(ulong dummy) diff --git a/board/freescale/imx8ulp_watch/Kconfig b/board/freescale/imx8ulp_watch/Kconfig new file mode 100644 index 0000000000..2dbf7bbef3 --- /dev/null +++ b/board/freescale/imx8ulp_watch/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8ULP_WATCH + +config SYS_BOARD + default "imx8ulp_watch" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8ulp_watch" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8ulp_watch/MAINTAINERS b/board/freescale/imx8ulp_watch/MAINTAINERS new file mode 100644 index 0000000000..8ac8fd35be --- /dev/null +++ b/board/freescale/imx8ulp_watch/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8ULP WATCH BOARD +M: NXP semiconductor +S: Maintained +F: board/freescale/imx8ulp_watch/ +F: include/configs/imx8ulp_evk.h +F: configs/imx8ulp_watch_android_defconfig diff --git a/board/freescale/imx8ulp_watch/Makefile b/board/freescale/imx8ulp_watch/Makefile new file mode 100644 index 0000000000..4563ea9a36 --- /dev/null +++ b/board/freescale/imx8ulp_watch/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += imx8ulp_watch.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += lpddr4x_timing.o +endif diff --git a/board/freescale/imx8ulp_watch/imx8ulp_watch.c b/board/freescale/imx8ulp_watch/imx8ulp_watch.c new file mode 100644 index 0000000000..ada412b769 --- /dev/null +++ b/board/freescale/imx8ulp_watch/imx8ulp_watch.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/imx8ulp-pins.h> +#include <asm/arch/clock.h> +#include <asm/arch/pcc.h> +#include <asm/arch/sys_proto.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <power-domain.h> +#include <dt-bindings/power/imx8ulp-power.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMX8ULP_GPIOA_BASE_ADDR (0x28800000 + 0x40) +#define IMX8ULP_GPIOB_BASE_ADDR (0x28810000 + 0x40) +#define IMX8ULP_GPIOC_BASE_ADDR (0x28820000 + 0x40) + +#define PANEL_RESET_GPIO_ADDR IMX8ULP_GPIOC_BASE_ADDR +#define PANEL_RESET_PIN 10 + + +static iomux_cfg_t const panel_reset_pads[] = { + IMX8ULP_PAD_PTC10__PTC10, +}; + +static void imx8ulp_gpio_set_value(struct gpio_regs *regs, int offset, int value) +{ + if (value) + writel((1 << offset), ®s->gpio_psor); + else + writel((1 << offset), ®s->gpio_pcor); +} + +void mipi_dsi_mux_panel(void) +{ + struct gpio_regs *panel_rst = (struct gpio_regs *)PANEL_RESET_GPIO_ADDR; + + /* It is temp solution to directly access gpio in RTD, need change to rpmsg later */ + + imx8ulp_iomux_setup_multiple_pads(panel_reset_pads, ARRAY_SIZE(panel_reset_pads)); + panel_rst->gpio_pddr |= (1 << PANEL_RESET_PIN); // set panel reset pin as output direction +} + +void mipi_dsi_panel_reset(void) +{ + /* It is temp solution to directly access gpio in RTD, need change to rpmsg later */ + struct gpio_regs *panel_rst = (struct gpio_regs *)PANEL_RESET_GPIO_ADDR; + imx8ulp_gpio_set_value(panel_rst, PANEL_RESET_PIN, 0); + mdelay(1); + imx8ulp_gpio_set_value(panel_rst, PANEL_RESET_PIN, 1); + mdelay(12); +} + +int board_init(void) +{ + /* When sync with M33 is failed, use local driver to set for video */ + if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_DM_VIDEO)) { + mipi_dsi_mux_panel(); + mipi_dsi_panel_reset(); + } + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + + +void board_quiesce_devices(void) +{ + /* Disable the power domains may used in u-boot before entering kernel */ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice *scmi_devpd; + int ret, i; + struct power_domain pd; + ulong ids[] = { + IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, IMX8ULP_PD_USDHC0, + IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, IMX8ULP_PD_DCNANO, + IMX8ULP_PD_MIPI_DSI}; + + ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd); + if (ret) { + printf("Cannot get scmi devpd: err=%d\n", ret); + return; + } + + pd.dev = scmi_devpd; + + for (i = 0; i < ARRAY_SIZE(ids); i++) { + pd.id = ids[i]; + ret = power_domain_off(&pd); + if (ret) + printf("power_domain_off %lu failed: err=%d\n", ids[i], ret); + } +#endif +} diff --git a/board/freescale/imx8ulp_watch/lpddr4x_timing.c b/board/freescale/imx8ulp_watch/lpddr4x_timing.c new file mode 100644 index 0000000000..5d54dfb84c --- /dev/null +++ b/board/freescale/imx8ulp_watch/lpddr4x_timing.c @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2022 NXP + * + * Generated code from NXP_DDR_tool + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0x4b00 }, /* 14 */ + { 0x2e06003c, 0x2edfa }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0xc0 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x2011001 }, /* 23 */ + { 0x2e060060, 0x2010000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x1604 }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040618 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0x50008 }, /* 46 */ + { 0x2e0600bc, 0x40309 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4000d29 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x4040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a04 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x41507 }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x1b }, /* 67 */ + { 0x2e060110, 0x16e }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0xe000f }, /* 73 */ + { 0x2e060128, 0x4a0026 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x7070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x1c001c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x3050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0x5b80 }, /* 113 */ + { 0x2e0601c8, 0x5b80 }, /* 114 */ + { 0x2e0601cc, 0x5b80 }, /* 115 */ + { 0x2e0601d0, 0x5b80 }, /* 116 */ + { 0x2e0601d4, 0x5b80 }, /* 117 */ + { 0x2e0601dc, 0xa02 }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0xa0014 }, /* 173 */ + { 0x2e0602b8, 0x4040018 }, /* 174 */ + { 0x2e0602bc, 0x18 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x71000914 }, /* 183 */ + { 0x2e0602e0, 0x7171 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x71717100 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20008 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80060 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0x50003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x1000103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x80a0505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x102 }, /* 309 */ + { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1b1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x2dc }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x894 }, /* 591 */ + { 0x2e060940, 0x1c98 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020408 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3060100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c03 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x201 }, /* 11 */ + { 0x2e062030, 0x7 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x2010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x34 }, /* 164 */ + { 0x2e062294, 0x2003e }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1806 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x1b }, /* 170 */ + { 0x2e0622ac, 0x16e }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0016 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010a05 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2080404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x320009 }, /* 189 */ + { 0x2e0622f8, 0x36000a }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1001801 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x190100 }, /* 196 */ + { 0x2e062314, 0x1000019 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x2000d }, /* 208 */ + { 0x2e062344, 0x140018 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0058 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x4090403 }, /* 222 */ + { 0x2e06237c, 0xbd8 }, /* 223 */ + { 0x2e062380, 0x20010005 }, /* 224 */ + { 0x2e062384, 0x80a0a03 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x2dc }, /* 232 */ + { 0x2e0623a4, 0x1c98 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x1c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0x4b00 }, /* 243 */ + { 0x2e0623d0, 0x17702 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0xc0 }, /* 246 */ + { 0x2e0623dc, 0x1c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x17702 }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10008 }, /* 254 */ + { 0x2e0623fc, 0x600040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44710004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19447100 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194471 }, /* 281 */ + { 0x2e062468, 0x71000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44710004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19447109 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194471 }, /* 288 */ + { 0x2e062484, 0x71000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44710914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19447100 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194471 }, /* 295 */ + { 0x2e0624a0, 0x71091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x9bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000100 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c0e01 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x118 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56472031 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2980298 }, /* 100 */ + { 0x2e064194, 0x2980298 }, /* 101 */ + { 0x2e064198, 0x2980298 }, /* 102 */ + { 0x2e06419c, 0x2980298 }, /* 103 */ + { 0x2e0641a0, 0x298 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x1940080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x9bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000100 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c0e01 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x118 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x2315647 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2980298 }, /* 356 */ + { 0x2e064594, 0x2980298 }, /* 357 */ + { 0x2e064598, 0x2980298 }, /* 358 */ + { 0x2e06459c, 0x2980298 }, /* 359 */ + { 0x2e0645a0, 0x298 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x1940080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x9bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000100 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c0e01 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x118 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x56470213 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2980298 }, /* 612 */ + { 0x2e064994, 0x2980298 }, /* 613 */ + { 0x2e064998, 0x2980298 }, /* 614 */ + { 0x2e06499c, 0x2980298 }, /* 615 */ + { 0x2e0649a0, 0x298 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x1940080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x9bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000100 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c0e01 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x118 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x20137564 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2980298 }, /* 868 */ + { 0x2e064d94, 0x2980298 }, /* 869 */ + { 0x2e064d98, 0x2980298 }, /* 870 */ + { 0x2e064d9c, 0x2980298 }, /* 871 */ + { 0x2e064da0, 0x298 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x1940080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241342 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x10701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x64 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11742 }, /* 1625 */ + { 0x2e065968, 0x3020600 }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x4afcc }, /* 1635 */ + { 0x2e065990, 0x8 }, /* 1636 */ + { 0x2e065994, 0x26f }, /* 1637 */ + { 0x2e06599c, 0x26f }, /* 1639 */ + { 0x2e0659a4, 0x26f00 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x26fcc }, /* 1643 */ + { 0x2e0659b4, 0x26f00 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x26f00 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x26f00 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x26f00 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { + { 0x2e064168, 0x3020100 }, /* 90 */ + { 0x2e064170, 0xc043e42 }, /* 92 */ + { 0x2e064174, 0xf0c1701 }, /* 93 */ + { 0x2e064180, 0x187 }, /* 96 */ + { 0x2e064184, 0x3200203 }, /* 97 */ + { 0x2e064190, 0x3070307 }, /* 100 */ + { 0x2e064194, 0x3070307 }, /* 101 */ + { 0x2e064198, 0x3070307 }, /* 102 */ + { 0x2e06419c, 0x3070307 }, /* 103 */ + { 0x2e0641a0, 0x307 }, /* 104 */ + { 0x2e0641c8, 0x1bd0080 }, /* 114 */ + { 0x2e064568, 0x3020100 }, /* 346 */ + { 0x2e064570, 0xc043e42 }, /* 348 */ + { 0x2e064574, 0xf0c1701 }, /* 349 */ + { 0x2e064580, 0x187 }, /* 352 */ + { 0x2e064584, 0x3200203 }, /* 353 */ + { 0x2e064590, 0x3070307 }, /* 356 */ + { 0x2e064594, 0x3070307 }, /* 357 */ + { 0x2e064598, 0x3070307 }, /* 358 */ + { 0x2e06459c, 0x3070307 }, /* 359 */ + { 0x2e0645a0, 0x307 }, /* 360 */ + { 0x2e0645c8, 0x1bd0080 }, /* 370 */ + { 0x2e064968, 0x3020100 }, /* 602 */ + { 0x2e064970, 0xc043e42 }, /* 604 */ + { 0x2e064974, 0xf0c1701 }, /* 605 */ + { 0x2e064980, 0x187 }, /* 608 */ + { 0x2e064984, 0x3200203 }, /* 609 */ + { 0x2e064990, 0x3070307 }, /* 612 */ + { 0x2e064994, 0x3070307 }, /* 613 */ + { 0x2e064998, 0x3070307 }, /* 614 */ + { 0x2e06499c, 0x3070307 }, /* 615 */ + { 0x2e0649a0, 0x307 }, /* 616 */ + { 0x2e0649c8, 0x1bd0080 }, /* 626 */ + { 0x2e064d68, 0x3020100 }, /* 858 */ + { 0x2e064d70, 0xc043e42 }, /* 860 */ + { 0x2e064d74, 0xf0c1701 }, /* 861 */ + { 0x2e064d80, 0x187 }, /* 864 */ + { 0x2e064d84, 0x3200203 }, /* 865 */ + { 0x2e064d90, 0x3070307 }, /* 868 */ + { 0x2e064d94, 0x3070307 }, /* 869 */ + { 0x2e064d98, 0x3070307 }, /* 870 */ + { 0x2e064d9c, 0x3070307 }, /* 871 */ + { 0x2e064da0, 0x307 }, /* 872 */ + { 0x2e064dc8, 0x1bd0080 }, /* 882 */ + { 0x2e06509c, 0x33e }, /* 1063 */ + { 0x2e06549c, 0x33e }, /* 1319 */ + { 0x2e065878, 0x10703 }, /* 1566 */ + { 0x2e065964, 0x1342 }, /* 1625 */ +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 192, 1056 }, +}; + diff --git a/board/freescale/imx8ulp_watch/spl.c b/board/freescale/imx8ulp_watch/spl.c new file mode 100644 index 0000000000..1dfb4f6f7f --- /dev/null +++ b/board/freescale/imx8ulp_watch/spl.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8ulp-pins.h> +#include <fsl_sec.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <asm/arch/ddr.h> +#include <asm/arch/rdc.h> +#include <asm/arch/upower.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/arch/clock.h> +#include <asm/arch/pcc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* Reboot in dual boot setting no need to init ddr again */ + bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT); + if (!ddr_enable) { + init_clk_ddr(); + ddr_init(&dram_timing); + } else { + /* reinit pfd/pfddiv and lpavnic except pll4*/ + cgc2_pll4_init(false); + } +} + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_BOOTROM_SUPPORT + return BOOT_DEVICE_BOOTROM; +#else + enum boot_device boot_device_spl = get_boot_device(); + + switch (boot_device_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + case USB2_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif +} + +#define PMIC_I2C_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_SRE_SLOW | PAD_CTL_ODE) +#define PMIC_MODE_PAD_CTRL (PAD_CTL_PUS_UP) + +static iomux_cfg_t const pmic_pads[] = { + IMX8ULP_PAD_PTB7__PMIC0_MODE2 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL), + IMX8ULP_PAD_PTB8__PMIC0_MODE1 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL), + IMX8ULP_PAD_PTB9__PMIC0_MODE0 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL), + IMX8ULP_PAD_PTB11__PMIC0_SCL | MUX_PAD_CTRL(PMIC_I2C_PAD_CTRL), + IMX8ULP_PAD_PTB10__PMIC0_SDA | MUX_PAD_CTRL(PMIC_I2C_PAD_CTRL), +}; + +void setup_iomux_pmic(void) +{ + imx8ulp_iomux_setup_multiple_pads(pmic_pads, ARRAY_SIZE(pmic_pads)); +} + +int power_init_board(void) +{ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + /* Set buck3 to 0.9v LD */ + upower_pmic_i2c_write(0x22, 0x18); + } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + /* Set buck3 to 1.0v ND */ + upower_pmic_i2c_write(0x22, 0x20); + } else { + /* Set buck3 to 1.1v OD */ + upower_pmic_i2c_write(0x22, 0x28); + + } + + return 0; +} + +void display_ele_fw_version(void) +{ + u32 fw_version, sha1, res; + int ret; + + ret = ahab_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf("ahab get firmware version failed %d, 0x%x\n", ret, res); + } else { + printf("ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000ff00)) >> 8, + (fw_version & (0x000000ff)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + u32 res; + int ret; + + ret = arch_cpu_init_dm(); + if (ret) + return; + + board_early_init_f(); + + preloader_console_init(); + + puts("Normal Boot\n"); + + display_ele_fw_version(); + + /* Set iomuxc0 for pmic when m33 is not booted */ + if (!m33_image_booted()) + setup_iomux_pmic(); + + /* Load the lposc fuse to work around ROM issue, + * The fuse depends on S400 to read. + */ + if (is_soc_rev(CHIP_REV_1_0)) + load_lposc_fuse(); + + upower_init(); + + power_init_board(); + + clock_init_late(); + + /* DDR initialization */ + spl_dram_init(); + + /* This must place after upower init, so access to MDA and MRC are valid */ + /* Init XRDC MDA */ + xrdc_init_mda(); + + /* Init XRDC MRC for VIDEO, DSP domains */ + xrdc_init_mrc(); + + /* Call it after PS16 power up */ + set_lpav_qos(); + + /* Asks S400 to release CAAM for A35 core */ + ret = ahab_release_caam(7, &res); + if (!ret) { + + /* Only two UCLASS_MISC devicese are present on the platform. There + * are MU and CAAM. Here we initialize CAAM once it's released by + * S400 firmware.. + */ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + } + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ahab_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } +} + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx93_evk/Kconfig b/board/freescale/imx93_evk/Kconfig new file mode 100644 index 0000000000..032e523198 --- /dev/null +++ b/board/freescale/imx93_evk/Kconfig @@ -0,0 +1,21 @@ +if TARGET_IMX93_11X11_EVK + +config SYS_BOARD + default "imx93_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_evk" + +config IMX93_EVK_LPDDR4X + bool "Using LPDDR4X Timing and PMIC voltage" + default y + select IMX9_LPDDR4X + help + Select the LPDDR4X timing and 0.6V VDDQ + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile new file mode 100644 index 0000000000..17956d24bf --- /dev/null +++ b/board/freescale/imx93_evk/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX9_LOW_DRIVE_MODE +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o +else +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o +endif +endif diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c new file mode 100644 index 0000000000..02eaffe396 --- /dev/null +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/global_data.h> +#include <asm/arch-imx9/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <power/pmic.h> +#include "../common/tcpc.h" +#include <dm/device.h> +#include <dm/uclass.h> +#include <usb.h> +#include <dwc3-uboot.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2) +#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(LPUART1_CLK_ROOT); + + return 0; +} + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; +struct tcpc_port portpd; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(2, 0x71); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(2, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config portpd_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +struct tcpc_port_config port1_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x51, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 9000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port pd\n"); + ret = tcpc_init(&portpd, portpd_config, NULL); + if (ret) { + printf("%s: tcpc portpd init failed, err=%d\n", + __func__, ret); + } + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } + + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + debug("%s %d\n", __func__, dev_seq(dev)); + + if (dev_seq(dev) == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + + tcpc_print_log(port_ptr); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif + +static int setup_fec(void) +{ + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_eqos(void) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + return set_clk_eqos(ENET_125MHZ); +} + +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + /* Enable EXT1_PWREN for PCIE_3.3V */ + ret = dm_gpio_lookup_name("gpio@22_13", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "EXT1_PWREN"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Deassert SD3_nRST */ + ret = dm_gpio_lookup_name("gpio@22_12", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "SD3_nRST"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); +} + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (CONFIG_IS_ENABLED(FEC_MXC)) + setup_fec(); + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + setup_eqos(); + + board_gpio_init(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "11X11_EVK"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} + diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c b/board/freescale/imx93_evk/lpddr4x_timing.c new file mode 100644 index 0000000000..59c9f274f2 --- /dev/null +++ b/board/freescale/imx93_evk/lpddr4x_timing.c @@ -0,0 +1,1488 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Generated code from NXP_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaaee001b }, + { 0x4e300108, 0x626ee273 }, + { 0x4e30010c, 0x5e18b }, + { 0x4e300100, 0x25ab321b }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300250, 0x2b }, + { 0x4e300254, 0x015b015b }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x16291314 }, + { 0x4e300304, 0x163110c }, + { 0x4e300308, 0xa200e3c }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300124, 0x1c770000 }, + { 0x4e300800, 0x43930002 }, + { 0x4e300804, 0x1f1f1f1f }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x3a5 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x419 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, }, +}; + diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c b/board/freescale/imx93_evk/lpddr4x_timing_ld.c new file mode 100644 index 0000000000..78d40cd6d9 --- /dev/null +++ b/board/freescale/imx93_evk/lpddr4x_timing_ld.c @@ -0,0 +1,1498 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaa77000e }, + { 0x4e300108, 0x1816b1aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300100, 0x12552100 }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0xaa00aa }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x11281109 }, + { 0x4e300304, 0xaa110a }, + { 0x4e300308, 0x620071e }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 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}, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x20c }, + { 0x2000c, 0x74 }, + { 0x2000d, 0x48e }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 1866mts 2D */ + .drate = 1866, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1866, }, +}; + diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c new file mode 100644 index 0000000000..9a041af30e --- /dev/null +++ b/board/freescale/imx93_evk/spl.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <command.h> +#include <cpu_func.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/imx93_pins.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch-mx7ulp/gpio.h> +#include <asm/mach-imx/syscounter.h> +#include <asm/mach-imx/s400_api.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <linux/delay.h> +#include <asm/arch/clock.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/ddr.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <asm/arch/trdc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + /* 0.75v for Low drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + /* 0.9v for Over drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = arch_cpu_init_dm(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + printf("SOC: 0x%x\n", gd->arch.soc_rev); + printf("LC: 0x%x\n", gd->arch.lifecycle); + } + + power_init_board(); + + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_core_max_clk(); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx93_qsb/Kconfig b/board/freescale/imx93_qsb/Kconfig new file mode 100644 index 0000000000..47eab96b70 --- /dev/null +++ b/board/freescale/imx93_qsb/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX93_9X9_QSB + +config SYS_BOARD + default "imx93_qsb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_qsb" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx93_qsb/Makefile b/board/freescale/imx93_qsb/Makefile new file mode 100644 index 0000000000..b4aca9bf1d --- /dev/null +++ b/board/freescale/imx93_qsb/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_qsb.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += lpddr4_timing.o +endif diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c new file mode 100644 index 0000000000..b5cb2709fc --- /dev/null +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/global_data.h> +#include <asm/arch-imx9/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <power/pmic.h> +#include "../common/tcpc.h" +#include <dm/device.h> +#include <dm/uclass.h> +#include <usb.h> +#include <dwc3-uboot.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2) +#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(LPUART1_CLK_ROOT); + + return 0; +} + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port portpd; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(0, 0x71); + } else + return -EINVAL; +} + +struct tcpc_port_config portpd_config = { + .i2c_bus = 0, /*i2c1*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +struct tcpc_port_config port1_config = { + .i2c_bus = 0, /*i2c1*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port pd\n"); + ret = tcpc_init(&portpd, portpd_config, NULL); + if (ret) { + printf("%s: tcpc portpd init failed, err=%d\n", + __func__, ret); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + port_ptr = &port1; + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) + ret = tcpc_disable_src_vbus(&port1); + + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + debug("%s %d\n", __func__, dev_seq(dev)); + + port_ptr = &port1; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + + tcpc_print_log(port_ptr); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_eqos(void) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + return set_clk_eqos(ENET_125MHZ); +} + +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + /* Enable EXT1_PWREN for PCIE_3.3V */ + ret = dm_gpio_lookup_name("gpio@22_13", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "EXT1_PWREN"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Deassert SD3_nRST */ + ret = dm_gpio_lookup_name("gpio@22_12", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "SD3_nRST"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); +} + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + setup_eqos(); + + board_gpio_init(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "(9X9_QSB"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} + diff --git a/board/freescale/imx93_qsb/lpddr4_timing.c b/board/freescale/imx93_qsb/lpddr4_timing.c new file mode 100644 index 0000000000..9eec154724 --- /dev/null +++ b/board/freescale/imx93_qsb/lpddr4_timing.c @@ -0,0 +1,1575 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaaee001b }, + { 0x4e300108, 0x626ee273 }, + { 0x4e30010c, 0x5e18b }, + { 0x4e300100, 0x25ab321b }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300250, 0x2b }, + { 0x4e300254, 0x15b015b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x26522613 }, + { 0x4e300304, 0x15b2217 }, + { 0x4e300308, 0xa380e3c }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300124, 0x1c770000 }, + { 0x4e300800, 0x43930002 }, + { 0x4e300804, 0x1f1f1f1f }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x12007d, 0x212 }, + { 0x12007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x1004d, 0x600 }, + { 0x1014d, 0x600 }, + { 0x1104d, 0x600 }, + { 0x1114d, 0x600 }, + { 0x11004d, 0x600 }, + { 0x11014d, 0x600 }, + { 0x11104d, 0x600 }, + { 0x11114d, 0x600 }, + { 0x10049, 0xe3f }, + { 0x10149, 0xe3f }, + { 0x11049, 0xe3f }, + { 0x11149, 0xe3f }, + { 0x110049, 0xe3f }, + { 0x110149, 0xe3f }, + { 0x111049, 0xe3f }, + { 0x111149, 0xe3f }, + { 0x43, 0x7f }, + { 0x1043, 0x7f }, + { 0x2043, 0x7f }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x11 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x3a5 }, + { 0x120008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0x10c }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x1200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x331b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x331b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x419 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x20c }, + { 0x12000c, 0x74 }, + { 0x12000d, 0x48e }, + { 0x12000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, }, +}; diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c new file mode 100644 index 0000000000..952854cc65 --- /dev/null +++ b/board/freescale/imx93_qsb/spl.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <command.h> +#include <cpu_func.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/imx93_pins.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch-mx7ulp/gpio.h> +#include <asm/mach-imx/syscounter.h> +#include <asm/mach-imx/s400_api.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <linux/delay.h> +#include <asm/arch/clock.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/ddr.h> +#include <power/pmic.h> +#include <power/pca9450.h> +#include <asm/arch/trdc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* 0.9v: for LPDDR4X 3722 */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* 1.1v for LPDDR4 */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = arch_cpu_init_dm(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + printf("SOC: 0x%x\n", gd->arch.soc_rev); + printf("LC: 0x%x\n", gd->arch.lifecycle); + } + power_init_board(); + + set_arm_core_max_clk(); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 5ab03b3340..5d0dd3afdc 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -121,7 +121,10 @@ int board_eth_init(struct bd_info *bis) if (is_serdes_configured(SGMII_TSEC1)) { puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; - } + tsec_info[num].interface = PHY_INTERFACE_MODE_SGMII; + } else { + tsec_info[num].interface = PHY_INTERFACE_MODE_NONE; + } num++; #endif #ifdef CONFIG_TSEC2 @@ -129,7 +132,10 @@ int board_eth_init(struct bd_info *bis) if (is_serdes_configured(SGMII_TSEC2)) { puts("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; - } + tsec_info[num].interface = PHY_INTERFACE_MODE_SGMII; + } else { + tsec_info[num].interface = PHY_INTERFACE_MODE_NONE; + } num++; #endif if (!num) { diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c index a9f162b974..177323031c 100644 --- a/board/freescale/ls1021aqds/eth.c +++ b/board/freescale/ls1021aqds/eth.c @@ -141,8 +141,10 @@ int board_eth_init(struct bd_info *bis) puts("eTSEC1 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + tsec_info[num].interface = PHY_INTERFACE_MODE_SGMII; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII; } num++; #endif @@ -152,14 +154,17 @@ int board_eth_init(struct bd_info *bis) puts("eTSEC2 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + tsec_info[num].interface = PHY_INTERFACE_MODE_SGMII; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII; num++; #endif if (!num) { diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index a2a87eaf35..8e874bebf7 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019, 2021 NXP + * Copyright 2019, 2021-2022 NXP */ #include <common.h> @@ -34,7 +34,7 @@ #include <fsl_qe.h> #endif #include <fsl_validate.h> - +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -530,6 +530,15 @@ int board_init(void) #if defined(CONFIG_SPL_BUILD) void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + ls102xa_smmu_stream_id_init(); } #endif diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 5d2e8015a0..bf3692a443 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -68,7 +68,11 @@ void cpld_set_defbank(void) void cpld_set_nand(void) { - u16 reg = CPLD_CFG_RCW_SRC_NAND; + u16 reg = CPLD_CFG_RCW_SRC_NAND_4K; + + if (CPLD_READ(cpld_ver) < 0x3) + reg = CPLD_CFG_RCW_SRC_NAND; + u8 reg5 = (u8)(reg >> 1); u8 reg6 = (u8)(reg & 1); diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index 2e757b557f..eed34d6354 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -41,5 +41,6 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_BANK_SEL_ALTBANK 0x04 #define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_NAND_4K 0x118 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 002869f435..5a740a0dfa 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2021 NXP + * Copyright 2021-2022 NXP */ #include <common.h> @@ -167,7 +167,7 @@ int checkboard(void) if (cfg_rcw_src == 0x25) printf("vBank %d\n", CPLD_READ(vbank)); - else if (cfg_rcw_src == 0x106) + else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118)) puts("NAND\n"); else printf("Invalid setting of SW4\n"); @@ -272,6 +272,39 @@ void fdt_del_qe(void *blob) } } +/* Update the address of the Aquantia PHY on the MDIO bus for boards revision + * v7.0 and up. Also rename the PHY node to align with the address change. + */ +void fdt_fixup_phy_addr(void *blob) +{ + const char phy_path[] = + "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1"; + int ret, offset, new_addr = AQR113C_PHY_ADDR; + char new_name[] = "ethernet-phy@00"; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + offset = fdt_path_offset(blob, phy_path); + if (offset < 0) { + printf("ethernet-phy@1 node not found in the dts\n"); + return; + } + + ret = fdt_setprop_u32(blob, offset, "reg", new_addr); + if (ret < 0) { + printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", + fdt_strerror(ret)); + return; + } + + sprintf(new_name, "ethernet-phy@%x", new_addr); + ret = fdt_set_name(blob, offset, new_name); + if (ret < 0) + printf("Unable to rename node ethernet-phy@1: %s\n", + fdt_strerror(ret)); +} + int ft_board_setup(void *blob, struct bd_info *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; @@ -290,6 +323,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif + fdt_fixup_phy_addr(blob); #endif fdt_fixup_icid(blob); @@ -313,6 +347,65 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +void nand_fixup() +{ + uint32_t csor = 0; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + /* Change NAND Flash PGS/SPRZ configuration */ + csor = CONFIG_SYS_NAND_CSOR; + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) + csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; + + if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64) + csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; + +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + set_ifc_csor(IFC_CS1, csor); + else if (cfg_rcw_src == 0x118) + set_ifc_csor(IFC_CS0, csor); + else { + if (src == BOOT_SOURCE_SD_MMC) + set_ifc_csor(IFC_CS1, csor); + else + printf("Invalid setting\n"); + } +#else +#ifdef CONFIG_NAND_BOOT + set_ifc_csor(IFC_CS0, csor); +#else + set_ifc_csor(IFC_CS1, csor); +#endif +#endif + + return; +} + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *blob) +{ + /* nand driver fix up */ + nand_fixup(); + + /* fdt fix up */ + fdt_fixup_phy_addr(blob); + + return 0; +} +#endif + u8 flash_read8(void *addr) { return __raw_readb(addr + 1); diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 22e43dffe7..f6467d40fc 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -408,3 +408,10 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SLL_LCDIF_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 9c355e4e23..4460117380 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -458,3 +458,11 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 0); + enable_lcdif_clock(LCDIF2_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 7e1c538677..8e725ff882 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -794,3 +794,11 @@ int checkboard(void) #endif return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 0); + enable_lcdif_clock(LCDIF2_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 221a1ba791..96d40af5da 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -446,6 +446,13 @@ void board_preboot_os(void) gpio_set_value(IMX_GPIO_NR(5, 9), 0); } +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); +#endif +} + #ifdef CONFIG_SPL_BUILD #include <linux/libfdt.h> #include <spl.h> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 72e4898ae8..23dbc67107 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -367,3 +367,10 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 9887aeee69..34a12cf108 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -249,6 +249,7 @@ int show_bootloader_menu(void) { break; case 2: do_reset(NULL, 0, 0, NULL); + break; case 3: board_recovery_setup(); break; diff --git a/board/toradex/apalis-imx8/Kconfig b/board/toradex/apalis-imx8/Kconfig index b43d6281b6..f16f9d2702 100644 --- a/board/toradex/apalis-imx8/Kconfig +++ b/board/toradex/apalis-imx8/Kconfig @@ -12,6 +12,9 @@ config SYS_CONFIG_NAME config TDX_CFG_BLOCK default y +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + config TDX_HAVE_MMC default y diff --git a/board/toradex/apalis-imx8/Makefile b/board/toradex/apalis-imx8/Makefile index a8c3eb7240..fe19cfdf69 100644 --- a/board/toradex/apalis-imx8/Makefile +++ b/board/toradex/apalis-imx8/Makefile @@ -1,6 +1,6 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright 2019 Toradex +# Copyright 2019-2022 Toradex # obj-y += apalis-imx8.o diff --git a/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg index 16183f9667..fc4aa74990 100644 --- a/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg +++ b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2019 Toradex + * Copyright 2019-2022 Toradex * * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure * and create imx8image boot image diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 04877fcd94..051149bd05 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2019 Toradex + * Copyright 2019-2022 Toradex */ #include <common.h> @@ -12,11 +12,15 @@ #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sci/sci.h> +#include <asm/arch/snvs_security_sc.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/io.h> +#include <command.h> #include <env.h> #include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> #include <linux/libfdt.h> #include "../common/tdx-cfg-block.h" @@ -28,22 +32,105 @@ DECLARE_GLOBAL_DATA_PTR; (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define PCB_VERS_DETECT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define PCB_VERS_DEFAULT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT)) + +#define TDX_USER_FUSE_BLOCK1_A 276 +#define TDX_USER_FUSE_BLOCK1_B 277 +#define TDX_USER_FUSE_BLOCK2_A 278 +#define TDX_USER_FUSE_BLOCK2_B 279 + +enum pcb_rev_t { + PCB_VERSION_1_0, + PCB_VERSION_1_1 +}; + +static iomux_cfg_t pcb_vers_detect[] = { + SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT), + SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DETECT), +}; + +static iomux_cfg_t pcb_vers_default[] = { + SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT), + SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(PCB_VERS_DEFAULT), +}; + static iomux_cfg_t uart1_pads[] = { SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +struct tdx_user_fuses { + u16 pid4; + u16 vers; + u8 ramid; +}; + static void setup_iomux_uart(void) { imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +static uint32_t do_get_tdx_user_fuse(int a, int b) +{ + sc_err_t sciErr; + u32 val_a = 0; + u32 val_b = 0; + + sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", a); + return 0; + } + + sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); + if (sciErr != SC_ERR_NONE) { + printf("Error reading out user fuse %d\n", b); + return 0; + } + + return ((val_a & 0xffff) << 16) | (val_b & 0xffff); +} + +static void get_tdx_user_fuse(struct tdx_user_fuses *tdxuserfuse) +{ + u32 fuse_block; + + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK2_A, + TDX_USER_FUSE_BLOCK2_B); + + /* + * Fuse block 2 acts as a backup area, if this reads 0 we want to + * use fuse block 1 + */ + if (fuse_block == 0) + fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK1_A, + TDX_USER_FUSE_BLOCK1_B); + + tdxuserfuse->pid4 = (fuse_block >> 18) & GENMASK(13, 0); + tdxuserfuse->vers = (fuse_block >> 4) & GENMASK(13, 0); + tdxuserfuse->ramid = fuse_block & GENMASK(3, 0); +} + void board_mem_get_layout(u64 *phys_sdram_1_start, u64 *phys_sdram_1_size, u64 *phys_sdram_2_start, u64 *phys_sdram_2_size) { u32 is_quadplus = 0, val = 0; + struct tdx_user_fuses tdxramfuses; sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); if (scierr == SC_ERR_NONE) { @@ -51,25 +138,44 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, is_quadplus = ((val >> 4) & 0x3) != 0x0; } + get_tdx_user_fuse(&tdxramfuses); + *phys_sdram_1_start = PHYS_SDRAM_1; *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; *phys_sdram_2_start = PHYS_SDRAM_2; - if (is_quadplus) - /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + + switch (tdxramfuses.ramid) { + case 1: + *phys_sdram_2_size = SZ_2G; + break; + case 2: *phys_sdram_2_size = 0x0UL; - else - *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + case 3: + *phys_sdram_2_size = SZ_2G; + break; + case 4: + *phys_sdram_2_size = SZ_4G + SZ_2G; + break; + default: + if (is_quadplus) + /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ + *phys_sdram_2_size = 0x0UL; + else + *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; + break; + } } int board_early_init_f(void) { sc_pm_clock_rate_t rate = SC_80MHZ; - sc_err_t err = 0; + int ret; /* Set UART1 clock root to 80 MHz and enable it */ - err = sc_pm_setup_uart(SC_R_UART_1, rate); - if (err != SC_ERR_NONE) - return 0; + ret = sc_pm_setup_uart(SC_R_UART_1, rate); + if (ret) + return ret; setup_iomux_uart(); @@ -77,25 +183,30 @@ int board_early_init_f(void) } #if CONFIG_IS_ENABLED(DM_GPIO) + +#define BKL1_GPIO IMX_GPIO_NR(1, 10) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS1_GPIO00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + static void board_gpio_init(void) { - /* TODO */ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + gpio_request(BKL1_GPIO, "BKL1_GPIO"); } #else static inline void board_gpio_init(void) {} #endif -#if IS_ENABLED(CONFIG_FEC_MXC) -#include <miiphy.h> - -int board_phy_config(struct phy_device *phydev) +/* + * Backlight off before OS handover + */ +void board_preboot_os(void) { - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; + gpio_direction_output(BKL1_GPIO, 0); } -#endif int checkboard(void) { @@ -107,10 +218,86 @@ int checkboard(void) return 0; } +static enum pcb_rev_t get_pcb_revision(void) +{ + unsigned int pcb_vers = 0; + + imx8_iomux_setup_multiple_pads(pcb_vers_detect, + ARRAY_SIZE(pcb_vers_detect)); + + gpio_request(IMX_GPIO_NR(1, 18), + "PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_00"); + gpio_request(IMX_GPIO_NR(1, 19), + "PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_01"); + gpio_direction_input(IMX_GPIO_NR(1, 18)); + gpio_direction_input(IMX_GPIO_NR(1, 19)); + + udelay(1000); + + pcb_vers = gpio_get_value(IMX_GPIO_NR(1, 18)); + pcb_vers |= gpio_get_value(IMX_GPIO_NR(1, 19)) << 1; + + /* Set muxing back to default values for saving energy */ + imx8_iomux_setup_multiple_pads(pcb_vers_default, + ARRAY_SIZE(pcb_vers_default)); + + switch (pcb_vers) { + case 0b11: + return PCB_VERSION_1_0; + case 0b10: + return PCB_VERSION_1_1; + default: + printf("Unknown PCB version=0x%x, default to V1.1\n", pcb_vers); + return PCB_VERSION_1_1; + } +} + +static void select_dt_from_module_version(void) +{ + env_set("soc", "imx8qm"); + env_set("variant", "-v1.1"); + + switch (tdx_hw_tag.prodid) { + /* Select Apalis iMX8QM device trees */ + case APALIS_IMX8QM_IT: + case APALIS_IMX8QM_WIFI_BT_IT: + case APALIS_IMX8QM_8GB_WIFI_BT_IT: + if (get_pcb_revision() == PCB_VERSION_1_0) + env_set("variant", ""); + break; + /* Select Apalis iMX8QP device trees */ + case APALIS_IMX8QP_WIFI_BT: + case APALIS_IMX8QP: + env_set("soc", "imx8qp"); + break; + default: + printf("Unknown Apalis iMX8 module\n"); + return; + } +} + +static int do_select_dt_from_module_version(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + select_dt_from_module_version(); + return 0; +} + +U_BOOT_CMD(select_dt_from_module_version, CONFIG_SYS_MAXARGS, 1, do_select_dt_from_module_version, + "\n", " - select devicetree from module version" +); + int board_init(void) { board_gpio_init(); + if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } + return 0; } @@ -119,7 +306,10 @@ int board_init(void) */ void reset_cpu(void) { - /* TODO */ + sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD); + + do { + } while (1); } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) @@ -142,5 +332,9 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + build_info(); + + select_dt_from_module_version(); + return 0; } diff --git a/board/toradex/colibri-imx8x/Kconfig b/board/toradex/colibri-imx8x/Kconfig index b89840a379..cb11e2c318 100644 --- a/board/toradex/colibri-imx8x/Kconfig +++ b/board/toradex/colibri-imx8x/Kconfig @@ -12,6 +12,9 @@ config SYS_CONFIG_NAME config TDX_CFG_BLOCK default y +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + config TDX_HAVE_MMC default y diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 169d4d04b1..36bc85fdf0 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -12,17 +12,21 @@ #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sci/sci.h> +#include <asm/arch/snvs_security_sc.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/io.h> #include <env.h> #include <errno.h> #include <linux/libfdt.h> +#include <usb.h> #include "../common/tdx-cfg-block.h" DECLARE_GLOBAL_DATA_PTR; +static struct gpio_desc gpio_usb_cdet; + #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ @@ -40,21 +44,44 @@ static void setup_iomux_uart(void) imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); } -void board_mem_get_layout(u64 *phys_sdram_1_start, - u64 *phys_sdram_1_size, - u64 *phys_sdram_2_start, - u64 *phys_sdram_2_size) +int board_ci_udc_phy_mode(void *__iomem phy_base, int phy_off) { - u32 is_dualx = 0, val = 0; - sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + int ret; - if (scierr == SC_ERR_NONE) { + switch ((phys_addr_t)phy_base) { + case USB_BASE_ADDR: + if (!dm_gpio_is_valid(&gpio_usb_cdet)) + return -ENODEV; + + ret = dm_gpio_get_value(&gpio_usb_cdet); + if (ret < 0) + return ret; + + return ret ? USB_INIT_DEVICE : USB_INIT_HOST; + default: + return USB_INIT_HOST; + } +} + +static int is_imx8dx(void) +{ + u32 val = 0; + sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val); + + if (sc_err == SC_ERR_NONE) { /* DX has two A35 cores disabled */ - is_dualx = (val & 0xf) != 0x0; + return (val & 0xf) != 0x0; } + return false; +} +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ *phys_sdram_1_start = PHYS_SDRAM_1; - if (is_dualx) + if (is_imx8dx()) /* Our DX based SKUs only have 1 GB RAM */ *phys_sdram_1_size = SZ_1G; else @@ -91,7 +118,14 @@ int board_early_init_f(void) #if IS_ENABLED(CONFIG_DM_GPIO) static void board_gpio_init(void) { - /* TODO */ + if (dm_gpio_lookup_name("GPIO5_9", &gpio_usb_cdet)) + return; + + if (dm_gpio_request(&gpio_usb_cdet, "usb_c_det")) + return; + + if (dm_gpio_set_dir_flags(&gpio_usb_cdet, GPIOD_IS_IN)) + return; } #else static inline void board_gpio_init(void) {} @@ -119,10 +153,29 @@ int checkboard(void) return 0; } +static void select_dt_from_module_version(void) +{ + /* + * The dtb filename is constructed from ${soc}-colibri-${fdt_board}.dtb. + * Set soc depending on the used SoC. + */ + if (is_imx8dx()) + env_set("soc", "imx8dx"); + else + env_set("soc", "imx8qxp"); +} + int board_init(void) { board_gpio_init(); + if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } + return 0; } @@ -154,5 +207,9 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + build_info(); + + select_dt_from_module_version(); + return 0; } diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 7cf2dfae97..31e63d1e9e 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -137,18 +137,29 @@ const struct toradex_som toradex_modules[] = { [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; -const char * const toradex_carrier_boards[] = { - [0] = "UNKNOWN CARRIER BOARD", - [155] = "Dahlia", - [156] = "Verdin Development Board", +struct pid4list { + int pid4; + char * const name; }; -const char * const toradex_display_adapters[] = { - [0] = "UNKNOWN DISPLAY ADAPTER", - [157] = "Verdin DSI to HDMI Adapter", - [159] = "Verdin DSI to LVDS Adapter", +const struct pid4list toradex_carrier_boards[] = { + /* the code assumes unknown at index 0 */ + {0, "UNKNOWN CARRIER BOARD"}, + {DAHLIA, "Dahlia"}, + {VERDIN_DEVELOPMENT_BOARD, "Verdin Development Board"}, + {YAVIA, "Yavia"}, +}; + +const struct pid4list toradex_display_adapters[] = { + /* the code assumes unknown at index 0 */ + {0, "UNKNOWN DISPLAY ADAPTER"}, + {VERDIN_DSI_TO_HDMI_ADAPTER, "Verdin DSI to HDMI Adapter"}, + {VERDIN_DSI_TO_LVDS_ADAPTER, "Verdin DSI to LVDS Adapter"}, }; const u32 toradex_ouis[] = { @@ -156,6 +167,32 @@ const u32 toradex_ouis[] = { [1] = 0x8c06cbUL, }; +const char * const get_toradex_carrier_boards(int pid4) +{ + int i, index = 0; + + for (i = 1; i < ARRAY_SIZE(toradex_carrier_boards); i++) { + if (pid4 == toradex_carrier_boards[i].pid4) { + index = i; + break; + } + } + return toradex_carrier_boards[index].name; +} + +const char * const get_toradex_display_adapters(int pid4) +{ + int i, index = 0; + + for (i = 1; i < ARRAY_SIZE(toradex_display_adapters); i++) { + if (pid4 == toradex_display_adapters[i].pid4) { + index = i; + break; + } + } + return toradex_display_adapters[index].name; +} + static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr) { int i; @@ -635,10 +672,11 @@ static int get_cfgblock_carrier_interactive(void) int ret = 0; printf("Supported carrier boards:\n"); - printf("CARRIER BOARD NAME\t\t [ID]\n"); + printf("%30s\t[ID]\n", "CARRIER BOARD NAME"); for (int i = 0; i < ARRAY_SIZE(toradex_carrier_boards); i++) - if (toradex_carrier_boards[i]) - printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i); + printf("%30s\t[%d]\n", + toradex_carrier_boards[i].name, + toradex_carrier_boards[i].pid4); sprintf(message, "Choose your carrier board (provide ID): "); len = cli_readline(message); diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 32e4c6f687..017f8a8f19 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -94,11 +94,17 @@ enum { VERDIN_IMX8MPQ_8GB_WIFI_BT, APALIS_IMX8QM_8GB_WIFI_BT_IT, VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, + /* 69 */ + VERDIN_IMX8MPQ_8GB_WIFI_BT_IT = 70, /* 70 */ + /* 71-85 */ + VERDIN_IMX8MMDL_2G_IT = 86, + VERDIN_IMX8MMQ_2G_IT_NO_CAN, }; enum { DAHLIA = 155, VERDIN_DEVELOPMENT_BOARD = 156, + YAVIA = 173, }; enum { @@ -107,7 +113,6 @@ enum { }; extern const struct toradex_som toradex_modules[]; -extern const char * const toradex_carrier_boards[]; extern bool valid_cfgblock; extern struct toradex_hw tdx_hw_tag; extern struct toradex_hw tdx_car_hw_tag; @@ -117,7 +122,8 @@ extern u32 tdx_car_serial; int read_tdx_cfg_block(void); int read_tdx_cfg_block_carrier(void); - +const char * const get_toradex_carrier_boards(int pid4); +const char * const get_toradex_display_adapters(int pid4); int try_migrate_tdx_cfg_block_carrier(void); void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr); diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index fadbe45541..de94036c47 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -31,7 +31,7 @@ static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA static char tdx_car_serial_str[SERIAL_STR_LEN + 1]; static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; -static char *tdx_carrier_board_name; +static const char *tdx_carrier_board_name; #endif #if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) @@ -125,8 +125,8 @@ int show_board_info(void) printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n"); try_migrate_tdx_cfg_block_carrier(); } else { - tdx_carrier_board_name = (char *) - toradex_carrier_boards[tdx_car_hw_tag.prodid]; + tdx_carrier_board_name = + get_toradex_carrier_boards(tdx_car_hw_tag.prodid); snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str), "%08u", tdx_car_serial); diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c index d114abf9d6..4dfec679b1 100644 --- a/board/toradex/verdin-imx8mm/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c @@ -1,12 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 Toradex + * Copyright 2023 Toradex * * Generated code from MX8M_DDR_tool - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga * - * DDR calibration created with mscale_ddr_tool_v210_setup.exe using - * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019. + * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using + * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023. */ #include <linux/kernel.h> @@ -17,22 +16,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400304, 0x1}, {0x3d400030, 0x1}, {0x3d400000, 0xa1080020}, - {0x3d400020, 0x203}, + {0x3d400020, 0x202}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x5b00d2}, + {0x3d400064, 0x2d00d2}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, {0x3d4000e0, 0x310000}, {0x3d4000e8, 0x66004d}, {0x3d4000ec, 0x16004d}, - {0x3d400100, 0x191e1920}, + {0x3d400100, 0x191e0c20}, {0x3d400104, 0x60630}, {0x3d40010c, 0xb0b000}, {0x3d400110, 0xe04080e}, {0x3d400114, 0x2040c0c}, {0x3d400118, 0x1010007}, - {0x3d40011c, 0x401}, + {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, {0x3d400138, 0xd8}, @@ -49,7 +48,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d4001b0, 0x11}, {0x3d4001c0, 0x1}, {0x3d4001c4, 0x1}, - {0x3d4000f4, 0xc99}, + {0x3d4000f4, 0x699}, {0x3d400108, 0x70e1617}, {0x3d400200, 0x1f}, {0x3d40020c, 0x0}, @@ -57,6 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -68,22 +68,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400498, 0x620096}, {0x3d40049c, 0x1100e07}, {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x1}, + {0x3d402020, 0x0}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0xc001c}, + {0x3d402064, 0x6001c}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040305}, + {0x3d402100, 0xa040105}, {0x3d402104, 0x30407}, {0x3d402108, 0x203060b}, {0x3d40210c, 0x505000}, {0x3d402110, 0x2040202}, {0x3d402114, 0x2030202}, {0x3d402118, 0x1010004}, - {0x3d40211c, 0x301}, + {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, {0x3d402138, 0x1d}, @@ -92,8 +92,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402190, 0x3818200}, {0x3d402194, 0x80303}, {0x3d4021b4, 0x100}, - {0x3d4020f4, 0xc99}, - {0x3d403020, 0x1}, + {0x3d4020f4, 0x599}, + {0x3d403020, 0x0}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, {0x3d403064, 0x30007}, @@ -108,7 +108,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403110, 0x2040202}, {0x3d403114, 0x2030202}, {0x3d403118, 0x1010004}, - {0x3d40311c, 0x301}, + {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, {0x3d403138, 0x8}, @@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403190, 0x3818200}, {0x3d403194, 0x80303}, {0x3d4031b4, 0x100}, - {0x3d4030f4, 0xc99}, + {0x3d4030f4, 0x599}, {0x3d400028, 0x0}, }; @@ -205,8 +205,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x220024, 0x1ab}, {0x2003a, 0x0}, {0x20056, 0x3}, - {0x120056, 0xa}, - {0x220056, 0xa}, + {0x120056, 0x3}, + {0x220056, 0x3}, {0x1004d, 0xe00}, {0x1014d, 0xe00}, {0x1104d, 0xe00}, @@ -1058,7 +1058,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x2dd4}, {0x5401a, 0x31}, @@ -1098,7 +1097,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1138,7 +1136,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1204,7 +1201,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0x5403b, 0x4d}, {0x5403c, 0x4d}, {0x5403d, 0x1600}, - { 0xd0000, 0x1 }, + {0xd0000, 0x1}, }; /* DRAM PHY init engine image */ @@ -1697,15 +1694,15 @@ struct dram_cfg_param ddr_phy_pie[] = { {0x400d6, 0x20a}, {0x400d7, 0x20b}, {0x2003a, 0x2}, - {0x2000b, 0x5d}, + {0x2000b, 0x34b}, {0x2000c, 0xbb}, {0x2000d, 0x753}, {0x2000e, 0x2c}, - {0x12000b, 0xc}, + {0x12000b, 0x70}, {0x12000c, 0x19}, {0x12000d, 0xfa}, {0x12000e, 0x10}, - {0x22000b, 0x3}, + {0x22000b, 0x1c}, {0x22000c, 0x6}, {0x22000d, 0x3e}, {0x22000e, 0x10}, @@ -1846,5 +1843,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = {3000, 400, 100,}, }; diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 067e8621eb..c2e43368a9 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -61,13 +61,6 @@ void spl_board_init(void) if (ret) printf("Failed to initialize %s: %d\n", dev->name, ret); } - - /* Serial download mode */ - if (is_usb_boot()) { - puts("Back to ROM, SDP\n"); - restore_boot_params(); - } - puts("Normal Boot\n"); } #ifdef CONFIG_SPL_LOAD_FIT diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 3e00d9b51e..29ea31e146 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -13,6 +13,33 @@ #include <linux/kernel.h> #include <asm/arch/ddr.h> +#include "lpddr4_timing.h" + +struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = { + { 0x3d400000, 0xa1080020}, + { 0x3d400200, 0x1f}, + { 0x3d40021c, 0xf07} +}; + +struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; struct dram_cfg_param ddr_ddrc_cfg[] = { /** Initialize DDRC registers **/ @@ -21,9 +48,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d400070, 0x61027f10 }, - { 0x3d400074, 0x7b0 }, + { 0x3d400064, 0x7a017c }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, @@ -31,15 +58,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, + { 0x3d400104, 0x8083f }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x12040a12 }, { 0x3d400114, 0x2050f0f }, { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, + { 0x3d40011c, 0x502 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -53,15 +80,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, - { 0x3d400200, 0x18 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, + { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, + { 0x3d40021c, 0xf08 }, { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -77,7 +105,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402020, 0x1001 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -89,20 +117,20 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -114,16 +142,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -1700,15 +1728,15 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x7d }, + { 0x2000b, 0x465 }, { 0x2000c, 0xfa }, { 0x2000d, 0x9c4 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1834,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { }, }; -struct dram_cfg_param ddr_ddrc_cfg2[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x1303 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d400070, 0x61027f10 }, - { 0x3d400074, 0x7b0 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, - { 0x3d400200, 0x1f }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1001 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, - { 0x3d400028, 0x0 }, -}; - -/* P0 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg2[] = { - { - /* P0 4000mts 1D */ - .drate = 4000, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2), - }, - { - /* P0 4000mts 2D */ - .drate = 4000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2), - }, -}; - -/* quad die, dual rank aka 8 GB DDR timing config params */ +/* ddr timing config params */ struct dram_timing_info dram_timing = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), @@ -2153,17 +1877,36 @@ struct dram_timing_info dram_timing = { .fsp_table = { 4000, 400, 100, }, }; -/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */ -struct dram_timing_info dram_timing2 = { - .ddrc_cfg = ddr_ddrc_cfg2, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg2, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, -}; +static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz, + struct dram_cfg_param *patch, int patch_sz) +{ + int i, j; + + for (i = 0; i < cfg_sz; i++) + for (j = 0; j < patch_sz; j++) + if (cfg[i].reg == patch[j].reg) + cfg[i].val = patch[j].val; +} + +void lpddr4_single_rank_training_patch(void) +{ + apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg), + ddr_ddrc_cfg_single_rank_patch, + ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg), + ddr_fsp0_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg), + ddr_fsp1_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg), + ddr_fsp2_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg), + ddr_fsp0_2d_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch)); +} diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.h b/board/toradex/verdin-imx8mp/lpddr4_timing.h new file mode 100644 index 0000000000..93f3e2fb86 --- /dev/null +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2022 Toradex + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void lpddr4_single_rank_training_patch(void); + +#endif /* __LPDDR4_TIMING_H__ */ + diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 6f1931ffac..b901038e90 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -17,10 +17,11 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/arch/ddr.h> +#include <dm/device.h> +#include <dm/uclass.h> #include <power/pmic.h> #include <power/pca9450.h> - -extern struct dram_timing_info dram_timing2; +#include "lpddr4_timing.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,17 +33,32 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { /* - * try configuring for quad die, dual rank aka 8 GB falling back to - * dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails + * Try configuring for dual rank memory falling back to single rank */ - if (ddr_init(&dram_timing)) { - printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n"); - ddr_init(&dram_timing2); + if (!ddr_init(&dram_timing)) { + printf("DDR configured as dual rank\n"); + return; + } + + lpddr4_single_rank_training_patch(); + if (!ddr_init(&dram_timing)) { + printf("DDR configured as single rank\n"); + return; } + printf("DDR configuration failed\n"); } void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + /* * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does * not allow to change it. Should set the clock after PMIC diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 4a0840e999..e16841c375 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -235,7 +235,8 @@ static void select_dt_from_module_version(void) */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT); + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT); } if (is_wifi) diff --git a/common/init/board_init.c b/common/init/board_init.c index eab5ee1395..6a55026177 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,9 +78,11 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ +#ifndef CONFIG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); #endif +#endif /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ top = rounddown(top-sizeof(struct global_data), 16); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 495ed37c40..90b1ef4148 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -457,6 +457,7 @@ config SPL_FIT_IMAGE_TINY depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 default y if ARCH_IMX8M + default y if ARCH_IMX9 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. diff --git a/common/spl/spl.c b/common/spl/spl.c index b452d4feeb..c9750ee163 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -20,6 +20,7 @@ #include <serial.h> #include <spl.h> #include <asm/global_data.h> +#include <asm-generic/gpio.h> #include <asm/u-boot.h> #include <nand.h> #include <fat.h> @@ -743,6 +744,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } } + if (CONFIG_IS_ENABLED(GPIO_HOG)) + gpio_hog_probe_all(); + #if CONFIG_IS_ENABLED(BOARD_INIT) spl_board_init(); #endif diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 9d5a6dccec..1ab201b2f2 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -736,6 +736,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, return 0; ctx.fit = spl_load_simple_fit_fix_load(ctx.fit); + if (ctx.fit == NULL) { + return -1; + } ret = spl_simple_fit_parse(&ctx); if (ret < 0) diff --git a/common/usb_hub.c b/common/usb_hub.c index 990993aa2f..f231d711d8 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -166,7 +166,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub) int i; struct usb_device *dev; unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2; - const char *env; + const char __maybe_unused *env; dev = hub->pusb_dev; @@ -191,10 +191,12 @@ static void usb_hub_power_on(struct usb_hub_device *hub) * but allow this time to be increased via env variable as some * devices break the spec and require longer warm-up times */ +#if CONFIG_IS_ENABLED(ENV_SUPPORT) env = env_get("usb_pgood_delay"); if (env) pgood_delay = max(pgood_delay, (unsigned)simple_strtol(env, NULL, 0)); +#endif debug("pgood_delay=%dms\n", pgood_delay); /* diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 3ad539c4f2..8ff0792ccc 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=3 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 @@ -10,17 +10,25 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 CONFIG_TARGET_APALIS_IMX8=y +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_SYS_LOAD_ADDR=0x95400000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-apalis${variant}-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y @@ -31,6 +39,8 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_EXT4_WRITE=y @@ -43,8 +53,15 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x08000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y @@ -60,6 +77,8 @@ CONFIG_FEC_MXC_SHARE_MDIO=y CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_CDNS3_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8=y CONFIG_POWER_DOMAIN=y @@ -71,4 +90,15 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_USB_PORT_AUTO=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 645ddcef53..0e69fb3fde 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=3 CONFIG_SYS_MEMTEST_START=0x88000000 CONFIG_SYS_MEMTEST_END=0x89000000 @@ -10,25 +10,37 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 CONFIG_TARGET_COLIBRI_IMX8X=y +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y -CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_SYS_LOAD_ADDR=0x95c00000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Colibri iMX8X # " CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_CMD_EXT4_WRITE=y @@ -41,8 +53,15 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x08000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y CONFIG_FXL6408_GPIO=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y @@ -58,6 +77,8 @@ CONFIG_FEC_MXC_SHARE_MDIO=y CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_CDNS3_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8=y CONFIG_POWER_DOMAIN=y @@ -69,4 +90,14 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/configs/imx8dx_17x17_val_defconfig b/configs/imx8dx_17x17_val_defconfig index 882905225a..f46b604f58 100644 --- a/configs/imx8dx_17x17_val_defconfig +++ b/configs/imx8dx_17x17_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dx_mek_defconfig b/configs/imx8dx_mek_defconfig index 083b819777..e193c7de16 100644 --- a/configs/imx8dx_mek_defconfig +++ b/configs/imx8dx_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dx_mek_fspi_defconfig b/configs/imx8dx_mek_fspi_defconfig index df26f991e7..d939c86a89 100644 --- a/configs/imx8dx_mek_fspi_defconfig +++ b/configs/imx8dx_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_defconfig b/configs/imx8dxl_ddr3l_evk_defconfig index 421d3e1181..36b0b83a5d 100644 --- a/configs/imx8dxl_ddr3l_evk_defconfig +++ b/configs/imx8dxl_ddr3l_evk_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_fspi_defconfig b/configs/imx8dxl_ddr3l_evk_fspi_defconfig index 9f4856954e..cea4f6d331 100644 --- a/configs/imx8dxl_ddr3l_evk_fspi_defconfig +++ b/configs/imx8dxl_ddr3l_evk_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_nand_defconfig b/configs/imx8dxl_ddr3l_evk_nand_defconfig index 7a92c318ce..92dab96d27 100644 --- a/configs/imx8dxl_ddr3l_evk_nand_defconfig +++ b/configs/imx8dxl_ddr3l_evk_nand_defconfig @@ -43,7 +43,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_defconfig b/configs/imx8dxl_evk_defconfig index 4341d7f919..36a056e2e9 100644 --- a/configs/imx8dxl_evk_defconfig +++ b/configs/imx8dxl_evk_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_fspi_defconfig b/configs/imx8dxl_evk_fspi_defconfig index 8248dcd839..f7fe652cdf 100644 --- a/configs/imx8dxl_evk_fspi_defconfig +++ b/configs/imx8dxl_evk_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_lcd_defconfig b/configs/imx8dxl_evk_lcd_defconfig index f2091fed79..59222826c0 100644 --- a/configs/imx8dxl_evk_lcd_defconfig +++ b/configs/imx8dxl_evk_lcd_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_phantom_mek_defconfig b/configs/imx8dxl_phantom_mek_defconfig index 87eb60cf59..90c17f7417 100644 --- a/configs/imx8dxl_phantom_mek_defconfig +++ b/configs/imx8dxl_phantom_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_phantom_mek_fspi_defconfig b/configs/imx8dxl_phantom_mek_fspi_defconfig index 25a666c8fd..17f1671013 100644 --- a/configs/imx8dxl_phantom_mek_fspi_defconfig +++ b/configs/imx8dxl_phantom_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mm_ab2_defconfig b/configs/imx8mm_ab2_defconfig new file mode 100644 index 0000000000..d0e5193ec6 --- /dev/null +++ b/configs/imx8mm_ab2_defconfig @@ -0,0 +1,194 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_AB2=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ab2" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ab2.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_IMG_LOAD_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 + +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_SPL_RSA=y +CONFIG_SHA384=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_AUTHENTICATE=y +CONFIG_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_TEE=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_HAVE_CAPSULE_UPDATE=y +CONFIG_FIT_SIGNATURE=y diff --git a/configs/imx8mm_ddr3l_val_defconfig b/configs/imx8mm_ddr3l_val_defconfig index 9b84bd1bec..3178976fe8 100644 --- a/configs/imx8mm_ddr3l_val_defconfig +++ b/configs/imx8mm_ddr3l_val_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_ab2_defconfig b/configs/imx8mm_ddr4_ab2_defconfig new file mode 100644 index 0000000000..84857b04a1 --- /dev/null +++ b/configs/imx8mm_ddr4_ab2_defconfig @@ -0,0 +1,164 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_AB2=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-ab2" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-ab2.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_IMG_LOAD_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_FSL_ESDHC_IMX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SPL_POWER_LEGACY=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_POWER_I2C=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 + +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_NAND_MXS_USE_MINIMUM_ECC=y +CONFIG_SYS_NAND_ONFI_DETECTION=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_MXS=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mm_ddr4_evk_android_defconfig b/configs/imx8mm_ddr4_evk_android_defconfig index 80e0d93775..7fd463fa19 100644 --- a/configs/imx8mm_ddr4_evk_android_defconfig +++ b/configs/imx8mm_ddr4_evk_android_defconfig @@ -170,3 +170,4 @@ CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_ddr4_evk_android_uuu_defconfig b/configs/imx8mm_ddr4_evk_android_uuu_defconfig index d6c5cb11d1..b39916c30c 100644 --- a/configs/imx8mm_ddr4_evk_android_uuu_defconfig +++ b/configs/imx8mm_ddr4_evk_android_uuu_defconfig @@ -165,3 +165,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig index a70a951992..4f020d7c19 100644 --- a/configs/imx8mm_ddr4_evk_defconfig +++ b/configs/imx8mm_ddr4_evk_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig index f4e93d0ab0..4a648a7ea5 100644 --- a/configs/imx8mm_ddr4_evk_nand_defconfig +++ b/configs/imx8mm_ddr4_evk_nand_defconfig @@ -45,7 +45,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_val_defconfig b/configs/imx8mm_ddr4_val_defconfig index 6a369e750a..f163c4b2c2 100644 --- a/configs/imx8mm_ddr4_val_defconfig +++ b/configs/imx8mm_ddr4_val_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_evk_1g_ddr_android_defconfig b/configs/imx8mm_evk_1g_ddr_android_defconfig index 5133f38cd3..94dd53eeca 100644 --- a/configs/imx8mm_evk_1g_ddr_android_defconfig +++ b/configs/imx8mm_evk_1g_ddr_android_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_IMX8M_1G_MEMORY=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_defconfig b/configs/imx8mm_evk_4g_android_defconfig index 7f2882c5a6..e6d3407e23 100644 --- a/configs/imx8mm_evk_4g_android_defconfig +++ b/configs/imx8mm_evk_4g_android_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_IMX8M_4G_LPDDR4=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_trusty_defconfig b/configs/imx8mm_evk_4g_android_trusty_defconfig index bf48059cc7..52c0e4b8df 100644 --- a/configs/imx8mm_evk_4g_android_trusty_defconfig +++ b/configs/imx8mm_evk_4g_android_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mm" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_uuu_defconfig b/configs/imx8mm_evk_4g_android_uuu_defconfig index bbe331da0a..ec8b3bb827 100644 --- a/configs/imx8mm_evk_4g_android_uuu_defconfig +++ b/configs/imx8mm_evk_4g_android_uuu_defconfig @@ -199,3 +199,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n CONFIG_IMX8M_4G_LPDDR4=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_defconfig b/configs/imx8mm_evk_android_defconfig index d7ffc14bec..32e7a71742 100644 --- a/configs/imx8mm_evk_android_defconfig +++ b/configs/imx8mm_evk_android_defconfig @@ -203,3 +203,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_dual_defconfig b/configs/imx8mm_evk_android_dual_defconfig index adad43db54..b5e3853d6c 100644 --- a/configs/imx8mm_evk_android_dual_defconfig +++ b/configs/imx8mm_evk_android_dual_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_defconfig b/configs/imx8mm_evk_android_trusty_defconfig index e5023f7521..ca516701a3 100644 --- a/configs/imx8mm_evk_android_trusty_defconfig +++ b/configs/imx8mm_evk_android_trusty_defconfig @@ -209,3 +209,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mm" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_dual_defconfig b/configs/imx8mm_evk_android_trusty_dual_defconfig index a609d53ff3..852cff0bd4 100644 --- a/configs/imx8mm_evk_android_trusty_dual_defconfig +++ b/configs/imx8mm_evk_android_trusty_dual_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig index 50c5a06872..1f9bbc2da1 100644 --- a/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig +++ b/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig @@ -209,5 +209,7 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mm" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_uuu_defconfig b/configs/imx8mm_evk_android_uuu_defconfig index 7a6c245d17..479346249d 100644 --- a/configs/imx8mm_evk_android_uuu_defconfig +++ b/configs/imx8mm_evk_android_uuu_defconfig @@ -198,3 +198,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ca1c4a268a..1d86997236 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index cef425149f..d92c66f4e1 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -45,7 +45,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ab2_defconfig b/configs/imx8mn_ab2_defconfig new file mode 100644 index 0000000000..1cfda9e150 --- /dev/null +++ b/configs/imx8mn_ab2_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MN_AB2=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ab2" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ab2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_IMG_LOAD_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y diff --git a/configs/imx8mn_ddr3l_ab2_defconfig b/configs/imx8mn_ddr3l_ab2_defconfig new file mode 100644 index 0000000000..ac939df584 --- /dev/null +++ b/configs/imx8mn_ddr3l_ab2_defconfig @@ -0,0 +1,142 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x70000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MN_DDR3L_AB2=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-ab2" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-ab2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_IMG_LOAD_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig index fef1be5027..81ed94d8ae 100644 --- a/configs/imx8mn_ddr3l_evk_defconfig +++ b/configs/imx8mn_ddr3l_evk_defconfig @@ -50,7 +50,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr4_ab2_defconfig b/configs/imx8mn_ddr4_ab2_defconfig new file mode 100644 index 0000000000..63b77093cd --- /dev/null +++ b/configs/imx8mn_ddr4_ab2_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR4_AB2=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-ab2" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-ab2.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_IMG_LOAD_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 097ff4f5f1..9db46d225d 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr4_evk_ld_defconfig b/configs/imx8mn_ddr4_evk_ld_defconfig index 0db9422123..8fe4b7d861 100644 --- a/configs/imx8mn_ddr4_evk_ld_defconfig +++ b/configs/imx8mn_ddr4_evk_ld_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mn_evk_android_trusty_secure_unlock_dual_defconfig index f9424aada2..782355777c 100644 --- a/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig +++ b/configs/imx8mn_evk_android_trusty_secure_unlock_dual_defconfig @@ -185,5 +185,6 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mn" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mn" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MN" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 20c2ff2a52..07a03b0e01 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -53,7 +53,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mn_evk_ld_defconfig b/configs/imx8mn_evk_ld_defconfig index b2d30247ab..5772625672 100644 --- a/configs/imx8mn_evk_ld_defconfig +++ b/configs/imx8mn_evk_ld_defconfig @@ -50,7 +50,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_defconfig b/configs/imx8mp_ddr4_evk_defconfig index 028a5b82d3..686c2b299f 100644 --- a/configs/imx8mp_ddr4_evk_defconfig +++ b/configs/imx8mp_ddr4_evk_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig index 920fa8ee06..ad516ea1f4 100644 --- a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig +++ b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_nand_defconfig b/configs/imx8mp_ddr4_evk_nand_defconfig index 8aaf3fad38..7286989a12 100644 --- a/configs/imx8mp_ddr4_evk_nand_defconfig +++ b/configs/imx8mp_ddr4_evk_nand_defconfig @@ -46,7 +46,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_evk_android_trusty_powersave_defconfig b/configs/imx8mp_evk_android_trusty_powersave_dual_defconfig index 260fd422d8..ac6a1998fd 100644 --- a/configs/imx8mp_evk_android_trusty_powersave_defconfig +++ b/configs/imx8mp_evk_android_trusty_powersave_dual_defconfig @@ -193,3 +193,5 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MP" CONFIG_IMX8M_VDD_SOC_850MV=y CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mp_evk_android_trusty_secure_unlock_dual_defconfig index b1f62640ed..1e7dfc8d3f 100644 --- a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig +++ b/configs/imx8mp_evk_android_trusty_secure_unlock_dual_defconfig @@ -191,5 +191,6 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MP" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 393e9b8aba..2dc3ebc5b9 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -51,7 +51,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mp_evk_inline_ecc_defconfig b/configs/imx8mp_evk_inline_ecc_defconfig index b8a82849ab..e07340744e 100644 --- a/configs/imx8mp_evk_inline_ecc_defconfig +++ b/configs/imx8mp_evk_inline_ecc_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_evk_ndm_defconfig b/configs/imx8mp_evk_ndm_defconfig index ae66220d74..84049e7fe1 100644 --- a/configs/imx8mp_evk_ndm_defconfig +++ b/configs/imx8mp_evk_ndm_defconfig @@ -52,7 +52,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mq_ddr3l_val_defconfig b/configs/imx8mq_ddr3l_val_defconfig index d655205f7f..6096880d6c 100644 --- a/configs/imx8mq_ddr3l_val_defconfig +++ b/configs/imx8mq_ddr3l_val_defconfig @@ -46,7 +46,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_ddr4_val_defconfig b/configs/imx8mq_ddr4_val_defconfig index 8daa255b14..f912ba647d 100644 --- a/configs/imx8mq_ddr4_val_defconfig +++ b/configs/imx8mq_ddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_ddr4_val_nand_defconfig b/configs/imx8mq_ddr4_val_nand_defconfig index 8aea657047..f8485cc2d7 100644 --- a/configs/imx8mq_ddr4_val_nand_defconfig +++ b/configs/imx8mq_ddr4_val_nand_defconfig @@ -45,7 +45,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_evk_android_defconfig b/configs/imx8mq_evk_android_defconfig index b74492e9f9..9d5dc1de40 100644 --- a/configs/imx8mq_evk_android_defconfig +++ b/configs/imx8mq_evk_android_defconfig @@ -167,3 +167,4 @@ CONFIG_AVB_WARNING_LOGO_ROWS=0x60 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_dual_defconfig b/configs/imx8mq_evk_android_dual_defconfig index 4c428fc569..917e83e850 100644 --- a/configs/imx8mq_evk_android_dual_defconfig +++ b/configs/imx8mq_evk_android_dual_defconfig @@ -168,3 +168,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_defconfig b/configs/imx8mq_evk_android_trusty_defconfig index 075e9e887d..a9740ecda9 100644 --- a/configs/imx8mq_evk_android_trusty_defconfig +++ b/configs/imx8mq_evk_android_trusty_defconfig @@ -173,3 +173,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mq" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_dual_defconfig b/configs/imx8mq_evk_android_trusty_dual_defconfig index 4763648ba7..648b77bfc5 100644 --- a/configs/imx8mq_evk_android_trusty_dual_defconfig +++ b/configs/imx8mq_evk_android_trusty_dual_defconfig @@ -172,3 +172,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig index 5a00d4e7c9..f406981aa3 100644 --- a/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig +++ b/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig @@ -173,5 +173,7 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mq" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_uuu_defconfig b/configs/imx8mq_evk_android_uuu_defconfig index ed696565b7..460db0b7dc 100644 --- a/configs/imx8mq_evk_android_uuu_defconfig +++ b/configs/imx8mq_evk_android_uuu_defconfig @@ -161,3 +161,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index dc2c5003f2..51f24980cc 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -49,7 +49,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8qm_ddr4_val_defconfig b/configs/imx8qm_ddr4_val_defconfig index 3ad81fc695..6e433b77d4 100644 --- a/configs/imx8qm_ddr4_val_defconfig +++ b/configs/imx8qm_ddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_lpddr4_val_defconfig b/configs/imx8qm_lpddr4_val_defconfig index ff7855d1a0..eba7ee5769 100644 --- a/configs/imx8qm_lpddr4_val_defconfig +++ b/configs/imx8qm_lpddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_lpddr4_val_fspi_defconfig b/configs/imx8qm_lpddr4_val_fspi_defconfig index 4da05191c1..b77c3b8c2d 100644 --- a/configs/imx8qm_lpddr4_val_fspi_defconfig +++ b/configs/imx8qm_lpddr4_val_fspi_defconfig @@ -53,7 +53,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_android_defconfig b/configs/imx8qm_mek_android_defconfig index 4ae8b05fcf..9cb61da220 100644 --- a/configs/imx8qm_mek_android_defconfig +++ b/configs/imx8qm_mek_android_defconfig @@ -206,3 +206,4 @@ CONFIG_PSCI_BOARD_REBOOT=y CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_dual_defconfig b/configs/imx8qm_mek_android_dual_defconfig index 7e465d0e03..6637225097 100644 --- a/configs/imx8qm_mek_android_dual_defconfig +++ b/configs/imx8qm_mek_android_dual_defconfig @@ -207,3 +207,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_hdmi_defconfig b/configs/imx8qm_mek_android_hdmi_defconfig index 0551b0826c..b7fb8cd751 100644 --- a/configs/imx8qm_mek_android_hdmi_defconfig +++ b/configs/imx8qm_mek_android_hdmi_defconfig @@ -208,3 +208,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_defconfig b/configs/imx8qm_mek_android_trusty_defconfig index ea93c9ce76..c40d236c07 100644 --- a/configs/imx8qm_mek_android_trusty_defconfig +++ b/configs/imx8qm_mek_android_trusty_defconfig @@ -213,3 +213,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_SHA256=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_dual_defconfig b/configs/imx8qm_mek_android_trusty_dual_defconfig index 7a8a7a3c1c..97d1f554b5 100644 --- a/configs/imx8qm_mek_android_trusty_dual_defconfig +++ b/configs/imx8qm_mek_android_trusty_dual_defconfig @@ -214,3 +214,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_SHA256=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig index f46457629a..0b2ce5f1f2 100644 --- a/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig +++ b/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig @@ -213,5 +213,7 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_SHA256=y +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_uuu_defconfig b/configs/imx8qm_mek_android_uuu_defconfig index 6a558b16aa..9239ef02f9 100644 --- a/configs/imx8qm_mek_android_uuu_defconfig +++ b/configs/imx8qm_mek_android_uuu_defconfig @@ -200,3 +200,4 @@ CONFIG_CMD_BMP=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto2_trusty_defconfig b/configs/imx8qm_mek_androidauto2_trusty_defconfig index 0cd969bb52..d11d032f81 100644 --- a/configs/imx8qm_mek_androidauto2_trusty_defconfig +++ b/configs/imx8qm_mek_androidauto2_trusty_defconfig @@ -211,3 +211,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig index de51e6e666..36251bdc10 100644 --- a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig +++ b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto_trusty_defconfig b/configs/imx8qm_mek_androidauto_trusty_defconfig index 9fcbc53e44..c557926ec4 100644 --- a/configs/imx8qm_mek_androidauto_trusty_defconfig +++ b/configs/imx8qm_mek_androidauto_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig index 2010ba1aa2..e91ddffbaf 100644 --- a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig +++ b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_cockpit_a53_defconfig b/configs/imx8qm_mek_cockpit_a53_defconfig index a7d7fd4d1e..b4d1f531ac 100644 --- a/configs/imx8qm_mek_cockpit_a53_defconfig +++ b/configs/imx8qm_mek_cockpit_a53_defconfig @@ -39,7 +39,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 29e9d796a6..d575904063 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig index 5284194138..0a8502d7b1 100644 --- a/configs/imx8qm_mek_fspi_defconfig +++ b/configs/imx8qm_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_trusty_xen_defconfig b/configs/imx8qm_mek_trusty_xen_defconfig index 0cd969bb52..cacd625916 100644 --- a/configs/imx8qm_mek_trusty_xen_defconfig +++ b/configs/imx8qm_mek_trusty_xen_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_17x17_val_defconfig b/configs/imx8qxp_17x17_val_defconfig index 181a6696eb..a75ab18161 100644 --- a/configs/imx8qxp_17x17_val_defconfig +++ b/configs/imx8qxp_17x17_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_ddr3_val_defconfig b/configs/imx8qxp_ddr3_val_defconfig index d2cc47f630..acaf40ddd0 100644 --- a/configs/imx8qxp_ddr3_val_defconfig +++ b/configs/imx8qxp_ddr3_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_defconfig b/configs/imx8qxp_lpddr4_val_defconfig index fcc6f7a275..186e467f94 100644 --- a/configs/imx8qxp_lpddr4_val_defconfig +++ b/configs/imx8qxp_lpddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_fspi_defconfig b/configs/imx8qxp_lpddr4_val_fspi_defconfig index aba96c898b..b900b36e0e 100644 --- a/configs/imx8qxp_lpddr4_val_fspi_defconfig +++ b/configs/imx8qxp_lpddr4_val_fspi_defconfig @@ -53,7 +53,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_nand_defconfig b/configs/imx8qxp_lpddr4_val_nand_defconfig index 7e3c606619..0cee3d8613 100644 --- a/configs/imx8qxp_lpddr4_val_nand_defconfig +++ b/configs/imx8qxp_lpddr4_val_nand_defconfig @@ -44,7 +44,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_mek_android_defconfig b/configs/imx8qxp_mek_android_defconfig index ef8f3fffb9..033daa7ad7 100644 --- a/configs/imx8qxp_mek_android_defconfig +++ b/configs/imx8qxp_mek_android_defconfig @@ -204,3 +204,4 @@ CONFIG_PSCI_BOARD_REBOOT=y CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_dual_defconfig b/configs/imx8qxp_mek_android_dual_defconfig index 119c94f049..f904654d3d 100644 --- a/configs/imx8qxp_mek_android_dual_defconfig +++ b/configs/imx8qxp_mek_android_dual_defconfig @@ -205,3 +205,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_trusty_dual_defconfig b/configs/imx8qxp_mek_android_trusty_dual_defconfig index 6363bc47a5..91718b0707 100644 --- a/configs/imx8qxp_mek_android_trusty_dual_defconfig +++ b/configs/imx8qxp_mek_android_trusty_dual_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig index 4fc4dba90b..9de24b5d85 100644 --- a/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig +++ b/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig @@ -211,5 +211,7 @@ CONFIG_ATTESTATION_ID_DEVICE="mek_8q" CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_uuu_defconfig b/configs/imx8qxp_mek_android_uuu_defconfig index 80ff2f8cec..45ee29db70 100644 --- a/configs/imx8qxp_mek_android_uuu_defconfig +++ b/configs/imx8qxp_mek_android_uuu_defconfig @@ -198,3 +198,4 @@ CONFIG_CMD_BMP=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto2_trusty_defconfig b/configs/imx8qxp_mek_androidauto2_trusty_defconfig index 1a9ecc8849..d932149a87 100644 --- a/configs/imx8qxp_mek_androidauto2_trusty_defconfig +++ b/configs/imx8qxp_mek_androidauto2_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto_trusty_defconfig b/configs/imx8qxp_mek_androidauto_trusty_defconfig index bae4378391..e5912f8585 100644 --- a/configs/imx8qxp_mek_androidauto_trusty_defconfig +++ b/configs/imx8qxp_mek_androidauto_trusty_defconfig @@ -209,3 +209,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig index 10989c26c5..a4b7c9a747 100644 --- a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig +++ b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig @@ -211,3 +211,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index eda9d2cc00..0e9b0b1890 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig index 56e3334828..7fa22d10ef 100644 --- a/configs/imx8qxp_mek_fspi_defconfig +++ b/configs/imx8qxp_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig index 80a669861e..23ff269937 100644 --- a/configs/imx8ulp_9x9_evk_android_defconfig +++ b/configs/imx8ulp_9x9_evk_android_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -148,3 +148,6 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_android_trusty_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig index 509d55c7bd..d929c04e91 100644 --- a/configs/imx8ulp_9x9_evk_android_trusty_defconfig +++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -154,3 +154,7 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" +CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_android_uuu_defconfig b/configs/imx8ulp_9x9_evk_android_uuu_defconfig index bd6d6dc5ef..3308c0b76a 100644 --- a/configs/imx8ulp_9x9_evk_android_uuu_defconfig +++ b/configs/imx8ulp_9x9_evk_android_uuu_defconfig @@ -137,9 +137,11 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_defconfig b/configs/imx8ulp_9x9_evk_defconfig index 3bb9926470..f1f5a3cf24 100644 --- a/configs/imx8ulp_9x9_evk_defconfig +++ b/configs/imx8ulp_9x9_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y @@ -70,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y @@ -137,4 +139,4 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y diff --git a/configs/imx8ulp_9x9_evk_i3c_defconfig b/configs/imx8ulp_9x9_evk_i3c_defconfig index d9a01b77e0..5011a6f812 100644 --- a/configs/imx8ulp_9x9_evk_i3c_defconfig +++ b/configs/imx8ulp_9x9_evk_i3c_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y @@ -71,6 +72,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y @@ -137,4 +139,4 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig index 2c5292db68..d5b8b93006 100644 --- a/configs/imx8ulp_evk_android_defconfig +++ b/configs/imx8ulp_evk_android_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -148,3 +148,6 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig index 38d8777334..a2ab29cab8 100644 --- a/configs/imx8ulp_evk_android_dual_defconfig +++ b/configs/imx8ulp_evk_android_dual_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -149,3 +149,6 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig index ed4044dc59..9e56ac6b48 100644 --- a/configs/imx8ulp_evk_android_trusty_defconfig +++ b/configs/imx8ulp_evk_android_trusty_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -154,3 +154,6 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig index 0d5f665cff..8be797977a 100644 --- a/configs/imx8ulp_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -155,3 +155,6 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig index accc888097..a92d3e6b11 100644 --- a/configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig +++ b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig @@ -136,7 +136,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_LZ4=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y @@ -154,5 +154,8 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" +CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_uuu_defconfig b/configs/imx8ulp_evk_android_uuu_defconfig index 03bde348ec..7078836de1 100644 --- a/configs/imx8ulp_evk_android_uuu_defconfig +++ b/configs/imx8ulp_evk_android_uuu_defconfig @@ -137,9 +137,11 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index 9834089f94..b5c76f8129 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y @@ -70,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y @@ -137,4 +139,7 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y diff --git a/configs/imx8ulp_evk_i3c_defconfig b/configs/imx8ulp_evk_i3c_defconfig index 74ee8e8462..2f70101317 100644 --- a/configs/imx8ulp_evk_i3c_defconfig +++ b/configs/imx8ulp_evk_i3c_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y @@ -72,6 +73,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y @@ -138,4 +140,4 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y diff --git a/configs/imx8ulp_evk_nd_defconfig b/configs/imx8ulp_evk_nd_defconfig index 53cfdf2355..bd454f3cb2 100644 --- a/configs/imx8ulp_evk_nd_defconfig +++ b/configs/imx8ulp_evk_nd_defconfig @@ -25,7 +25,6 @@ CONFIG_REMAKE_ELF=y CONFIG_SYS_LOAD_ADDR=0x80400000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb" CONFIG_BOARD_EARLY_INIT_F=y @@ -45,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y @@ -71,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y @@ -138,5 +139,5 @@ CONFIG_SCMI_POWER_DOMAIN=y CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y -CONFIG_IMX_PMC_TEMPERATURE=y +CONFIG_SCMI_THERMAL=y CONFIG_IMX8ULP_ND_MODE=y diff --git a/configs/imx8ulp_watch_android_defconfig b/configs/imx8ulp_watch_android_defconfig new file mode 100644 index 0000000000..8ae1851dc1 --- /dev/null +++ b/configs/imx8ulp_watch_android_defconfig @@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x1002000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-watch" +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_TARGET_IMX8ULP_WATCH=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8ulp-watch.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_DCNANO=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_VIDEO_LOGO=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LCD_USMP_RM67162=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0xC8 +CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_watch_android_dual_defconfig b/configs/imx8ulp_watch_android_dual_defconfig new file mode 100644 index 0000000000..833c1b657c --- /dev/null +++ b/configs/imx8ulp_watch_android_dual_defconfig @@ -0,0 +1,141 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x1002000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-watch" +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_TARGET_IMX8ULP_WATCH=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8ulp-watch.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_DCNANO=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_VIDEO_LOGO=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LCD_USMP_RM67162=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0xC8 +CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_DUAL_BOOTLOADER=y +CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_watch_android_trusty_dual_defconfig b/configs/imx8ulp_watch_android_trusty_dual_defconfig new file mode 100644 index 0000000000..ab439b3943 --- /dev/null +++ b/configs/imx8ulp_watch_android_trusty_dual_defconfig @@ -0,0 +1,146 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x1002000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-watch" +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_TARGET_IMX8ULP_WATCH=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8ulp-watch.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_DCNANO=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_VIDEO_LOGO=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LCD_USMP_RM67162=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0xC8 +CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_IMX_TRUSTY_OS=y +CONFIG_ATTESTATION_ID_BRAND="Android" +CONFIG_ATTESTATION_ID_DEVICE="watch_8ulp" +CONFIG_ATTESTATION_ID_PRODUCT="watch_8ulp" +CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" +CONFIG_ATTESTATION_ID_MODEL="WATCH_8ULP" +CONFIG_DUAL_BOOTLOADER=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_watch_android_uuu_defconfig b/configs/imx8ulp_watch_android_uuu_defconfig new file mode 100644 index 0000000000..5d5799855f --- /dev/null +++ b/configs/imx8ulp_watch_android_uuu_defconfig @@ -0,0 +1,134 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x1002000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-watch" +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_TARGET_IMX8ULP_WATCH=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx8ulp-watch.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_ULP_WATCHDOG=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_DCNANO=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_VIDEO_LOGO=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LCD_USMP_RM67162=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig new file mode 100644 index 0000000000..4bf4aac854 --- /dev/null +++ b/configs/imx93_11x11_evk_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ADP5585_GPIO=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y +CONFIG_PHY=y +CONFIG_PHY_IMX93_MIPI_DPHY=y +CONFIG_MIPI_DPHY_HELPERS=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_DW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/imx93_11x11_evk_inline_ecc_defconfig b/configs/imx93_11x11_evk_inline_ecc_defconfig new file mode 100644 index 0000000000..8fc62d1988 --- /dev/null +++ b/configs/imx93_11x11_evk_inline_ecc_defconfig @@ -0,0 +1,187 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_IMX9_DRAM_INLINE_ECC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ADP5585_GPIO=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y +CONFIG_PHY=y +CONFIG_PHY_IMX93_MIPI_DPHY=y +CONFIG_MIPI_DPHY_HELPERS=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_DW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig new file mode 100644 index 0000000000..aa1c4984a0 --- /dev/null +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_IMX9_LOW_DRIVE_MODE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ADP5585_GPIO=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y +CONFIG_PHY=y +CONFIG_PHY_IMX93_MIPI_DPHY=y +CONFIG_MIPI_DPHY_HELPERS=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_DW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y + +CONFIG_OF_BOARD_FIXUP=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig new file mode 100644 index 0000000000..c928b5aa82 --- /dev/null +++ b/configs/imx93_9x9_qsb_defconfig @@ -0,0 +1,181 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb-ontat-wvga-panel" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_9X9_QSB=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y + +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SIMPLE_PANEL=y +CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig new file mode 100644 index 0000000000..593c6c17c8 --- /dev/null +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -0,0 +1,182 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb-ontat-wvga-panel" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_9X9_QSB=y +CONFIG_IMX9_DRAM_INLINE_ECC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y + +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SIMPLE_PANEL=y +CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index e7c277d6c6..5609022a20 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 130397fc07..0387716a02 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FSL_LS_PPA=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index a86138f179..af13a80e30 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -14,6 +14,7 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 12af76d3b7..7e68e25c22 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -18,6 +18,7 @@ CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 61e348291e..0f58b8ce82 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 1ea5f9a808..4e3f436db0 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 6ff5614cb5..1cb37cf99b 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index fc61b00e85..c4fd419326 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -15,11 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" @@ -83,6 +85,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_OF_SYSTEM_SETUP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index d469fa1462..347302bc9c 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_eimnor_defconfig b/configs/mx6dlsabreauto_eimnor_defconfig index 2c9180c86d..d775d189a1 100644 --- a/configs/mx6dlsabreauto_eimnor_defconfig +++ b/configs/mx6dlsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_nand_defconfig b/configs/mx6dlsabreauto_nand_defconfig index 7990e0a32b..ef5cbcafe1 100644 --- a/configs/mx6dlsabreauto_nand_defconfig +++ b/configs/mx6dlsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_optee_defconfig b/configs/mx6dlsabreauto_optee_defconfig index a50f156465..65a4497c98 100644 --- a/configs/mx6dlsabreauto_optee_defconfig +++ b/configs/mx6dlsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_plugin_defconfig b/configs/mx6dlsabreauto_plugin_defconfig index 78b0d346cf..47b1a6402f 100644 --- a/configs/mx6dlsabreauto_plugin_defconfig +++ b/configs/mx6dlsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_spinor_defconfig b/configs/mx6dlsabreauto_spinor_defconfig index 162a98dde0..3f5280f898 100644 --- a/configs/mx6dlsabreauto_spinor_defconfig +++ b/configs/mx6dlsabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index b23a524fb2..f91b23218c 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_epdc_defconfig b/configs/mx6dlsabresd_epdc_defconfig index 79d5742e1e..853e5c5ef5 100644 --- a/configs/mx6dlsabresd_epdc_defconfig +++ b/configs/mx6dlsabresd_epdc_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_optee_defconfig b/configs/mx6dlsabresd_optee_defconfig index aca36d95df..4cc87f3161 100644 --- a/configs/mx6dlsabresd_optee_defconfig +++ b/configs/mx6dlsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_plugin_defconfig b/configs/mx6dlsabresd_plugin_defconfig index 417607a291..6f35ff8b56 100644 --- a/configs/mx6dlsabresd_plugin_defconfig +++ b/configs/mx6dlsabresd_plugin_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig index 553bc99c71..bd83071583 100644 --- a/configs/mx6qpsabreauto_defconfig +++ b/configs/mx6qpsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_eimnor_defconfig b/configs/mx6qpsabreauto_eimnor_defconfig index 8bd43ffb72..0dceadbcf1 100644 --- a/configs/mx6qpsabreauto_eimnor_defconfig +++ b/configs/mx6qpsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_nand_defconfig b/configs/mx6qpsabreauto_nand_defconfig index 7eebfcab1e..be87a9b515 100644 --- a/configs/mx6qpsabreauto_nand_defconfig +++ b/configs/mx6qpsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_optee_defconfig b/configs/mx6qpsabreauto_optee_defconfig index a53cac34e8..6b618c4966 100644 --- a/configs/mx6qpsabreauto_optee_defconfig +++ b/configs/mx6qpsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_plugin_defconfig b/configs/mx6qpsabreauto_plugin_defconfig index 6075500b55..51e32a7f9f 100644 --- a/configs/mx6qpsabreauto_plugin_defconfig +++ b/configs/mx6qpsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_sata_defconfig b/configs/mx6qpsabreauto_sata_defconfig index 472eb10c8e..407981dd25 100644 --- a/configs/mx6qpsabreauto_sata_defconfig +++ b/configs/mx6qpsabreauto_sata_defconfig @@ -102,3 +102,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_spinor_defconfig b/configs/mx6qpsabreauto_spinor_defconfig index 229494f00e..b64d4f0eb5 100644 --- a/configs/mx6qpsabreauto_spinor_defconfig +++ b/configs/mx6qpsabreauto_spinor_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_defconfig b/configs/mx6qpsabresd_defconfig index ba36499910..eb386c720a 100644 --- a/configs/mx6qpsabresd_defconfig +++ b/configs/mx6qpsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_optee_defconfig b/configs/mx6qpsabresd_optee_defconfig index 77978c9561..4ba3890b95 100644 --- a/configs/mx6qpsabresd_optee_defconfig +++ b/configs/mx6qpsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_sata_defconfig b/configs/mx6qpsabresd_sata_defconfig index 19e72e2b17..f9a057339f 100644 --- a/configs/mx6qpsabresd_sata_defconfig +++ b/configs/mx6qpsabresd_sata_defconfig @@ -111,3 +111,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index c2e92a947e..978fe14826 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_eimnor_defconfig b/configs/mx6qsabreauto_eimnor_defconfig index 8205860865..38b3f974c1 100644 --- a/configs/mx6qsabreauto_eimnor_defconfig +++ b/configs/mx6qsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_nand_defconfig b/configs/mx6qsabreauto_nand_defconfig index d1479557f0..3281cab0eb 100644 --- a/configs/mx6qsabreauto_nand_defconfig +++ b/configs/mx6qsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_optee_defconfig b/configs/mx6qsabreauto_optee_defconfig index 7ba7d641d7..f594feb87a 100644 --- a/configs/mx6qsabreauto_optee_defconfig +++ b/configs/mx6qsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_plugin_defconfig b/configs/mx6qsabreauto_plugin_defconfig index 5d90ecde91..29c0d38bbc 100644 --- a/configs/mx6qsabreauto_plugin_defconfig +++ b/configs/mx6qsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_sata_defconfig b/configs/mx6qsabreauto_sata_defconfig index 9b71e45b16..e132390287 100644 --- a/configs/mx6qsabreauto_sata_defconfig +++ b/configs/mx6qsabreauto_sata_defconfig @@ -102,3 +102,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_spinor_defconfig b/configs/mx6qsabreauto_spinor_defconfig index 5c51939b4f..3ac3d004ab 100644 --- a/configs/mx6qsabreauto_spinor_defconfig +++ b/configs/mx6qsabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 6817c6f88a..c2a8bbe1e9 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -90,3 +90,5 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 986fab886d..bef2e54c6b 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_optee_defconfig b/configs/mx6qsabresd_optee_defconfig index 93187e1f41..33e036803c 100644 --- a/configs/mx6qsabresd_optee_defconfig +++ b/configs/mx6qsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_plugin_defconfig b/configs/mx6qsabresd_plugin_defconfig index f2e85177b9..cb68cabdc1 100644 --- a/configs/mx6qsabresd_plugin_defconfig +++ b/configs/mx6qsabresd_plugin_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_sata_defconfig b/configs/mx6qsabresd_sata_defconfig index 11c7c1d8da..b0c166c1ed 100644 --- a/configs/mx6qsabresd_sata_defconfig +++ b/configs/mx6qsabresd_sata_defconfig @@ -111,3 +111,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index fe3ec76748..81251995bb 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -117,3 +117,5 @@ CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index d2f5f8df15..f1a7ae6f18 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -122,3 +122,5 @@ CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 2cc16e2110..e0dbd22866 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -90,3 +90,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_epdc_defconfig b/configs/mx6slevk_epdc_defconfig index 638afd5208..5f7ee6188f 100644 --- a/configs/mx6slevk_epdc_defconfig +++ b/configs/mx6slevk_epdc_defconfig @@ -95,3 +95,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_optee_defconfig b/configs/mx6slevk_optee_defconfig index 779b1a4771..422ccb9152 100644 --- a/configs/mx6slevk_optee_defconfig +++ b/configs/mx6slevk_optee_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_plugin_defconfig b/configs/mx6slevk_plugin_defconfig index 642543e142..df1b60a7d0 100644 --- a/configs/mx6slevk_plugin_defconfig +++ b/configs/mx6slevk_plugin_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 3f8a2ddd3d..0c432a46e5 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 09d71ae905..9ae103d3a3 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -82,3 +82,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr2_val_defconfig b/configs/mx6sll_lpddr2_val_defconfig index 2b1f0434b7..4f01034a44 100644 --- a/configs/mx6sll_lpddr2_val_defconfig +++ b/configs/mx6sll_lpddr2_val_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_defconfig b/configs/mx6sll_lpddr3_val_defconfig index 5cad2d7775..4b4fa344c6 100644 --- a/configs/mx6sll_lpddr3_val_defconfig +++ b/configs/mx6sll_lpddr3_val_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_epdc_defconfig b/configs/mx6sll_lpddr3_val_epdc_defconfig index 497480d9e9..1921e086bb 100644 --- a/configs/mx6sll_lpddr3_val_epdc_defconfig +++ b/configs/mx6sll_lpddr3_val_epdc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_plugin_defconfig b/configs/mx6sll_lpddr3_val_plugin_defconfig index a88e1e403e..d016b013be 100644 --- a/configs/mx6sll_lpddr3_val_plugin_defconfig +++ b/configs/mx6sll_lpddr3_val_plugin_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_spinor_defconfig b/configs/mx6sll_lpddr3_val_spinor_defconfig index 4590d781eb..8087eaeec8 100644 --- a/configs/mx6sll_lpddr3_val_spinor_defconfig +++ b/configs/mx6sll_lpddr3_val_spinor_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 56e5755223..fab5c0d822 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig index 87ace8ad3e..2d66343059 100644 --- a/configs/mx6sllevk_epdc_defconfig +++ b/configs/mx6sllevk_epdc_defconfig @@ -87,3 +87,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_optee_defconfig b/configs/mx6sllevk_optee_defconfig index 7978739bf3..02b18d66de 100644 --- a/configs/mx6sllevk_optee_defconfig +++ b/configs/mx6sllevk_optee_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 602cb48baa..2f7c12f820 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_defconfig b/configs/mx6solosabreauto_defconfig index bdf5103638..d3192e32dc 100644 --- a/configs/mx6solosabreauto_defconfig +++ b/configs/mx6solosabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_eimnor_defconfig b/configs/mx6solosabreauto_eimnor_defconfig index dc764a2f1a..e7ac350237 100644 --- a/configs/mx6solosabreauto_eimnor_defconfig +++ b/configs/mx6solosabreauto_eimnor_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_nand_defconfig b/configs/mx6solosabreauto_nand_defconfig index 8f6816c0f7..86add3582c 100644 --- a/configs/mx6solosabreauto_nand_defconfig +++ b/configs/mx6solosabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_optee_defconfig b/configs/mx6solosabreauto_optee_defconfig index d18fc606d8..b4cce2f6bb 100644 --- a/configs/mx6solosabreauto_optee_defconfig +++ b/configs/mx6solosabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_spinor_defconfig b/configs/mx6solosabreauto_spinor_defconfig index 4de754b0b6..5382813bc2 100644 --- a/configs/mx6solosabreauto_spinor_defconfig +++ b/configs/mx6solosabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig index 9b5843a13d..f41a900cfb 100644 --- a/configs/mx6solosabresd_defconfig +++ b/configs/mx6solosabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabresd_optee_defconfig b/configs/mx6solosabresd_optee_defconfig index 731e6f28d0..2face9926d 100644 --- a/configs/mx6solosabresd_optee_defconfig +++ b/configs/mx6solosabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_defconfig b/configs/mx6sx_14x14_lpddr2_val_defconfig index bea729b6d9..687c52b152 100644 --- a/configs/mx6sx_14x14_lpddr2_val_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig index 04ea9c8bd2..06b3ccae00 100644 --- a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig index f2a56d271e..fd0e3e1755 100644 --- a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_defconfig b/configs/mx6sx_17x17_val_defconfig index 8427cc704d..9bb0187ecb 100644 --- a/configs/mx6sx_17x17_val_defconfig +++ b/configs/mx6sx_17x17_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_eimnor_defconfig b/configs/mx6sx_17x17_val_eimnor_defconfig index 092e73a7c2..4ae90d9f8a 100644 --- a/configs/mx6sx_17x17_val_eimnor_defconfig +++ b/configs/mx6sx_17x17_val_eimnor_defconfig @@ -72,3 +72,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_nand_defconfig b/configs/mx6sx_17x17_val_nand_defconfig index 1478027ece..16f0185251 100644 --- a/configs/mx6sx_17x17_val_nand_defconfig +++ b/configs/mx6sx_17x17_val_nand_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_plugin_defconfig b/configs/mx6sx_17x17_val_plugin_defconfig index 454aec8da6..7c95d28299 100644 --- a/configs/mx6sx_17x17_val_plugin_defconfig +++ b/configs/mx6sx_17x17_val_plugin_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_qspi2_defconfig b/configs/mx6sx_17x17_val_qspi2_defconfig index d614d181b4..6b32679f73 100644 --- a/configs/mx6sx_17x17_val_qspi2_defconfig +++ b/configs/mx6sx_17x17_val_qspi2_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_spinor_defconfig b/configs/mx6sx_17x17_val_spinor_defconfig index 3e4ab08a61..e579d02481 100644 --- a/configs/mx6sx_17x17_val_spinor_defconfig +++ b/configs/mx6sx_17x17_val_spinor_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17wp_val_defconfig b/configs/mx6sx_17x17wp_val_defconfig index c4f9ff3fa8..d79ef92e72 100644 --- a/configs/mx6sx_17x17wp_val_defconfig +++ b/configs/mx6sx_17x17wp_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_defconfig b/configs/mx6sx_19x19_ddr3_val_defconfig index 365c4266e9..a371c401c8 100644 --- a/configs/mx6sx_19x19_ddr3_val_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig index ea6389c6f6..9b85e58043 100644 --- a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig @@ -71,3 +71,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_nand_defconfig b/configs/mx6sx_19x19_ddr3_val_nand_defconfig index 57b57efbae..2f74fb0901 100644 --- a/configs/mx6sx_19x19_ddr3_val_nand_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_nand_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig index 8568c358e6..ed21966a28 100644 --- a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig index cccdbc8d13..fa497fc511 100644 --- a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig index b3439bc3a7..32bbe2a499 100644 --- a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_defconfig b/configs/mx6sx_19x19_lpddr2_val_defconfig index 79ae5deebd..d4de70cc1a 100644 --- a/configs/mx6sx_19x19_lpddr2_val_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig index 0e16c6ae68..2a353e731e 100644 --- a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig index a515ad6673..491e07c7f7 100644 --- a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 3cd1254f8f..89b3548977 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_nand_defconfig b/configs/mx6sxsabreauto_nand_defconfig index 0dc30d8475..a32d0d312b 100644 --- a/configs/mx6sxsabreauto_nand_defconfig +++ b/configs/mx6sxsabreauto_nand_defconfig @@ -117,3 +117,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_optee_defconfig b/configs/mx6sxsabreauto_optee_defconfig index b246eff6d9..add640ec30 100644 --- a/configs/mx6sxsabreauto_optee_defconfig +++ b/configs/mx6sxsabreauto_optee_defconfig @@ -113,3 +113,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_plugin_defconfig b/configs/mx6sxsabreauto_plugin_defconfig index 8c4a158a7d..7e81e7b3cc 100644 --- a/configs/mx6sxsabreauto_plugin_defconfig +++ b/configs/mx6sxsabreauto_plugin_defconfig @@ -113,3 +113,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_qspi1_defconfig b/configs/mx6sxsabreauto_qspi1_defconfig index 0878827593..9b0b725dbd 100644 --- a/configs/mx6sxsabreauto_qspi1_defconfig +++ b/configs/mx6sxsabreauto_qspi1_defconfig @@ -117,3 +117,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 7d2a7995e0..ccd084a4ff 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -111,3 +111,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig index 5b41f86a30..3fa8f151be 100644 --- a/configs/mx6sxsabresd_emmc_defconfig +++ b/configs/mx6sxsabresd_emmc_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig index fbcb906692..04b8e656b1 100644 --- a/configs/mx6sxsabresd_m4fastup_defconfig +++ b/configs/mx6sxsabresd_m4fastup_defconfig @@ -87,3 +87,5 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_optee_defconfig b/configs/mx6sxsabresd_optee_defconfig index 572ab0cebb..8801dbd7b2 100644 --- a/configs/mx6sxsabresd_optee_defconfig +++ b/configs/mx6sxsabresd_optee_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig index c7ae5c7e4c..1f6a5f63d0 100644 --- a/configs/mx6sxsabresd_plugin_defconfig +++ b/configs/mx6sxsabresd_plugin_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig index a5e1fcedb4..5fdab1f758 100644 --- a/configs/mx6sxsabresd_qspi2_defconfig +++ b/configs/mx6sxsabresd_qspi2_defconfig @@ -116,3 +116,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_defconfig b/configs/mx6ul_14x14_ddr3_val_defconfig index ad0cc2698e..011dd23469 100644 --- a/configs/mx6ul_14x14_ddr3_val_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_defconfig @@ -75,3 +75,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig index a75a381f8a..7ffe1d36d8 100644 --- a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig @@ -64,3 +64,5 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_MMC=n +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig index 0d68ad1298..e6d2980a47 100644 --- a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_nand_defconfig b/configs/mx6ul_14x14_ddr3_val_nand_defconfig index 8f1483cd05..d727d78fc3 100644 --- a/configs/mx6ul_14x14_ddr3_val_nand_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_nand_defconfig @@ -75,3 +75,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig index fdd8315a67..ad9c14f8d3 100644 --- a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig @@ -76,3 +76,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig index 15c0e6e3b1..b843458073 100644 --- a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig @@ -77,3 +77,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig index a82bed66e2..4788727d34 100644 --- a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig @@ -78,3 +78,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1aa455f120..687d7362fe 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -101,3 +101,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_emmc_defconfig b/configs/mx6ul_14x14_evk_emmc_defconfig index 19baa475e0..ce6b7afb70 100644 --- a/configs/mx6ul_14x14_evk_emmc_defconfig +++ b/configs/mx6ul_14x14_evk_emmc_defconfig @@ -101,3 +101,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_nand_defconfig b/configs/mx6ul_14x14_evk_nand_defconfig index 7b99e89be6..61d49d2f51 100644 --- a/configs/mx6ul_14x14_evk_nand_defconfig +++ b/configs/mx6ul_14x14_evk_nand_defconfig @@ -105,3 +105,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_optee_defconfig b/configs/mx6ul_14x14_evk_optee_defconfig index 885f25e7b2..d5621b59a2 100644 --- a/configs/mx6ul_14x14_evk_optee_defconfig +++ b/configs/mx6ul_14x14_evk_optee_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_plugin_defconfig b/configs/mx6ul_14x14_evk_plugin_defconfig index 6555f224b3..97b032d000 100644 --- a/configs/mx6ul_14x14_evk_plugin_defconfig +++ b/configs/mx6ul_14x14_evk_plugin_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_qspi1_defconfig b/configs/mx6ul_14x14_evk_qspi1_defconfig index 608bd156f3..260183a57c 100644 --- a/configs/mx6ul_14x14_evk_qspi1_defconfig +++ b/configs/mx6ul_14x14_evk_qspi1_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_spl_defconfig b/configs/mx6ul_14x14_evk_spl_defconfig index dfc1bc2fd4..b21aa2b976 100644 --- a/configs/mx6ul_14x14_evk_spl_defconfig +++ b/configs/mx6ul_14x14_evk_spl_defconfig @@ -100,3 +100,5 @@ CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_lpddr2_val_defconfig b/configs/mx6ul_14x14_lpddr2_val_defconfig index 6a80b0e6d4..740ea1b6ee 100644 --- a/configs/mx6ul_14x14_lpddr2_val_defconfig +++ b/configs/mx6ul_14x14_lpddr2_val_defconfig @@ -66,3 +66,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig index 22b88418ca..41dc2ad821 100644 --- a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig +++ b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 7afd445694..6d2b998e8f 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_optee_defconfig b/configs/mx6ul_9x9_evk_optee_defconfig index bfb3cb6c75..4d71c0e644 100644 --- a/configs/mx6ul_9x9_evk_optee_defconfig +++ b/configs/mx6ul_9x9_evk_optee_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_plugin_defconfig b/configs/mx6ul_9x9_evk_plugin_defconfig index 3ca556a36f..7c2dc45f37 100644 --- a/configs/mx6ul_9x9_evk_plugin_defconfig +++ b/configs/mx6ul_9x9_evk_plugin_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_qspi1_defconfig b/configs/mx6ul_9x9_evk_qspi1_defconfig index 55f5efb465..b5abc8c051 100644 --- a/configs/mx6ul_9x9_evk_qspi1_defconfig +++ b/configs/mx6ul_9x9_evk_qspi1_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_spl_defconfig b/configs/mx6ul_9x9_evk_spl_defconfig index a121e96603..66ef7428ba 100644 --- a/configs/mx6ul_9x9_evk_spl_defconfig +++ b/configs/mx6ul_9x9_evk_spl_defconfig @@ -90,3 +90,5 @@ CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_defconfig b/configs/mx6ull_14x14_ddr3_val_defconfig index 18879920ac..d545f2771d 100644 --- a/configs/mx6ull_14x14_ddr3_val_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig index c7f75c035a..568b55908c 100644 --- a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig index ac06caeffe..1be63ac379 100644 --- a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_nand_defconfig b/configs/mx6ull_14x14_ddr3_val_nand_defconfig index 2ccdd61e4a..fddaaeb267 100644 --- a/configs/mx6ull_14x14_ddr3_val_nand_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_nand_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig index 77a643e560..05913c6a3c 100644 --- a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig @@ -76,3 +76,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig index e04d76179a..f41f5c1f13 100644 --- a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig index 36eb157659..6dafce4fd9 100644 --- a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig index 5b266463cf..782ea09914 100644 --- a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig @@ -76,3 +76,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index cdcd496edd..06193017f4 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -99,3 +99,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig index d94085e13b..4b81d0ea72 100644 --- a/configs/mx6ull_14x14_evk_emmc_defconfig +++ b/configs/mx6ull_14x14_evk_emmc_defconfig @@ -99,3 +99,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig index 16900e04f0..efca82d619 100644 --- a/configs/mx6ull_14x14_evk_nand_defconfig +++ b/configs/mx6ull_14x14_evk_nand_defconfig @@ -106,3 +106,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig index 2bb3d44fa8..51e1bd8fde 100644 --- a/configs/mx6ull_14x14_evk_optee_defconfig +++ b/configs/mx6ull_14x14_evk_optee_defconfig @@ -100,3 +100,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index baab9c2ee8..ffdcc93819 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -100,3 +100,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig index f1fe8b4000..69db8b7ec7 100644 --- a/configs/mx6ull_14x14_evk_qspi1_defconfig +++ b/configs/mx6ull_14x14_evk_qspi1_defconfig @@ -102,3 +102,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig index 66eacc55fa..e96c202f4d 100644 --- a/configs/mx6ull_9x9_evk_defconfig +++ b/configs/mx6ull_9x9_evk_defconfig @@ -103,3 +103,11 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y + +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig index 7eace52b5c..cd7a5505e1 100644 --- a/configs/mx6ull_9x9_evk_plugin_defconfig +++ b/configs/mx6ull_9x9_evk_plugin_defconfig @@ -104,3 +104,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig index f145b65e6c..4168573e03 100644 --- a/configs/mx6ull_9x9_evk_qspi1_defconfig +++ b/configs/mx6ull_9x9_evk_qspi1_defconfig @@ -106,3 +106,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_DM_RNG=y +CONFIG_CMD_RNG=y +CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 438af0a065..ee911af30a 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -87,4 +87,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y
\ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_emmc_defconfig b/configs/mx6ulz_14x14_evk_emmc_defconfig index 7595c54ee8..44881ee749 100644 --- a/configs/mx6ulz_14x14_evk_emmc_defconfig +++ b/configs/mx6ulz_14x14_evk_emmc_defconfig @@ -87,4 +87,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y
\ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_nand_defconfig b/configs/mx6ulz_14x14_evk_nand_defconfig index 6526b17200..44a69b350c 100644 --- a/configs/mx6ulz_14x14_evk_nand_defconfig +++ b/configs/mx6ulz_14x14_evk_nand_defconfig @@ -91,4 +91,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y
\ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_optee_defconfig b/configs/mx6ulz_14x14_evk_optee_defconfig index ebb71c0684..12a2973b7b 100644 --- a/configs/mx6ulz_14x14_evk_optee_defconfig +++ b/configs/mx6ulz_14x14_evk_optee_defconfig @@ -88,4 +88,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y
\ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_qspi1_defconfig b/configs/mx6ulz_14x14_evk_qspi1_defconfig index d6af77381f..a19528a293 100644 --- a/configs/mx6ulz_14x14_evk_qspi1_defconfig +++ b/configs/mx6ulz_14x14_evk_qspi1_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 7c157a23d0..1a0142795a 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -247,7 +247,6 @@ CONFIG_ERRNO_STR=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y CONFIG_UNIT_TEST=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ab0e2defee..de2526df09 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -318,7 +318,6 @@ CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 217b0647bb..bbcf435ac6 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_BOOTEFI_HELLO=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_NVEDIT_INFO=y CONFIG_CMD_NVEDIT_LOAD=y CONFIG_CMD_NVEDIT_SELECT=y @@ -210,3 +211,7 @@ CONFIG_HEXDUMP=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_DFU_SF=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index b9d01d8d9f..2e493daa88 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -2,10 +2,11 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y @@ -15,14 +16,11 @@ CONFIG_TARGET_VERDIN_IMX8MM=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_LOAD_ADDR=0x48200000 -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_IMX_BOOTAUX=y +CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y @@ -42,6 +40,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="Verdin iMX8MM # " # CONFIG_BOOTM_NETBSD is not set @@ -74,16 +75,12 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth0" CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 -CONFIG_SPL_CLK_COMPOSITE_CCF=y -CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -91,6 +88,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x42800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y @@ -113,6 +111,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -132,17 +132,17 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y -CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 389f23f86e..ae022ec399 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -1,11 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_SYS_I2C_MXC_I2C1=y @@ -19,13 +20,12 @@ CONFIG_TARGET_VERDIN_IMX8MP=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_SYS_LOAD_ADDR=0x48200000 -CONFIG_SYS_MEMTEST_START=0x40000000 -CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y @@ -38,6 +38,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y @@ -91,7 +92,13 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -99,7 +106,6 @@ CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -114,8 +120,8 @@ CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_FIXED=y -CONFIG_DM_MDIO=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_IMX=y @@ -143,13 +149,19 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_MX7 is not set CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index fe337c88bd..753a4e5e29 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -312,8 +312,8 @@ Run the following command .. code-block:: console $ mkeficapsule \ - --index 1 --instance 0 \ - [--fit <FIT image> | --raw <raw image>] \ + --index <index> --instance 0 \ + --guid <image GUID> \ <capsule_file_name> Performing the update @@ -333,8 +333,104 @@ won't be taken over across the reboot. If this is the case, you can skip this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS) set. +A few values need to be defined in the board file for performing the +capsule update. These values are defined in the board file by +initialisation of a structure which provides information needed for +capsule updates. The following structures have been defined for +containing the image related information + +.. code-block:: c + + struct efi_fw_image { + efi_guid_t image_type_id; + u16 *fw_name; + u8 image_index; + }; + + struct efi_capsule_update_info { + const char *dfu_string; + struct efi_fw_image *images; + }; + + +A string is defined which is to be used for populating the +dfu_alt_info variable. This string is used by the function +set_dfu_alt_info. Instead of taking the variable from the environment, +the capsule update feature requires that the variable be set through +the function, since that is more robust. Allowing the user to change +the location of the firmware updates is not a very secure +practice. Getting this information from the firmware itself is more +secure, assuming the firmware has been verified by a previous stage +boot loader. + +The firmware images structure defines the GUID values, image index +values and the name of the images that are to be updated through +the capsule update feature. These values are to be defined as part of +an array. These GUID values would be used by the Firmware Management +Protocol(FMP) to populate the image descriptor array and also +displayed as part of the ESRT table. The image index values defined in +the array should be one greater than the dfu alt number that +corresponds to the firmware image. So, if the dfu alt number for an +image is 2, the value of image index in the fw_images array for that +image should be 3. The dfu alt number can be obtained by running the +following command:: + + dfu list + +When using the FMP for FIT images, the image index value needs to be +set to 1. + Finally, the capsule update can be initiated by rebooting the board. +An example of setting the values in the struct efi_fw_image and +struct efi_capsule_update_info is shown below + +.. code-block:: c + + struct efi_fw_image fw_images[] = { + { + .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-UBOOT", + .image_index = 1, + }, + { + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-FIP", + .image_index = 2, + }, + { + .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-OPTEE", + .image_index = 3, + }, + }; + + struct efi_capsule_update_info update_info = { + .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;" + "fip.bin raw 180000 78000;" + "optee.bin raw 500000 100000", + .images = fw_images, + }; + +Platforms must declare a variable update_info of type struct +efi_capsule_update_info as shown in the example above. The platform +will also define a fw_images array which contains information of all +the firmware images that are to be updated through capsule update +mechanism. The dfu_string is the string that is to be set as +dfu_alt_info. In the example above, the image index to be set for +u-boot.bin binary is 0x1, for fip.bin is 0x2 and for optee.bin is 0x3. + +As an example, for generating the capsule for the optee.bin image, the +following command can be issued + +.. code-block:: bash + + $ ./tools/mkeficapsule \ + --index 0x3 --instance 0 \ + --guid c1b629f1-ce0e-4894-82bf-f0a38387e630 \ + optee.bin optee.capsule + + Enabling Capsule Authentication ******************************* diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt index d9218ab431..ca91f1232a 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -30,7 +30,7 @@ Verification index = 2 # Authenticate Start Address, Offset, Length and file Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ - 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ - 0x00910000 0x0F56C8 0x09139 "flash.bin", \ - 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ - 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" + 0x40200000 0x05CC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F76C8 0x09139 "flash.bin", \ + 0xFE000000 0x100804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14DA6C 0x06DCF "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt index be0b353084..55dcd1d6ce 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt @@ -44,6 +44,6 @@ # is a copy of the file used for the authentication command above Verification Index = 0 Mac Bytes = 16 - Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ - 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + Blocks = 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x115540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_fdt.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_fdt.txt new file mode 100644 index 0000000000..dd88843dee --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_fdt.txt @@ -0,0 +1,32 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target index = 2 + # Key to install + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x401fadc0 0x57c00 0x3020 "signed-flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt index 9a41c8bb40..b699b4dbf3 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt @@ -27,9 +27,9 @@ [Authenticate Data] Verification index = 2 Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin", \ - 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ - 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x115540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc.bin" [Install Secret Key] # Install the blob @@ -47,7 +47,7 @@ # is a copy of the file used for the authentication command above Verification Index = 0 Mac Bytes = 16 - Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ - 0x920000 0x113540 0xA160 "flash-spl-fit-enc-dummy.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin" + Blocks = 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ + 0x920000 0x115540 0xA160 "flash-spl-fit-enc-dummy.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc-dummy.bin" diff --git a/doc/imx/habv4/guides/mx8m_encrypted_boot.txt b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt index bb9b6b80f0..5a5f2bd835 100644 --- a/doc/imx/habv4/guides/mx8m_encrypted_boot.txt +++ b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt @@ -41,19 +41,25 @@ The diagram below illustrates an encrypted flash.bin image layout: Signed | ------- +-----------------------------+ | Data | Enc ^ | u-boot-spl.bin | | | Data | | + | | SPL - v v | DDR FW | | Image + | | | DDR FW | | Image + | | | + | | + v v | Hash of FIT FDT | | ------------------ +-----------------------------+ | | CSF - SPL + DDR FW | v +-----------------------------+ -------- | DEK Blob | +-----------------------------+ | Padding | - ------- +-----------------------------+ -------- - Signed ^ | FDT - FIT | ^ - Data | +-----------------------------+ | - v | IVT - FIT | | - ------- +-----------------------------+ | - | CSF - FIT | | + ------------------ +-----------------------------+ -------- + ^ Signed ^ | FDT - FIT | ^ + | Data | +-----------------------------+ | + Signed | v | IVT - FIT | | + Data | ------- +-----------------------------+ | +(optional) | CSF - FIT | | + | +-----------------------------+ | + v | IVT - FIT FDT (optional) | | + ------------------ +-----------------------------+ | + | CSF - FIT FDT (optional) | | ------------------ +-----------------------------+ | ^ | u-boot-nodtb.bin | | FIT | +-----------------------------+ | Image @@ -81,6 +87,7 @@ by following one of the methods below: CONFIG_CMD_DEKBLOB=y CONFIG_IMX_OPTEE_DEK_ENCAP=y CONFIG_CMD_PRIBLOB=y + CONFIG_IMX_SPL_FIT_FDT_SIGNATURE=y (Optional, for FIT FDT signature only) - Kconfig @@ -166,7 +173,9 @@ Command Sequence File (CSF): Second Loader IMAGE: sld_header_off 0x57c00 sld_csf_off 0x58c20 - sld hab block: 0x401fcdc0 0x57c00 0x1020 + sld hab block: 0x401fadc0 0x57c00 0x1020 + fit-fdt csf_off 0x5ac20 + fit-fdt hab block: 0x401fadc0 0x57c00 0x3020 - Additional HAB information is provided by running the following command: @@ -176,10 +185,10 @@ Command Sequence File (CSF): ./../scripts/pad_image.sh u-boot-nodtb.bin fsl-imx8mm-evk.dtb TEE_LOAD_ADDR=0xbe000000 ATF_LOAD_ADDR=0x00920000 VERSION=v1 \ ./print_fit_hab.sh 0x60000 fsl-imx8mm-evk.dtb - 0x40200000 0x5AC00 0xB0318 - 0x402B0318 0x10AF18 0x8628 - 0x920000 0x113540 0xA160 - 0xBE000000 0x11D6A0 0x48520 + 0x40200000 0x5CC00 0xB0318 + 0x402B0318 0x10CF18 0x8628 + 0x920000 0x115540 0xA160 + 0xBE000000 0x11F6A0 0x48520 1.6 Creating the CSF description file for SPL + DDR FW image ------------------------------------------------------------- @@ -332,7 +341,7 @@ file. [Authenticate Data] ... - Blocks = 0x401FCDC0 0x57C00 0x1020 "flash-spl-enc.bin" + Blocks = 0x401FADC0 0x57C00 0x1020 "flash-spl-enc.bin" - Add the Install Secret Key command to generate the dek_fit.bin file and install the blob. The Blob Address is a fixed address defined in imx-mkimage @@ -356,10 +365,10 @@ file. imx-mkimage output: - 0x40200000 0x5AC00 0xB0318 ──┬── Total length = 0xB0318 + 0x8628 = 0xB8940 - 0x402B0318 0x10AF18 0x8628 ──┘ - 0x920000 0x113540 0xA160 - 0xBE000000 0x11D6A0 0x48520 + 0x40200000 0x5CC00 0xB0318 ──┬── Total length = 0xB0318 + 0x8628 = 0xB8940 + 0x402B0318 0x10CF18 0x8628 ──┘ + 0x920000 0x115540 0xA160 + 0xBE000000 0x11F6A0 0x48520 Decrypt data in csf_fit_enc.txt: @@ -367,9 +376,9 @@ file. [Decrypt Data] ... - Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ - 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + Blocks = 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x115540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc.bin" 1.8.2 csf_fit_sign_enc.txt --------------------------- @@ -384,10 +393,10 @@ The second CSF is used to sign the encrypted FIT image previously generated [Authenticate Data] ... - Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin" - 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ - 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + Blocks = 0x401fadc0 0x57c00 0x1020 "flash-spl-fit-enc.bin" + 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x115540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc.bin" - Add the Install Secret Key command to generate a dummy DEK blob file, @@ -408,9 +417,28 @@ The second CSF is used to sign the encrypted FIT image previously generated [Decrypt Data] ... - Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ - 0x920000 0x113540 0xA160"flash-spl-fit-enc-dummy.bin", \ - 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin" + Blocks = 0x40200000 0x5CC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ + 0x920000 0x115540 0xA160"flash-spl-fit-enc-dummy.bin", \ + 0xBE000000 0x11F6A0 0x48520 "flash-spl-fit-enc-dummy.bin" + +1.8.3 (Optional) csf_fit_fdt.txt +--------------------------- + +When optional FIT FDT signature is used, user needs third CSF to sign encrypted-flash.bin +generated by 1.11.2. Because FIT FDT structure is not encrypted, so this step will not +encrypt any data. + +- FIT FDT signature "Authenticate Data" addresses in flash.bin build log: + + fit-fdt hab block: 0x401fadc0 0x57c00 0x3020 + +- "Authenticate Data" command in csf_fit_fdt.txt file: + + For example: + + [Authenticate Data] + ... + Blocks = 0x401fadc0 0x57c00 0x3020 "encrypted-flash.bin" 1.9 Encrypting and signing the FIT image ----------------------------------------- @@ -503,6 +531,10 @@ The CSF offsets can be obtained from the flash.bin build log: sld_csf_off 0x58c20 +- (Optional) FIT FDT CSF offset: + + fit-fdt csf_off 0x5ac20 + The encrypted flash.bin image can be then assembled: - Create a flash-spl-fit-enc.bin copy: @@ -539,7 +571,21 @@ The encrypted flash.bin image can be then assembled: $ dd if=dek_fit_blob.bin of=encrypted-flash.bin seek=$((0x165BC0)) bs=1 conv=notrunc -1.11.3 Flash encrypted boot image +1.11.3 (Optional) Create and Insert FIT FDT CSF +----------------------------------- + +If FIT FDT signature is used, users need to continue sign the encrypted-flash.bin +with csf_fit_fdt.txt CSF file + +- Create FIT FDT CSF binary file + + $ ./cst -i csf_fit_fdt.txt -o csf_fit_fdt.bin + +- Insert csf_fit_fdt.bin in encrypted-flash.bin at 0x5ac20 offset: + + $ dd if=csf_fit_fdt.bin of=encrypted-flash.bin seek=$((0x5ac20)) bs=1 conv=notrunc + +1.11.4 Flash encrypted boot image ----------------------------------- - Flash encrypted image in SDCard: diff --git a/doc/imx/habv4/guides/mx8m_secure_boot.txt b/doc/imx/habv4/guides/mx8m_secure_boot.txt index dbc8bcd1d5..8a6ac62dac 100644 --- a/doc/imx/habv4/guides/mx8m_secure_boot.txt +++ b/doc/imx/habv4/guides/mx8m_secure_boot.txt @@ -39,17 +39,23 @@ file are covered by a digital signature. Signed | +-----------------------------+ | Data | | u-boot-spl.bin | | | | + | | SPL - v | DDR FW | | Image + | | DDR FW | | Image + | | + | | + v | Hash of FIT FDT | | ------- +-----------------------------+ | | CSF - SPL + DDR FW | v +-----------------------------+ -------- | Padding | - ------- +-----------------------------+ -------- - Signed ^ | FDT - FIT | ^ - Data | +-----------------------------+ | - v | IVT - FIT | | - ------- +-----------------------------+ | - | CSF - FIT | | + ----------------- +-----------------------------+ -------- + ^ Signed ^ | FDT - FIT | ^ + | Data | +-----------------------------+ | + | v | IVT - FIT | | + Signed | -------+-----------------------------+ | + Data | | CSF - FIT | | +(optional) +-----------------------------+ | + v | IVT - FIT FDT (optional) | | + ----------------- +-----------------------------+ | + | CSF - FIT FDT (optional) | | ------- +-----------------------------+ | FIT ^ | u-boot-nodtb.bin | | Image | +-----------------------------+ | @@ -124,6 +130,17 @@ to extend the root of trust, authenticating the U-Boot, ARM trusted firmware The root of trust can be extended again at U-Boot level to authenticate Kernel and M4 images. +Note: +FIT uses a FDT structure to describe the images loading information. In SPL image, +the Hash of the FIT FDT structure is appended after DDR firmware. By default, +SPL will verify the Hash before parsing the FIT FDT structure to load images. +It means SPL image having to bind with FIT image. Users who need to decouple SPL +image with FIT image, for example upgrading FIT image individually, could use +optional FIT FDT signature. The FIT FDT signature approach generates another +signature to FIT image, see the IVT - FIT FDT (optional) and CSF - FIT FDT (optional) +in the signed flash.bin image layout. SPL will authenticate the FIT FDT structure +before parsing it to load images. + 1.2 Enabling the secure boot support in U-Boot ----------------------------------------------- @@ -138,6 +155,7 @@ configuration: - Defconfig: CONFIG_IMX_HAB=y + CONFIG_IMX_SPL_FIT_FDT_SIGNATURE=y (Optional, for FIT FDT signature only) - Kconfig: @@ -204,9 +222,11 @@ parameters and CSF offsets: spl hab block: 0x7e0fd0 0x1a000 0x2e600 Second Loader IMAGE: - sld_header_off 0x57c00 - sld_csf_off 0x58c20 - sld hab block: 0x401fcdc0 0x57c00 0x1020 + sld_header_off 0x57c00 + sld_csf_off 0x58c20 + sld hab block: 0x401fadc0 0x57c00 0x1020 + fit-fdt csf_off 0x5ac20 + fit-fdt hab block: 0x401fadc0 0x57c00 0x3020 Additional HAB information is provided by running the following command: @@ -216,10 +236,10 @@ Additional HAB information is provided by running the following command: TEE_LOAD_ADDR=0xfe000000 ATF_LOAD_ADDR=0x00910000 ./print_fit_hab.sh \ 0x60000 fsl-imx8mq-evk.dtb - 0x40200000 0x5AC00 0x9AAC8 - 0x910000 0xF56C8 0x9139 - 0xFE000000 0xFE804 0x4D268 - 0x4029AAC8 0x14BA6C 0x6DCF + 0x40200000 0x5CC00 0x9AAC8 + 0x910000 0xF76C8 0x9139 + 0xFE000000 0x100804 0x4D268 + 0x4029AAC8 0x14DA6C 0x6DCF If problems are encountered while using mkimage, please refer to the Linux User Guide which can be found alongside the latest Linux BSP release. @@ -238,7 +258,7 @@ this document. Please refer to introduction_habv4.txt for keys, certificates, SRK table, and SRK hash generation. The resulting file locations should be inserted into the CSF files like this: -- Insertion into both csf_spl.txt and csf_fit.txt +- Insertion into both csf_spl.txt, csf_fit.txt, and csf_fit_fdt.txt (optional) For Example: @@ -281,10 +301,10 @@ needed again for binary insertion. - FIT image "Authenticate Data" addresses in print_fit_hab build log: - 0x40200000 0x5AC00 0x9AAC8 - 0x910000 0xF56C8 0x9139 - 0xFE000000 0xFE804 0x4D268 - 0x4029AAC8 0x14BA6C 0x6DCF + 0x40200000 0x5CC00 0x9AAC8 + 0x910000 0xF76C8 0x9139 + 0xFE000000 0x100804 0x4D268 + 0x4029AAC8 0x14DA6C 0x6DCF - "Authenticate Data" command in csf_fit.txt file: @@ -292,11 +312,23 @@ needed again for binary insertion. [Authenticate Data] ... - Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ - 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ - 0x00910000 0x0F56C8 0x09139 "flash.bin", \ - 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ - 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" + Blocks = 0x401fadc0 0x057c00 0x1020 "flash.bin", \ + 0x40200000 0x05CC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F76C8 0x09139 "flash.bin", \ + 0xFE000000 0x100804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14DA6C 0x06DCF "flash.bin" + +- (Optional) FIT FDT signature "Authenticate Data" addresses in flash.bin build log: + + fit-fdt hab block: 0x401fadc0 0x57c00 0x3020 + +- (Optional) "Authenticate Data" command in csf_fit_fdt.txt file: + + For example: + + [Authenticate Data] + ... + Blocks = 0x401fadc0 0x57c00 0x3020 "signed-flash.bin" 1.4.1 Avoiding Kernel crash in closed devices ---------------------------------------------- @@ -352,6 +384,10 @@ The CSF offsets can be obtained from the flash.bin build log: sld_csf_off 0x58c20 +- (Optional) FIT FDT CSF offset: + + fit-fdt csf_off 0x5ac20 + The signed flash.bin image can be then assembled: - Create a flash.bin copy: @@ -366,6 +402,17 @@ The signed flash.bin image can be then assembled: $ dd if=csf_fit.bin of=signed_flash.bin seek=$((0x58c20)) bs=1 conv=notrunc +(Optional) If FIT FDT signature is used, users need to continue sign the signed_flash.bin +with csf_fit_fdt.txt CSF file + +- (Optional) Create FIT FDT CSF binary file (must after signed_flash.bin is generated): + + $ ./cst -i csf_fit_fdt.txt -o csf_fit_fdt.bin + +- (Optional) Insert csf_fit_fdt.bin in signed_flash.bin at 0x5ac20 offset: + + $ dd if=csf_fit_fdt.bin of=signed_flash.bin seek=$((0x5ac20)) bs=1 conv=notrunc + - Flash signed flash.bin image: $ sudo dd if=signed_flash.bin of=/dev/sd<x> bs=1K seek=33 && sync diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index 8babb27ee8..09bdc24295 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -41,18 +41,6 @@ If you want to use other types than above two, you should explicitly specify a guid for the FMP driver. .SH "OPTIONS" -One of -.BR --fit ", " --raw " or " --guid -option must be specified. - -.TP -.BR -f ", " --fit -Indicate that the blob is a FIT image file - -.TP -.BR -r ", " --raw -Indicate that the blob is a raw image file - .TP .BI "-g\fR,\fB --guid " guid-string Specify guid for image blob type. The format is: diff --git a/drivers/Makefile b/drivers/Makefile index 4e7cf28440..d886187e18 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ +obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/ obj-$(CONFIG_SPL_DM_RESET) += reset/ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index eff0fa134f..58ee17062c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -18,17 +18,19 @@ int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name) { - struct udevice *parent; + struct udevice *parent = NULL; struct driver *drv; int ret; - ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); - if (ret) { - log_err("%s: failed to get %s device (parent of %s)\n", - __func__, parent_name, name); - } else { - log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, - parent->name, parent); + if (parent_name) { + ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); + if (ret) { + log_err("%s: failed to get %s device (parent of %s)\n", + __func__, parent_name, name); + } else { + log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, + parent->name, parent); + } } drv = lists_driver_lookup_name(drv_name); diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index cdd348020b..b892b953cd 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -26,6 +26,7 @@ config SPL_CLK_IMX8MM depends on ARCH_IMX8M && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MX8MM @@ -34,6 +35,7 @@ config CLK_IMX8MM depends on ARCH_IMX8M select CLK select CLK_CCF + select CLK_COMPOSITE_CCF help This enables support clock driver for i.MX8MM platforms. @@ -106,3 +108,21 @@ config CLK_IMXRT1050 select CLK_COMPOSITE_CCF help This enables support clock driver for i.MXRT1050 platforms. + +config SPL_CLK_IMX93 + bool "Enable i.MX93 clock driver" + depends on ARCH_IMX9 && SPL + select SPL_CLK + select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF + help + Enable support for i.MX93 clocks. + +config CLK_IMX93 + bool "Enable i.MX93 clock driver" + depends on ARCH_IMX9 + select CLK + select CLK_CCF + select CLK_COMPOSITE_CCF + help + Enable support for i.MX93 clocks. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 5f07207cce..4eebc34092 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o clk-gate-93.o diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c new file mode 100644 index 0000000000..fa2c200760 --- /dev/null +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Author: Alice Guo <alice.guo@nxp.com> + */ + +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> + +#include "clk.h" + +#define PLL_CTRL 0x00 +#define CLKMUX_BYPASS BIT(2) +#define CLKMUX_EN BIT(1) +#define POWERUP BIT(0) +#define PLL_NUMERATOR 0x40 +#define PLL_MFN_MASK GENMASK(31, 2) +#define PLL_DENOMINATOR 0x50 +#define PLL_MFD_MASK GENMASK(29, 0) +#define PLL_DIV 0x60 +#define PLL_MFI_MASK GENMASK(24, 16) +#define PLL_RDIV_MASK GENMASK(15, 13) +#define PLL_ODIV_MASK GENMASK(7, 0) +#define PLL_STATUS 0xf0 +#define PLL_LOCK BIT(0) + +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + +static const struct imx93_pll_fracn_gp fracn_tbl[] = { + PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), + PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), + PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), + PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4), + PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), + PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), + PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), + PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5), + PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) +}; + +struct imx93_pll { + struct clk clk; + void __iomem *base; + const struct imx93_pll_fracn_gp *tbl; +}; + +#define to_imx93_pll(_c) container_of(_c, struct imx93_pll, clk) + +static int imx93_wait_pll_lock(struct imx93_pll *pll) +{ + u32 val; + + return readl_poll_timeout(pll->base + PLL_STATUS, val, (val & PLL_LOCK), 200); +} + +static const struct imx93_pll_fracn_gp *imx93_pll_get_cfg(struct imx93_pll *pll, ulong rate) +{ + const struct imx93_pll_fracn_gp *tbl = pll->tbl; + + for (int i = 0; i < ARRAY_SIZE(fracn_tbl); i++) + if (tbl[i].rate == rate) + return &tbl[i]; + + return NULL; +} + +static ulong imx93_pll_set_rate(struct clk *clk, ulong rate) +{ + struct imx93_pll *pll = to_imx93_pll(clk); + const struct imx93_pll_fracn_gp *cfg = NULL; + u32 tmp, pll_div, ana_mfn; + int ret; + + cfg = imx93_pll_get_cfg(pll, rate); + if (!cfg) + return -EINVAL; + + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + tmp &= ~POWERUP; + writel_relaxed(tmp, pll->base + PLL_CTRL); + tmp &= ~CLKMUX_BYPASS; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + pll_div = FIELD_PREP(PLL_MFI_MASK, cfg->mfi) | + FIELD_PREP(PLL_RDIV_MASK, cfg->rdiv) | cfg->odiv; + writel_relaxed(pll_div, pll->base + PLL_DIV); + writel_relaxed(cfg->mfd, pll->base + PLL_DENOMINATOR); + writel_relaxed(FIELD_PREP(PLL_MFN_MASK, cfg->mfn), pll->base + PLL_NUMERATOR); + + udelay(5); + + tmp |= POWERUP; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + ret = imx93_wait_pll_lock(pll); + if (ret) + return ret; + + tmp |= CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + ana_mfn = FIELD_GET(PLL_MFN_MASK, readl_relaxed(pll->base + PLL_STATUS)); + WARN(ana_mfn != cfg->mfn, "ana_mfn != cfg->mfn\n"); + + return 0; +} + +static ulong imx93_pll_get_rate(struct clk *clk) +{ + struct imx93_pll *pll = to_imx93_pll(clk); + const struct imx93_pll_fracn_gp *tbl = pll->tbl; + u32 pll_numerator, pll_denominator, pll_div; + u32 mfn, mfd, mfi, rdiv, odiv; + u64 fvco = clk_get_parent_rate(clk); + + pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR); + mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator); + + pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR); + mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator); + + pll_div = readl_relaxed(pll->base + PLL_DIV); + mfi = FIELD_GET(PLL_MFI_MASK, pll_div); + rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); + odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); + + for (int i = 0; i < ARRAY_SIZE(fracn_tbl); i++) + if (tbl[i].mfn == mfn && tbl[i].mfd == mfd && + tbl[i].rdiv == rdiv && tbl[i].odiv == odiv) + return tbl[i].rate; + + if (rdiv == 0) + rdiv = 1; + + switch (odiv) { + case 0 /* 00000000b */: + odiv = 2; + break; + case 1 /* 00000001b */: + odiv = 3; + break; + case 127 /* 01111111b */: + odiv = 255; + break; + default: + break; + } + + fvco = fvco * mfi * mfd + fvco * mfn; + do_div(fvco, mfd * rdiv * odiv); + + return (ulong)fvco; +} + +static int imx93_pll_enable(struct clk *clk) +{ + struct imx93_pll *pll = to_imx93_pll(clk); + u32 val; + int ret; + + val = readl_relaxed(pll->base + PLL_CTRL); + if (val & POWERUP) + return 0; + + val |= CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + val |= POWERUP; + writel_relaxed(val, pll->base + PLL_CTRL); + val |= CLKMUX_EN; + writel_relaxed(val, pll->base + PLL_CTRL); + + ret = imx93_wait_pll_lock(pll); + if (ret) + return ret; + + val &= ~CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + + return 0; +} + +static int imx93_pll_disable(struct clk *clk) +{ + struct imx93_pll *pll = to_imx93_pll(clk); + u32 val; + + val = readl_relaxed(pll->base + PLL_CTRL); + val &= ~POWERUP; + writel_relaxed(val, pll->base + PLL_CTRL); + + return 0; +} + +static struct clk_ops imx93_pll_ops = { + .set_rate = imx93_pll_set_rate, + .get_rate = imx93_pll_get_rate, + .enable = imx93_pll_enable, + .disable = imx93_pll_disable, +}; + +struct clk *clk_register_imx93_pll(const char *name, const char *parent_name, + void __iomem *base) +{ + struct imx93_pll *pll; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->tbl = fracn_tbl; + + ret = clk_register(&pll->clk, "imx93_pll", name, parent_name); + if (ret) { + printf("%s: failed to register pll: %d\n", __func__, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->clk; +} + +U_BOOT_DRIVER(imx93_pll) = { + .name = "imx93_pll", + .id = UCLASS_CLK, + .ops = &imx93_pll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c new file mode 100644 index 0000000000..7b43f18e6e --- /dev/null +++ b/drivers/clk/imx/clk-gate-93.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Author: Alice Guo <alice.guo@nxp.com> + */ + +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/bug.h> +#include <linux/clk-provider.h> + +#include "clk.h" + +#define LPCG_DIRECT 0x0 +#define LPCG_LPM_CUR 0x1c +#define LPM_SETTING_OFF 0x0 +#define LPM_SETTING_ON 0x4 +#define LPCG_AUTHEN 0x30 +#define WHITE_LIST_DM0 16 +#define DOMAIN_ID_A55 3 +#define TZ_NS BIT(9) +#define CPULPM_MOD BIT(2) + +struct imx93_clk_gate { + struct clk clk; + void __iomem *reg_base; + u8 lpcg_on_offset; + u8 lpcg_on_ctrl; + u8 lpcg_on_mask; + ulong flags; +}; + +#define to_imx93_clk_gate(_clk) container_of(_clk, struct imx93_clk_gate, clk) + +static bool imx93_clk_gate_check_authen(void __iomem *reg_base) +{ + u32 authen; + + authen = readl(reg_base + LPCG_AUTHEN); + if (!(authen & TZ_NS) || !(authen & BIT(WHITE_LIST_DM0 + DOMAIN_ID_A55))) + return false; + + return true; +} + +static void imx93_clk_gate_ctrl_hw(struct clk *clk, bool enable) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + u32 v; + + v = readl(gate->reg_base + LPCG_AUTHEN); + if (v & CPULPM_MOD) { + v = enable ? LPM_SETTING_ON : LPM_SETTING_OFF; + writel(v, gate->reg_base + LPCG_LPM_CUR); + } else { + v = readl(gate->reg_base + LPCG_DIRECT); + v &= ~(gate->lpcg_on_mask << gate->lpcg_on_offset); + if (enable) + v |= (gate->lpcg_on_ctrl & gate->lpcg_on_mask) << gate->lpcg_on_offset; + writel(v, gate->reg_base + LPCG_DIRECT); + } +} + +static int imx93_clk_gate_enable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (!imx93_clk_gate_check_authen(gate->reg_base)) + return -EINVAL; + + imx93_clk_gate_ctrl_hw(clk, true); + + return 0; +} + +static int imx93_clk_gate_disable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (!imx93_clk_gate_check_authen(gate->reg_base)) + return -EINVAL; + + imx93_clk_gate_ctrl_hw(clk, false); + + return 0; +} + +static ulong imx93_clk_gate_set_rate(struct clk *clk, ulong rate) +{ + struct clk *parent = clk_get_parent(clk); + + if (parent) + return clk_set_rate(parent, rate); + + return -ENODEV; +} + +static const struct clk_ops imx93_clk_gate_ops = { + .set_rate = imx93_clk_gate_set_rate, + .enable = imx93_clk_gate_enable, + .disable = imx93_clk_gate_disable, + .get_rate = clk_generic_get_rate, +}; + +static struct clk *register_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + u8 lpcg_on_ctrl, u8 lpcg_on_mask, ulong flags) +{ + struct imx93_clk_gate *gate; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg_base = reg_base; + gate->lpcg_on_offset = lpcg_on_offset; + gate->lpcg_on_ctrl = lpcg_on_ctrl; + gate->lpcg_on_mask = lpcg_on_mask; + gate->flags = flags; + + ret = clk_register(&gate->clk, "imx93_clk_gate", name, parent_name); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return &gate->clk; +} + +struct clk *clk_register_imx93_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + ulong flags) +{ + return register_clk_gate(name, parent_name, reg_base, lpcg_on_offset, 1, + 1, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +} + +U_BOOT_DRIVER(imx93_clk_gate) = { + .name = "imx93_clk_gate", + .id = UCLASS_CLK, + .ops = &imx93_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c new file mode 100644 index 0000000000..f0d7f49a1f --- /dev/null +++ b/drivers/clk/imx/clk-imx93.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Author: Alice Guo <alice.guo@nxp.com> + */ + +#include <asm/io.h> +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/imx93-clock.h> +#include <linux/delay.h> + +#include "clk.h" + +/* Low-speed clocks operating at <=133Mhz */ +static const char *const low_speed_sels[] = { "clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll" }; +/* Non-IO clocks operating at 133-399MHz */ +static const char *const non_io_sels[] = { "clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2" }; +/* Clocks for IP with max frequency in the range 400-1000MHz */ +static const char *const fast_speed_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2" }; +/* Audio interface-related clocks, such as SAI, MQS and SPDIF */ +static const char *const audio_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "clk_ext" }; +/* Video interface-related clocks */ +static const char *const video_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd0" }; +/* Special case CKO1 and CKO2 clocks */ +static const char *const cko1_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll" }; +static const char *const cko2_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll" }; +/* Special case TPM clocks */ +static const char *const tpm_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "audio_pll", "clk_ext" }; +static const char *const misc_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd2" }; + +struct imx93_clk_root { + u32 clk_id; + char *name; + const char * const *parent_names; + u32 off; + unsigned long flags; +}; + +static struct imx93_clk_root clk_roots[] = { + { IMX93_CLK_A55_PERIPH, "a55_periph_root", fast_speed_sels, 0x0000, CLK_IS_CRITICAL }, + { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", low_speed_sels, 0x0080, CLK_IS_CRITICAL }, + { IMX93_CLK_A55, "a55_root", fast_speed_sels, 0x0100, CLK_IS_CRITICAL }, + { IMX93_CLK_M33, "m33_root", low_speed_sels, 0x0180, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", low_speed_sels, 0x0280, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_AON, "bus_aon_root", low_speed_sels, 0x0300, CLK_IS_CRITICAL }, + { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", fast_speed_sels, 0x0380, CLK_IS_CRITICAL }, + { IMX93_CLK_SWO_TRACE, "swo_trace_root", low_speed_sels, 0x0400, }, + { IMX93_CLK_M33_SYSTICK, "m33_systick_root", low_speed_sels, 0x0480, }, + { IMX93_CLK_FLEXIO1, "flexio1_root", low_speed_sels, 0x0500, }, + { IMX93_CLK_FLEXIO2, "flexio2_root", low_speed_sels, 0x0580, }, + { IMX93_CLK_LPIT1, "lpit1_root", low_speed_sels, 0x0600, }, + { IMX93_CLK_LPIT2, "lpit2_root", low_speed_sels, 0x0680, }, + { IMX93_CLK_LPTMR1, "lptmr1_root", low_speed_sels, 0x0700, }, + { IMX93_CLK_LPTMR2, "lptmr2_root", low_speed_sels, 0x0780, }, + { IMX93_CLK_TPM1, "tpm1_root", tpm_sels, 0x0800, }, + { IMX93_CLK_TPM2, "tpm2_root", tpm_sels, 0x0880, }, + { IMX93_CLK_TPM3, "tpm3_root", tpm_sels, 0x0900, }, + { IMX93_CLK_TPM4, "tpm4_root", tpm_sels, 0x0980, }, + { IMX93_CLK_TPM5, "tpm5_root", tpm_sels, 0x0a00, }, + { IMX93_CLK_TPM6, "tpm6_root", tpm_sels, 0x0a80, }, + { IMX93_CLK_FLEXSPI1, "flexspi1_root", fast_speed_sels, 0x0b00, }, + { IMX93_CLK_CAN1, "can1_root", low_speed_sels, 0x0b80, }, + { IMX93_CLK_CAN2, "can2_root", low_speed_sels, 0x0c00, }, + { IMX93_CLK_LPUART1, "lpuart1_root", low_speed_sels, 0x0c80, }, + { IMX93_CLK_LPUART2, "lpuart2_root", low_speed_sels, 0x0d00, }, + { IMX93_CLK_LPUART3, "lpuart3_root", low_speed_sels, 0x0d80, }, + { IMX93_CLK_LPUART4, "lpuart4_root", low_speed_sels, 0x0e00, }, + { IMX93_CLK_LPUART5, "lpuart5_root", low_speed_sels, 0x0e80, }, + { IMX93_CLK_LPUART6, "lpuart6_root", low_speed_sels, 0x0f00, }, + { IMX93_CLK_LPUART7, "lpuart7_root", low_speed_sels, 0x0f80, }, + { IMX93_CLK_LPUART8, "lpuart8_root", low_speed_sels, 0x1000, }, + { IMX93_CLK_LPI2C1, "lpi2c1_root", low_speed_sels, 0x1080, }, + { IMX93_CLK_LPI2C2, "lpi2c2_root", low_speed_sels, 0x1100, }, + { IMX93_CLK_LPI2C3, "lpi2c3_root", low_speed_sels, 0x1180, }, + { IMX93_CLK_LPI2C4, "lpi2c4_root", low_speed_sels, 0x1200, }, + { IMX93_CLK_LPI2C5, "lpi2c5_root", low_speed_sels, 0x1280, }, + { IMX93_CLK_LPI2C6, "lpi2c6_root", low_speed_sels, 0x1300, }, + { IMX93_CLK_LPI2C7, "lpi2c7_root", low_speed_sels, 0x1380, }, + { IMX93_CLK_LPI2C8, "lpi2c8_root", low_speed_sels, 0x1400, }, + { IMX93_CLK_LPSPI1, "lpspi1_root", low_speed_sels, 0x1480, }, + { IMX93_CLK_LPSPI2, "lpspi2_root", low_speed_sels, 0x1500, }, + { IMX93_CLK_LPSPI3, "lpspi3_root", low_speed_sels, 0x1580, }, + { IMX93_CLK_LPSPI4, "lpspi4_root", low_speed_sels, 0x1600, }, + { IMX93_CLK_LPSPI5, "lpspi5_root", low_speed_sels, 0x1680, }, + { IMX93_CLK_LPSPI6, "lpspi6_root", low_speed_sels, 0x1700, }, + { IMX93_CLK_LPSPI7, "lpspi7_root", low_speed_sels, 0x1780, }, + { IMX93_CLK_LPSPI8, "lpspi8_root", low_speed_sels, 0x1800, }, + { IMX93_CLK_I3C1, "i3c1_root", low_speed_sels, 0x1880, }, + { IMX93_CLK_I3C2, "i3c2_root", low_speed_sels, 0x1900, }, + { IMX93_CLK_USDHC1, "usdhc1_root", fast_speed_sels, 0x1980, }, + { IMX93_CLK_USDHC2, "usdhc2_root", fast_speed_sels, 0x1a00, }, + { IMX93_CLK_USDHC3, "usdhc3_root", fast_speed_sels, 0x1a80, }, + { IMX93_CLK_SAI1, "sai1_root", audio_sels, 0x1b00, }, + { IMX93_CLK_SAI2, "sai2_root", audio_sels, 0x1b80, }, + { IMX93_CLK_SAI3, "sai3_root", audio_sels, 0x1c00, }, + { IMX93_CLK_CCM_CKO1, "ccm_cko1_root", cko1_sels, 0x1c80, }, + { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", cko2_sels, 0x1d00, }, + { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", cko1_sels, 0x1d80, }, + { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", cko2_sels, 0x1e00, }, + { IMX93_CLK_HSIO, "hsio_root", low_speed_sels, 0x1e80, }, + { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", low_speed_sels, 0x1f00, }, + { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", low_speed_sels, 0x1f80, }, + { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", misc_sels, 0x2000, }, + { IMX93_CLK_ML_APB, "ml_apb_root", low_speed_sels, 0x2180, }, + { IMX93_CLK_ML, "ml_root", fast_speed_sels, 0x2200, }, + { IMX93_CLK_MEDIA_AXI, "media_axi_root", fast_speed_sels, 0x2280, }, + { IMX93_CLK_MEDIA_APB, "media_apb_root", low_speed_sels, 0x2300, }, + { IMX93_CLK_MEDIA_LDB, "media_ldb_root", video_sels, 0x2380, }, + { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", video_sels, 0x2400, }, + { IMX93_CLK_CAM_PIX, "cam_pix_root", video_sels, 0x2480, }, + { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", video_sels, 0x2500, }, + { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", video_sels, 0x2580, }, + { IMX93_CLK_ADC, "adc_root", low_speed_sels, 0x2700, }, + { IMX93_CLK_PDM, "pdm_root", audio_sels, 0x2780, }, + { IMX93_CLK_TSTMR1, "tstmr1_root", low_speed_sels, 0x2800, }, + { IMX93_CLK_TSTMR2, "tstmr2_root", low_speed_sels, 0x2880, }, + { IMX93_CLK_MQS1, "mqs1_root", audio_sels, 0x2900, }, + { IMX93_CLK_MQS2, "mqs2_root", audio_sels, 0x2980, }, + { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", non_io_sels, 0x2a00, }, + { IMX93_CLK_SPDIF, "spdif_root", audio_sels, 0x2a80, }, + { IMX93_CLK_ENET, "enet_root", non_io_sels, 0x2b00, }, + { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", low_speed_sels, 0x2b80, }, + { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", low_speed_sels, 0x2c00, }, + { IMX93_CLK_ENET_REF, "enet_ref_root", non_io_sels, 0x2c80, }, + { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", low_speed_sels, 0x2d00, }, + { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", low_speed_sels, 0x2d80, }, + { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", low_speed_sels, 0x2e00, }, + { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", low_speed_sels, 0x2e80, }, + { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", misc_sels, 0x2f00, } +}; + +struct imx93_clk_ccgr { + u32 clk_id; + char *name; + char *parent_names; + u32 off; + unsigned long flags; +}; + +static struct imx93_clk_ccgr clk_ccgrs[] = { + { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, CLK_IS_CRITICAL }, + { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, + { IMX93_CLK_ADC1_GATE, "adc1", "clock-osc-24m", 0x82c0, }, + { IMX93_CLK_WDOG1_GATE, "wdog1", "clock-osc-24m", 0x8300, }, + { IMX93_CLK_WDOG2_GATE, "wdog2", "clock-osc-24m", 0x8340, }, + { IMX93_CLK_WDOG3_GATE, "wdog3", "clock-osc-24m", 0x8380, }, + { IMX93_CLK_WDOG4_GATE, "wdog4", "clock-osc-24m", 0x83c0, }, + { IMX93_CLK_WDOG5_GATE, "wdog5", "clock-osc-24m", 0x8400, }, + { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, + { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, + { IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, }, + { IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, }, + { IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, }, + { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, + { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, + { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, + { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, + { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, + { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, + { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, + { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, }, + { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, + { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, }, + { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, }, + { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, + { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, + { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, + { IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, }, + { IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, }, + { IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, }, + { IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, }, + { IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, }, + { IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, }, + { IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, }, + { IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, }, + { IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, }, + { IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, }, + { IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, }, + { IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, }, + { IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, }, + { IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, }, + { IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, }, + { IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, }, + { IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, }, + { IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, }, + { IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, }, + { IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, }, + { IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, }, + { IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, }, + { IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, }, + { IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, }, + { IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, }, + { IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, }, + { IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, }, + { IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, }, + { IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, }, + { IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, }, + { IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, }, + { IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, }, + { IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, }, + { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, }, + { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, + { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, + { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, + { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, + { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, + { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, + { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, }, + { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, + { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, + { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "clock-osc-24m", 0x9a80, }, + { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, + { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, + { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, + { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, + { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, + { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-32k", 0x9dc0, }, + { IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, }, + { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, }, + { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, + { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, + { IMX93_CLK_TMC_GATE, "tmc", "clock-osc-24m", 0x9f40, }, + { IMX93_CLK_PMRO_GATE, "pmro", "clock-osc-24m", 0x9f80, } +}; + +static ulong imx93_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static ulong imx93_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static int imx93_clk_enable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_enable(c); +} + +static int imx93_clk_disable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_disable(c); +} + +static int imx93_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + + err = clk_get_by_id(parent->id, &p); + if (err) + return err; + + return clk_set_parent(c, p); +} + +static struct clk_ops imx93_clk_ops = { + .set_rate = imx93_clk_set_rate, + .get_rate = imx93_clk_get_rate, + .enable = imx93_clk_enable, + .disable = imx93_clk_disable, + .set_parent = imx93_clk_set_parent, +}; + +struct clk *imx93_clk_composite(const char *name, const char * const *parent_names, + int num_parents, void __iomem *reg, unsigned long flags) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg; + mux->shift = 8; + mux->mask = 3; + mux->num_parents = num_parents; + mux->flags = flags; + mux->parent_names = parent_names; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg; + div->shift = 0; + div->width = 8; + div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate->reg = reg; + gate->bit_idx = 24; + gate->flags = CLK_GATE_SET_TO_DISABLE | flags; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + &gate->clk, &clk_gate_ops, flags); + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} + +static int imx93_clk_probe(struct udevice *dev) +{ + void __iomem *ccm_base; + struct imx93_clk_root *root; + struct imx93_clk_ccgr *ccgr; + struct clk *clk; + struct clk fixed_clock; + int ret; + + clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL)); + + ret = clk_get_by_name(dev, "osc_24m", &fixed_clock); + if (ret) + return ret; + clk_dm(IMX93_CLK_24M, dev_get_clk_ptr(fixed_clock.dev)); + + ret = clk_get_by_name(dev, "clk_ext1", &fixed_clock); + if (ret) + return ret; + clk_dm(IMX93_CLK_EXT1, dev_get_clk_ptr(fixed_clock.dev)); + + ret = clk_get_by_name(dev, "osc_32k", &fixed_clock); + if (ret) + return ret; + clk_dm(IMX93_CLK_32K, dev_get_clk_ptr(fixed_clock.dev)); + + clk_dm(IMX93_CLK_SYS_PLL_PFD0, + clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000UL)); + clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2, + imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); + + clk_dm(IMX93_CLK_SYS_PLL_PFD1, + clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000UL)); + clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2, + imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); + + clk_dm(IMX93_CLK_SYS_PLL_PFD2, + clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000UL)); + clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, + imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); + +#ifndef CONFIG_SPL_BUILD + clk_dm(IMX93_CLK_VIDEO_PLL, + clk_register_imx93_pll("video_pll", "clock-osc-24m", (void __iomem *)0x44481400)); +#endif + + ccm_base = dev_read_addr_ptr(dev); + if (ccm_base == (void *)FDT_ADDR_T_NONE) { + debug("%s: No CCM register base address\n", __func__); + return -EINVAL; + } + + for (int i = 0; i < ARRAY_SIZE(clk_roots); i++) { + root = &clk_roots[i]; + clk = imx93_clk_composite(root->name, root->parent_names, 4, + ccm_base + root->off, root->flags); + clk_dm(root->clk_id, clk); + } + + for (int i = 0; i < ARRAY_SIZE(clk_ccgrs); i++) { + ccgr = &clk_ccgrs[i]; + clk = clk_register_imx93_clk_gate(ccgr->name, ccgr->parent_names, + ccm_base + ccgr->off, 0, ccgr->flags); + clk_dm(ccgr->clk_id, clk); + } + + return 0; +} + +static const struct udevice_id imx93_clk_ids[] = { + { .compatible = "fsl,imx93-ccm" }, + { }, +}; + +U_BOOT_DRIVER(imx93_clk) = { + .name = "imx93_clk", + .id = UCLASS_CLK, + .of_match = imx93_clk_ids, + .ops = &imx93_clk_ops, + .probe = imx93_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 60f287046b..e690756150 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -41,6 +41,21 @@ struct imx_pll14xx_clk { int flags; }; +struct imx93_pll_fracn_gp { + unsigned int rate; + unsigned int mfi; + unsigned int mfn; + unsigned int mfd; + unsigned int rdiv; + unsigned int odiv; +}; + +struct clk *clk_register_imx93_pll(const char *name, const char *parent_name, + void __iomem *reg); +struct clk *clk_register_imx93_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + ulong flags); + struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index de1c876e8a..c39c3adfe7 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -215,6 +215,7 @@ static int imx8_cpu_probe(struct udevice *dev) { struct cpu_imx_plat *plat = dev_get_plat(dev); u32 cpurev; + fdt_addr_t addr; set_core_data(dev); cpurev = get_cpu_rev(); @@ -222,12 +223,14 @@ static int imx8_cpu_probe(struct udevice *dev) plat->rev = get_imx8_rev(cpurev & 0xFFF); plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000; - plat->mpidr = dev_read_addr(dev); - if (plat->mpidr == FDT_ADDR_T_NONE) { + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { printf("%s: Failed to get CPU reg property\n", __func__); return -EINVAL; } + plat->mpidr = (u32)addr; + return 0; } diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 702d204a3d..da5955e31d 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -96,3 +96,13 @@ config RNG_SELF_TEST must be run before running any RNG based crypto implementation. endif + +config FSL_DCP_RNG + bool "Enable Random Number Generator support" + depends on DM_RNG + default n + help + Enable support for the hardware based random number generator + module of the DCP.It uses the True Random Number Generator (TRNG) + and a Pseudo-Random Number Generator (PRNG) to achieve a true + randomness and cryptographic strength. diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 926300e2ab..c653208d23 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_FSL_BLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c new file mode 100644 index 0000000000..a797710c2e --- /dev/null +++ b/drivers/crypto/fsl/dcp_rng.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * RNG driver for Freescale RNGC + * + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. + * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx> + * Copyright 2022 NXP + * + * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux + */ + +#include <asm/cache.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <rng.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <dm/root.h> + +#define DCP_RNG_MAX_FIFO_STORE_SIZE 4 +#define RNGC_VER_ID 0x0000 +#define RNGC_COMMAND 0x0004 +#define RNGC_CONTROL 0x0008 +#define RNGC_STATUS 0x000C +#define RNGC_ERROR 0x0010 +#define RNGC_FIFO 0x0014 + +/* the fields in the ver id register */ +#define RNGC_TYPE_SHIFT 28 + +/* the rng_type field */ +#define RNGC_TYPE_RNGB 0x1 +#define RNGC_TYPE_RNGC 0x2 + +#define RNGC_CMD_CLR_ERR 0x00000020 +#define RNGC_CMD_SEED 0x00000002 + +#define RNGC_CTRL_AUTO_SEED 0x00000010 + +#define RNGC_STATUS_ERROR 0x00010000 +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +#define RNGC_STATUS_SEED_DONE 0x00000020 +#define RNGC_STATUS_ST_DONE 0x00000010 + +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 + +#define RNGC_TIMEOUT 3000000U /* 3 sec */ + +struct imx_rngc { + unsigned long base; +}; + +static int rngc_read(struct udevice *dev, void *data, size_t len) +{ + struct imx_rngc *rngc = dev_get_priv(dev); + u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE]; + u32 status, level; + size_t size; + + while (len) { + status = readl(rngc->base + RNGC_STATUS); + + /* is there some error while reading this random number? */ + if (status & RNGC_STATUS_ERROR) + break; + /* how many random numbers are in FIFO? [0-16] */ + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >> + RNGC_STATUS_FIFO_LEVEL_SHIFT; + + if (level) { + /* retrieve a random number from FIFO */ + *(u32 *)buffer = readl(rngc->base + RNGC_FIFO); + size = min(len, sizeof(u32)); + memcpy(data, buffer, size); + data += size; + len -= size; + } + } + + return len ? -EIO : 0; +} + +static int rngc_init(struct imx_rngc *rngc) +{ + u32 cmd, ctrl, status, err_reg = 0; + unsigned long long timeval = 0; + unsigned long long timeout = RNGC_TIMEOUT; + + /* clear error */ + cmd = readl(rngc->base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND); + + /* create seed, repeat while there is some statistical error */ + do { + /* seed creation */ + cmd = readl(rngc->base + RNGC_COMMAND); + writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND); + + udelay(1); + timeval += 1; + + status = readl(rngc->base + RNGC_STATUS); + err_reg = readl(rngc->base + RNGC_ERROR); + + if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE)) + break; + + if (timeval > timeout) { + debug("rngc timed out\n"); + return -ETIMEDOUT; + } + } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR); + + if (err_reg) + return -EIO; + + /* + * enable automatic seeding, the rngc creates a new seed automatically + * after serving 2^20 random 160-bit words + */ + ctrl = readl(rngc->base + RNGC_CONTROL); + ctrl |= RNGC_CTRL_AUTO_SEED; + writel(ctrl, rngc->base + RNGC_CONTROL); + return 0; +} + +static int rngc_probe(struct udevice *dev) +{ + struct imx_rngc *rngc = dev_get_priv(dev); + fdt_addr_t addr; + u32 ver_id; + u8 rng_type; + int ret; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + ret = -EINVAL; + goto err; + } + + rngc->base = addr; + ver_id = readl(rngc->base + RNGC_VER_ID); + rng_type = ver_id >> RNGC_TYPE_SHIFT; + /* + * This driver supports only RNGC and RNGB. (There's a different + * driver for RNGA.) + */ + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) { + ret = -ENODEV; + goto err; + } + + ret = rngc_init(rngc); + if (ret) + goto err; + + return 0; + +err: + printf("%s error = %d\n", __func__, ret); + return ret; +} + +static const struct dm_rng_ops rngc_ops = { + .read = rngc_read, +}; + +static const struct udevice_id rngc_dt_ids[] = { + { .compatible = "fsl,imx25-rngb" }, + { } +}; + +U_BOOT_DRIVER(dcp_rng) = { + .name = "dcp_rng", + .id = UCLASS_RNG, + .of_match = rngc_dt_ids, + .ops = &rngc_ops, + .probe = rngc_probe, + .priv_auto = sizeof(struct imx_rngc), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 66f2819fcc..226e4be51d 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -146,9 +146,13 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, sg_entry_len = (sec_in32(&ctx->sg_tbl[i].len_flag) & SG_ENTRY_LENGTH_MASK); len += sg_entry_len; - addr = ctx->sg_tbl[i].addr_hi; - addr = (addr << 32) | ctx->sg_tbl[i].addr_lo; - flush_dcache_range((ulong)addr, (ulong)addr + sg_entry_len); +#ifdef CONFIG_CAAM_64BIT + addr = sec_in32(&ctx->sg_tbl[i].addr_hi); + addr = (addr << 32) | sec_in32(&ctx->sg_tbl[i].addr_lo); +#else + addr = sec_in32(&ctx->sg_tbl[i].addr_lo); +#endif + flush_dcache_range(addr, addr + sg_entry_len); } inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, ctx->hash, @@ -182,13 +186,6 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, uint32_t *desc; unsigned int size; - if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || - !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { - puts("Error: Address arguments are not aligned\n"); - return -EINVAL; - } - - debug("\ncaam hash\n"); desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c index c41a933a5d..cfe6332e88 100644 --- a/drivers/crypto/fsl/fsl_rsa.c +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -6,6 +6,7 @@ #include <config.h> #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <log.h> #include <asm/types.h> @@ -36,7 +37,7 @@ int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, inline_cnstr_jobdesc_pkha_rsaexp(desc, &pkin, out, sig_len); - flush_dcache_range((ulong)sig, (ulong)(sig + sig_len)); + flush_dcache_range((ulong)sig, (ulong)sig + sig_len); flush_dcache_range((ulong)prop->modulus, (ulong)(prop->modulus) + keylen); flush_dcache_range((ulong)prop->public_exponent, (ulong)(prop->public_exponent) + prop->exp_len); flush_dcache_range((ulong)desc, (ulong)desc + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE)); @@ -48,7 +49,7 @@ int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, return -EFAULT; } - invalidate_dcache_range((ulong)out, (ulong)sig_len); + invalidate_dcache_range((ulong)out, (ulong)out + sig_len); return 0; } diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig index 179f34530d..328fbabb6d 100644 --- a/drivers/ddr/imx/Kconfig +++ b/drivers/ddr/imx/Kconfig @@ -1,2 +1,4 @@ source "drivers/ddr/imx/imx8m/Kconfig" source "drivers/ddr/imx/imx8ulp/Kconfig" +source "drivers/ddr/imx/imx9/Kconfig" +source "drivers/ddr/imx/phy/Kconfig" diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index 0585de6218..15a2b030f8 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -3,6 +3,7 @@ menu "i.MX8M DDR controllers" config IMX8M_DRAM bool "imx8m dram" + select IMX_SNPS_DDR_PHY config IMX8M_LPDDR4 bool "imx8m lpddr4" diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile index bd9bcb8d53..aed91dc23f 100644 --- a/drivers/ddr/imx/imx8m/Makefile +++ b/drivers/ddr/imx/imx8m/Makefile @@ -5,5 +5,6 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o +obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o +obj-y += ../phy/ endif diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index c8c9314770..d64edc57be 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -11,6 +11,11 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { int i = 0; @@ -91,6 +96,209 @@ void __weak board_dram_ecc_scrub(void) { } +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, + unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} + +static unsigned int look_for_max(unsigned int data[], + unsigned int addr_start, unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && (data[i] > imax)) + imax = data[i]; + } + + return imax; +} + +void get_trained_CDD(u32 fsp) +{ + unsigned int i, ddr_type, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + if (ddr_type == 0x20) { + for (i = 0; i < 6; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4); + if (i == 0) { + cdd_cha[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_cha[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; + } else { + unsigned int ddr4_cdd[64]; + + for (i = 0; i < 29; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4); + ddr4_cdd[i * 2] = tmp & 0xff; + ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12); + g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24); + g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40); + g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56); + } +} + +void update_umctl2_rank_space_setting(unsigned int pstat_num) +{ + unsigned int i, ddr_type; + unsigned int addr_slot, rdata, tmp, tmp_t; + unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + for (i = 0; i < pstat_num; i++) { + addr_slot = i ? (i + 1) * 0x1000 : 0; + if (ddr_type == 0x20) { + /* update r2w:[13:8], w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (is_imx8mp()) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + + ddrc_r2w = (rdata >> 8) & 0x3f; + if (is_imx8mp()) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } else { + /* update w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (is_imx8mp()) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + tmp_t = (rdata & 0xffffffc0) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t); + + /* update r2w:[13:8] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_r2w = (rdata >> 8) & 0x3f; + if (is_imx8mp()) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8); + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } + + if (!is_imx8mq()) { + /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ + rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); + ddrc_wr_gap = (rdata >> 8) & 0xf; + if (is_imx8mp()) + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); + else + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + if (is_imx8mp()) + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1); + else + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t); + } + } + + if (is_imx8mq()) { + /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ + rdata = reg32_read(DDRC_RANKCTL(0)); + ddrc_wr_gap = (rdata >> 8) & 0xf; + tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write(DDRC_RANKCTL(0), tmp_t); + } +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int tmp, initial_drate, target_freq; @@ -251,3 +459,8 @@ int ddr_init(struct dram_timing_info *dram_timing) return 0; } + +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr) +{ + return 4 * paddr_apb_from_ctlr; +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c deleted file mode 100644 index 326b92d784..0000000000 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include <common.h> -#include <errno.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/ddr.h> -#include <asm/arch/clock.h> -#include <asm/arch/ddr.h> -#include <asm/arch/lpddr4_define.h> -#include <asm/arch/sys_proto.h> - -static unsigned int g_cdd_rr_max[4]; -static unsigned int g_cdd_rw_max[4]; -static unsigned int g_cdd_wr_max[4]; -static unsigned int g_cdd_ww_max[4]; - -static inline void poll_pmu_message_ready(void) -{ - unsigned int reg; - - do { - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - } while (reg & 0x1); -} - -static inline void ack_pmu_message_receive(void) -{ - unsigned int reg; - - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); - - do { - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - } while (!(reg & 0x1)); - - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); -} - -static inline unsigned int get_mail(void) -{ - unsigned int reg; - - poll_pmu_message_ready(); - - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); - - ack_pmu_message_receive(); - - return reg; -} - -static inline unsigned int get_stream_message(void) -{ - unsigned int reg, reg2; - - poll_pmu_message_ready(); - - reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); - - reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); - - reg2 = (reg2 << 16) | reg; - - ack_pmu_message_receive(); - - return reg2; -} - -static inline void decode_major_message(unsigned int mail) -{ - debug("[PMU Major message = 0x%08x]\n", mail); -} - -static inline void decode_streaming_message(void) -{ - unsigned int string_index, arg __maybe_unused; - int i = 0; - - string_index = get_stream_message(); - debug("PMU String index = 0x%08x\n", string_index); - while (i < (string_index & 0xffff)) { - arg = get_stream_message(); - debug("arg[%d] = 0x%08x\n", i, arg); - i++; - } - - debug("\n"); -} - -int wait_ddrphy_training_complete(void) -{ - unsigned int mail; - - while (1) { - mail = get_mail(); - decode_major_message(mail); - if (mail == 0x08) { - decode_streaming_message(); - } else if (mail == 0x07) { - debug("Training PASS\n"); - return 0; - } else if (mail == 0xff) { - printf("Training FAILED\n"); - return -1; - } - } -} - -void ddrphy_init_set_dfi_clk(unsigned int drate) -{ - switch (drate) { - case 4000: - dram_pll_init(MHZ(1000)); - dram_disable_bypass(); - break; - case 3200: - dram_pll_init(MHZ(800)); - dram_disable_bypass(); - break; - case 3000: - dram_pll_init(MHZ(750)); - dram_disable_bypass(); - break; - case 2400: - dram_pll_init(MHZ(600)); - dram_disable_bypass(); - break; - case 1600: - dram_pll_init(MHZ(400)); - dram_disable_bypass(); - break; - case 1066: - dram_pll_init(MHZ(266)); - dram_disable_bypass(); - break; - case 667: - dram_pll_init(MHZ(167)); - dram_disable_bypass(); - break; - case 400: - dram_enable_bypass(MHZ(400)); - break; - case 100: - dram_enable_bypass(MHZ(100)); - break; - default: - return; - } -} - -void ddrphy_init_read_msg_block(enum fw_type type) -{ -} - -void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, - unsigned int mr_data) -{ - unsigned int tmp; - /* - * 1. Poll MRSTAT.mr_wr_busy until it is 0. - * This checks that there is no outstanding MR transaction. - * No writes should be performed to MRCTRL0 and MRCTRL1 if - * MRSTAT.mr_wr_busy = 1. - */ - do { - tmp = reg32_read(DDRC_MRSTAT(0)); - } while (tmp & 0x1); - /* - * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and - * (for MRWs) MRCTRL1.mr_data to define the MR transaction. - */ - reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); - reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); - reg32setbit(DDRC_MRCTRL0(0), 31); -} - -unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) -{ - unsigned int tmp; - - reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); - do { - tmp = reg32_read(DDRC_MRSTAT(0)); - } while (tmp & 0x1); - - reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); - reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); - reg32setbit(DDRC_MRCTRL0(0), 31); - do { - tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); - } while ((tmp & 0x8) == 0); - tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); - tmp = tmp & 0xff; - reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); - - return tmp; -} - -unsigned int look_for_max(unsigned int data[], - unsigned int addr_start, unsigned int addr_end) -{ - unsigned int i, imax = 0; - - for (i = addr_start; i <= addr_end; i++) { - if (((data[i] >> 7) == 0) && (data[i] > imax)) - imax = data[i]; - } - - return imax; -} - -void get_trained_CDD(u32 fsp) -{ - unsigned int i, ddr_type, tmp; - unsigned int cdd_cha[12], cdd_chb[12]; - unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; - unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; - - ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; - if (ddr_type == 0x20) { - for (i = 0; i < 6; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4); - cdd_cha[i * 2] = tmp & 0xff; - cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; - } - - for (i = 0; i < 7; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4); - if (i == 0) { - cdd_cha[0] = (tmp >> 8) & 0xff; - } else if (i == 6) { - cdd_cha[11] = tmp & 0xff; - } else { - cdd_chb[i * 2 - 1] = tmp & 0xff; - cdd_chb[i * 2] = (tmp >> 8) & 0xff; - } - } - - cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); - cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); - cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); - cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); - cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); - cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); - cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); - cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); - g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; - g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; - g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; - g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; - } else { - unsigned int ddr4_cdd[64]; - - for (i = 0; i < 29; i++) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4); - ddr4_cdd[i * 2] = tmp & 0xff; - ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; - } - - g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12); - g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24); - g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40); - g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56); - } -} - -void update_umctl2_rank_space_setting(unsigned int pstat_num) -{ - unsigned int i, ddr_type; - unsigned int addr_slot, rdata, tmp, tmp_t; - unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap; - - ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; - for (i = 0; i < pstat_num; i++) { - addr_slot = i ? (i + 1) * 0x1000 : 0; - if (ddr_type == 0x20) { - /* update r2w:[13:8], w2r:[5:0] */ - rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); - ddrc_w2r = rdata & 0x3f; - if (is_imx8mp()) - tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); - else - tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; - ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; - - ddrc_r2w = (rdata >> 8) & 0x3f; - if (is_imx8mp()) - tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); - else - tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; - ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; - - tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r; - reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); - } else { - /* update w2r:[5:0] */ - rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); - ddrc_w2r = rdata & 0x3f; - if (is_imx8mp()) - tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); - else - tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; - ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; - tmp_t = (rdata & 0xffffffc0) | ddrc_w2r; - reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t); - - /* update r2w:[13:8] */ - rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); - ddrc_r2w = (rdata >> 8) & 0x3f; - if (is_imx8mp()) - tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); - else - tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; - ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; - - tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8); - reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); - } - - if (!is_imx8mq()) { - /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ - rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); - ddrc_wr_gap = (rdata >> 8) & 0xf; - if (is_imx8mp()) - tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); - else - tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; - ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; - - ddrc_rd_gap = (rdata >> 4) & 0xf; - if (is_imx8mp()) - tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1); - else - tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1; - ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; - - tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); - reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t); - } - } - - if (is_imx8mq()) { - /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ - rdata = reg32_read(DDRC_RANKCTL(0)); - ddrc_wr_gap = (rdata >> 8) & 0xf; - tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1; - ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; - - ddrc_rd_gap = (rdata >> 4) & 0xf; - tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1; - ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; - - tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); - reg32_write(DDRC_RANKCTL(0), tmp_t); - } -} diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index 42848863aa..5448c33838 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE help The DRAM config timing data need to be saved into sram for low power use. - default 0x2006c000 + default 0x20055000 endmenu diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig new file mode 100644 index 0000000000..0c2ee89c31 --- /dev/null +++ b/drivers/ddr/imx/imx9/Kconfig @@ -0,0 +1,33 @@ +menu "i.MX9 DDR controllers" + depends on ARCH_IMX9 + +config IMX9_DRAM + bool "imx9 dram" + select IMX_SNPS_DDR_PHY + +config IMX9_LPDDR4X + bool "imx9 lpddr4 and lpddr4x" + select IMX9_DRAM + help + Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC. + +config IMX9_DRAM_PM_COUNTER + bool "imx9 DDRC performance monitor counter" + default y + help + Enable DDR controller performance monitor counter for reference events. + +config IMX9_DRAM_INLINE_ECC + bool "Enable DDR INLINE ECC feature" + default n + help + Select to enable DDR INLINE ECC feature + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. + default 0x2051C000 + +endmenu diff --git a/drivers/ddr/imx/imx9/Makefile b/drivers/ddr/imx/imx9/Makefile new file mode 100644 index 0000000000..9403f988b3 --- /dev/null +++ b/drivers/ddr/imx/imx9/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX9_DRAM) += ddr_init.o +obj-y += ../phy/ +endif diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c new file mode 100644 index 0000000000..17b4b259ac --- /dev/null +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <errno.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> + +static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + +void ddrphy_coldreset(void) +{ + /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */ + /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */ + /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */ + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + mdelay(10); + /* src_gen_dphy_PwrOKIn_sw_rst_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert() */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); +} + +void check_ddrc_idle(void){ + uint32_t regval; + + do{ + regval = readl(REG_DDRDSR_2); + if(regval & BIT(31)) + break; + }while(1); +} + +void check_dfi_init_complete(void) +{ + uint32_t regval; + + do{ + regval = readl(REG_DDRDSR_2); + if(regval & BIT(2)) + break; + }while(1); + setbits_le32(REG_DDRDSR_2, BIT(2)); +} + +void ddrc_config(struct dram_cfg_param *ddrc_config, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + writel(ddrc_config->val, (ulong)ddrc_config->reg); + ddrc_config++; + } +} + +static unsigned int look_for_max(unsigned int data[], + unsigned int addr_start, unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && (data[i] > imax)) + imax = data[i]; + } + + return imax; +} + +void get_trained_CDD(u32 fsp) +{ + unsigned int i, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + for (i = 0; i < 6; i++) { + tmp = dwc_ddrphy_apb_rd(0x54013 + i); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = dwc_ddrphy_apb_rd(0x5402c + i); + + if (i == 0) { + cdd_chb[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_chb[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; +} + +void update_umctl2_rank_space_setting(unsigned int pstat_num) +{ + u32 tmp, tmp_t; + + int wwt, rrt, wrt, rwt; + int ext_wwt, ext_rrt, ext_wrt, ext_rwt; + int max_wwt, max_rrt, max_wrt, max_rwt; + + /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ + tmp = readl(REG_DDR_TIMING_CFG_0); + wwt = (tmp >> 24) & 0x3; + rrt = (tmp >> 26) & 0x3; + wrt = (tmp >> 28) & 0x3; + rwt = (tmp >> 30) & 0x3; + + /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ + tmp_t = readl(REG_DDR_TIMING_CFG_4); + ext_wwt = (tmp >> 8) & 0x1; + ext_rrt = (tmp >> 10) & 0x1; + ext_wrt = (tmp >> 12) & 0x1; + ext_rwt = (tmp >> 14) & 0x3; + + wwt = (ext_wwt << 2) | wwt; + rrt = (ext_rrt << 2) | wwt; + wrt = (ext_wrt << 2) | wrt; + rwt = (ext_rwt << 2) | rwt; + + /* calculate the maximum between controller and cdd values */ + max_wwt = MAX(g_cdd_ww_max[0], wwt); + max_rrt = MAX(g_cdd_rr_max[0], rrt); + max_wrt = MAX(g_cdd_wr_max[0], wrt); + max_rwt = MAX(g_cdd_rw_max[0], rwt); + + /* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */ + if (max_wwt > 7) + max_wwt = 7; + if (max_rrt > 7) + max_rrt = 7; + if (max_wrt > 7) + max_wrt = 7; + if (max_rwt > 15) + max_rwt = 15; + + /* recalculate timings for controller registers */ + wwt = max_wwt & 0x3; + rrt = max_rrt & 0x3; + wrt = max_wrt & 0x3; + rwt = max_rwt & 0x3; + + ext_wwt = (max_wwt & 0x4) >> 2; + ext_rrt = (max_rrt & 0x4) >> 2; + ext_wrt = (max_wrt & 0x4) >> 2; + ext_rwt = (max_rwt & 0xC) >> 2; + + /* update timing_cfg_0 and timing_cfg_4 */ + tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | + (rrt << 26) | (wwt << 24); + writel(tmp, REG_DDR_TIMING_CFG_0); + + tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) | + (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); + writel(tmp_t, REG_DDR_TIMING_CFG_4); +} + +void update_inline_ecc_setting(void) +{ + u32 val, sa, ea; + + val = readl(REG_DDR_CS0_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS0_BNDS); + } + + val = readl(REG_DDR_CS1_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS1_BNDS); + } + + /* Enable Inline ECC */ + setbits_le32(REG_DDR_ERR_EN, BIT(31) | BIT(30)); + + /* Enable data initialization */ + setbits_le32(REG_DDR_SDRAM_CFG2, BIT(4)); +} + +int ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int initial_drate; + int ret; + u32 regval; + + debug("DDRINFO: start DRAM init\n"); + + /* reset ddrphy */ + ddrphy_coldreset(); + + debug("DDRINFO: cfg clk\n"); + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(initial_drate); + + /* + * Start PHY initialization and training by + * accessing relevant PUB registers + */ + debug("DDRINFO:ddrphy config start\n"); + + ret = ddr_cfg_phy(dram_timing); + if (ret) + return ret; + + debug("DDRINFO: ddrphy config done\n"); + + /* rogram the ddrc registers */ + debug("DDRINFO: ddrc config start\n"); + ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); + +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC + update_inline_ecc_setting(); +#endif + +#ifdef CONFIG_IMX9_DRAM_PM_COUNTER + writel(0x200000, REG_DDR_DEBUG_19); +#endif + + check_dfi_init_complete(); + + regval=readl(REG_DDR_SDRAM_CFG); + writel((regval|0x80000000), REG_DDR_SDRAM_CFG); + + check_ddrc_idle(); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); + + return 0; +} + +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr) +{ + uint32_t paddr_apb_qual; + uint32_t paddr_apb_unqual_dec_22_13; + uint32_t paddr_apb_unqual_dec_19_13; + uint32_t paddr_apb_unqual_dec_12_1; + uint32_t paddr_apb_unqual; + uint32_t paddr_apb_phy; + + paddr_apb_qual = (paddr_apb_from_ctlr << 1); + paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13); + paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1); + + switch(paddr_apb_unqual_dec_22_13) { + case 0x000 : paddr_apb_unqual_dec_19_13 = 0x00;break; + case 0x001 : paddr_apb_unqual_dec_19_13 = 0x01;break; + case 0x002 : paddr_apb_unqual_dec_19_13 = 0x02;break; + case 0x003 : paddr_apb_unqual_dec_19_13 = 0x03;break; + case 0x004 : paddr_apb_unqual_dec_19_13 = 0x04;break; + case 0x005 : paddr_apb_unqual_dec_19_13 = 0x05;break; + case 0x006 : paddr_apb_unqual_dec_19_13 = 0x06;break; + case 0x007 : paddr_apb_unqual_dec_19_13 = 0x07;break; + case 0x008 : paddr_apb_unqual_dec_19_13 = 0x08;break; + case 0x009 : paddr_apb_unqual_dec_19_13 = 0x09;break; + case 0x00a : paddr_apb_unqual_dec_19_13 = 0x0a;break; + case 0x00b : paddr_apb_unqual_dec_19_13 = 0x0b;break; + case 0x100 : paddr_apb_unqual_dec_19_13 = 0x0c;break; + case 0x101 : paddr_apb_unqual_dec_19_13 = 0x0d;break; + case 0x102 : paddr_apb_unqual_dec_19_13 = 0x0e;break; + case 0x103 : paddr_apb_unqual_dec_19_13 = 0x0f;break; + case 0x104 : paddr_apb_unqual_dec_19_13 = 0x10;break; + case 0x105 : paddr_apb_unqual_dec_19_13 = 0x11;break; + case 0x106 : paddr_apb_unqual_dec_19_13 = 0x12;break; + case 0x107 : paddr_apb_unqual_dec_19_13 = 0x13;break; + case 0x108 : paddr_apb_unqual_dec_19_13 = 0x14;break; + case 0x109 : paddr_apb_unqual_dec_19_13 = 0x15;break; + case 0x10a : paddr_apb_unqual_dec_19_13 = 0x16;break; + case 0x10b : paddr_apb_unqual_dec_19_13 = 0x17;break; + case 0x200 : paddr_apb_unqual_dec_19_13 = 0x18;break; + case 0x201 : paddr_apb_unqual_dec_19_13 = 0x19;break; + case 0x202 : paddr_apb_unqual_dec_19_13 = 0x1a;break; + case 0x203 : paddr_apb_unqual_dec_19_13 = 0x1b;break; + case 0x204 : paddr_apb_unqual_dec_19_13 = 0x1c;break; + case 0x205 : paddr_apb_unqual_dec_19_13 = 0x1d;break; + case 0x206 : paddr_apb_unqual_dec_19_13 = 0x1e;break; + case 0x207 : paddr_apb_unqual_dec_19_13 = 0x1f;break; + case 0x208 : paddr_apb_unqual_dec_19_13 = 0x20;break; + case 0x209 : paddr_apb_unqual_dec_19_13 = 0x21;break; + case 0x20a : paddr_apb_unqual_dec_19_13 = 0x22;break; + case 0x20b : paddr_apb_unqual_dec_19_13 = 0x23;break; + case 0x300 : paddr_apb_unqual_dec_19_13 = 0x24;break; + case 0x301 : paddr_apb_unqual_dec_19_13 = 0x25;break; + case 0x302 : paddr_apb_unqual_dec_19_13 = 0x26;break; + case 0x303 : paddr_apb_unqual_dec_19_13 = 0x27;break; + case 0x304 : paddr_apb_unqual_dec_19_13 = 0x28;break; + case 0x305 : paddr_apb_unqual_dec_19_13 = 0x29;break; + case 0x306 : paddr_apb_unqual_dec_19_13 = 0x2a;break; + case 0x307 : paddr_apb_unqual_dec_19_13 = 0x2b;break; + case 0x308 : paddr_apb_unqual_dec_19_13 = 0x2c;break; + case 0x309 : paddr_apb_unqual_dec_19_13 = 0x2d;break; + case 0x30a : paddr_apb_unqual_dec_19_13 = 0x2e;break; + case 0x30b : paddr_apb_unqual_dec_19_13 = 0x2f;break; + case 0x010 : paddr_apb_unqual_dec_19_13 = 0x30;break; + case 0x011 : paddr_apb_unqual_dec_19_13 = 0x31;break; + case 0x012 : paddr_apb_unqual_dec_19_13 = 0x32;break; + case 0x013 : paddr_apb_unqual_dec_19_13 = 0x33;break; + case 0x014 : paddr_apb_unqual_dec_19_13 = 0x34;break; + case 0x015 : paddr_apb_unqual_dec_19_13 = 0x35;break; + case 0x016 : paddr_apb_unqual_dec_19_13 = 0x36;break; + case 0x017 : paddr_apb_unqual_dec_19_13 = 0x37;break; + case 0x018 : paddr_apb_unqual_dec_19_13 = 0x38;break; + case 0x019 : paddr_apb_unqual_dec_19_13 = 0x39;break; + case 0x110 : paddr_apb_unqual_dec_19_13 = 0x3a;break; + case 0x111 : paddr_apb_unqual_dec_19_13 = 0x3b;break; + case 0x112 : paddr_apb_unqual_dec_19_13 = 0x3c;break; + case 0x113 : paddr_apb_unqual_dec_19_13 = 0x3d;break; + case 0x114 : paddr_apb_unqual_dec_19_13 = 0x3e;break; + case 0x115 : paddr_apb_unqual_dec_19_13 = 0x3f;break; + case 0x116 : paddr_apb_unqual_dec_19_13 = 0x40;break; + case 0x117 : paddr_apb_unqual_dec_19_13 = 0x41;break; + case 0x118 : paddr_apb_unqual_dec_19_13 = 0x42;break; + case 0x119 : paddr_apb_unqual_dec_19_13 = 0x43;break; + case 0x210 : paddr_apb_unqual_dec_19_13 = 0x44;break; + case 0x211 : paddr_apb_unqual_dec_19_13 = 0x45;break; + case 0x212 : paddr_apb_unqual_dec_19_13 = 0x46;break; + case 0x213 : paddr_apb_unqual_dec_19_13 = 0x47;break; + case 0x214 : paddr_apb_unqual_dec_19_13 = 0x48;break; + case 0x215 : paddr_apb_unqual_dec_19_13 = 0x49;break; + case 0x216 : paddr_apb_unqual_dec_19_13 = 0x4a;break; + case 0x217 : paddr_apb_unqual_dec_19_13 = 0x4b;break; + case 0x218 : paddr_apb_unqual_dec_19_13 = 0x4c;break; + case 0x219 : paddr_apb_unqual_dec_19_13 = 0x4d;break; + case 0x310 : paddr_apb_unqual_dec_19_13 = 0x4e;break; + case 0x311 : paddr_apb_unqual_dec_19_13 = 0x4f;break; + case 0x312 : paddr_apb_unqual_dec_19_13 = 0x50;break; + case 0x313 : paddr_apb_unqual_dec_19_13 = 0x51;break; + case 0x314 : paddr_apb_unqual_dec_19_13 = 0x52;break; + case 0x315 : paddr_apb_unqual_dec_19_13 = 0x53;break; + case 0x316 : paddr_apb_unqual_dec_19_13 = 0x54;break; + case 0x317 : paddr_apb_unqual_dec_19_13 = 0x55;break; + case 0x318 : paddr_apb_unqual_dec_19_13 = 0x56;break; + case 0x319 : paddr_apb_unqual_dec_19_13 = 0x57;break; + case 0x020 : paddr_apb_unqual_dec_19_13 = 0x58;break; + case 0x120 : paddr_apb_unqual_dec_19_13 = 0x59;break; + case 0x220 : paddr_apb_unqual_dec_19_13 = 0x5a;break; + case 0x320 : paddr_apb_unqual_dec_19_13 = 0x5b;break; + case 0x040 : paddr_apb_unqual_dec_19_13 = 0x5c;break; + case 0x140 : paddr_apb_unqual_dec_19_13 = 0x5d;break; + case 0x240 : paddr_apb_unqual_dec_19_13 = 0x5e;break; + case 0x340 : paddr_apb_unqual_dec_19_13 = 0x5f;break; + case 0x050 : paddr_apb_unqual_dec_19_13 = 0x60;break; + case 0x051 : paddr_apb_unqual_dec_19_13 = 0x61;break; + case 0x052 : paddr_apb_unqual_dec_19_13 = 0x62;break; + case 0x053 : paddr_apb_unqual_dec_19_13 = 0x63;break; + case 0x054 : paddr_apb_unqual_dec_19_13 = 0x64;break; + case 0x055 : paddr_apb_unqual_dec_19_13 = 0x65;break; + case 0x056 : paddr_apb_unqual_dec_19_13 = 0x66;break; + case 0x057 : paddr_apb_unqual_dec_19_13 = 0x67;break; + case 0x070 : paddr_apb_unqual_dec_19_13 = 0x68;break; + case 0x090 : paddr_apb_unqual_dec_19_13 = 0x69;break; + case 0x190 : paddr_apb_unqual_dec_19_13 = 0x6a;break; + case 0x290 : paddr_apb_unqual_dec_19_13 = 0x6b;break; + case 0x390 : paddr_apb_unqual_dec_19_13 = 0x6c;break; + case 0x0c0 : paddr_apb_unqual_dec_19_13 = 0x6d;break; + case 0x0d0 : paddr_apb_unqual_dec_19_13 = 0x6e;break; + default : paddr_apb_unqual_dec_19_13 = 0x00; + } + + paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1)); + + paddr_apb_phy = (paddr_apb_unqual << 1); + + return paddr_apb_phy; +} diff --git a/drivers/ddr/imx/phy/Kconfig b/drivers/ddr/imx/phy/Kconfig new file mode 100644 index 0000000000..d3e589b23c --- /dev/null +++ b/drivers/ddr/imx/phy/Kconfig @@ -0,0 +1,4 @@ +config IMX_SNPS_DDR_PHY + bool "i.MX Snopsys DDR PHY" + help + Select the DDR PHY driver support on i.MX8M and i.MX9 SOC. diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile new file mode 100644 index 0000000000..bb3d4ee5b7 --- /dev/null +++ b/drivers/ddr/imx/phy/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +endif diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c index 67dd4e7059..67dd4e7059 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_csr.c +++ b/drivers/ddr/imx/phy/ddrphy_csr.c diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c index 08fed6178f..cd905f952c 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -7,7 +7,6 @@ #include <log.h> #include <linux/kernel.h> #include <asm/arch/ddr.h> -#include <asm/arch/lpddr4_define.h> #include <asm/arch/sys_proto.h> int ddr_cfg_phy(struct dram_timing_info *dram_timing) diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c new file mode 100644 index 0000000000..b852c870f9 --- /dev/null +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/sys_proto.h> + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_receive(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034)); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +int wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + debug("Training PASS\n"); + return 0; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + return -1; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; + case 3733: + dram_pll_init(MHZ(933)); + dram_disable_bypass(); + break; + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2800: + dram_pll_init(MHZ(700)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1866: + dram_pll_init(MHZ(466)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 1066: + dram_pll_init(MHZ(266)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 333: + dram_enable_bypass(MHZ(333)); + break; + case 200: + dram_enable_bypass(MHZ(200)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/phy/helper.c index f23904bf71..43b40a8029 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm/arch/ddr.h> #include <asm/arch/ddr.h> -#include <asm/arch/lpddr4_define.h> #include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,43 +45,43 @@ void ddr_load_train_firmware(enum fw_type type) dmem_start = imem_start + IMEM_LEN; pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + pr_to32 = IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; + writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; + writew((tmp32 >> 16) & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; pr_from32 += 4; i += 4; } pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + pr_to32 = DMEM_OFFSET_ADDR; for (i = 0x0; i < DMEM_LEN; ) { tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; + writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; + writew((tmp32 >> 16) & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; pr_from32 += 4; i += 4; } debug("check ddr_pmu_train_imem code\n"); pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + pr_to32 = IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); + pr_to32 += 1; + tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16); if (tmp32 != readl(pr_from32)) { debug("%lx %lx\n", pr_from32, pr_to32); error++; } pr_from32 += 4; - pr_to32 += 4; + pr_to32 += 1; i += 4; } if (error) @@ -92,17 +91,17 @@ void ddr_load_train_firmware(enum fw_type type) debug("check ddr4_pmu_train_dmem code\n"); pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + pr_to32 = DMEM_OFFSET_ADDR; for (i = 0x0; i < DMEM_LEN;) { - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); + pr_to32 += 1; + tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16); if (tmp32 != readl(pr_from32)) { debug("%lx %lx\n", pr_from32, pr_to32); error++; } pr_from32 += 4; - pr_to32 += 4; + pr_to32 += 1; i += 4; } diff --git a/drivers/fastboot/fb_fsl/fb_fsl_command.c b/drivers/fastboot/fb_fsl/fb_fsl_command.c index 11224728a8..61b1a9d580 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_command.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_command.c @@ -472,6 +472,16 @@ static bool endswith(char* s, char* subs) { return true; } +static bool erase_uboot_env(void) { + FbLockState status; + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + printf("can not erase env when device is in locked state\n"); + return false; + } else + return env_erase() ? false : true; +} + static void flashing(char *cmd, char *response) { FbLockState status; @@ -726,7 +736,14 @@ static void flashing(char *cmd, char *response) } #endif /* !CONFIG_AVB_ATX */ #endif /* CONFIG_IMX_TRUSTY_OS */ - else if (endswith(cmd, "unlock_critical")) { + else if (endswith(cmd, ERASE_UBOOT_ENV)) { + if(erase_uboot_env()) + strcpy(response, "OKAY"); + else { + printf("ERROR erase uboot environment variable failed!"); + strcpy(response, "FAILerase uboot environment variable failed!"); + } + } else if (endswith(cmd, "unlock_critical")) { strcpy(response, "OKAY"); } else if (endswith(cmd, "unlock")) { printf("flashing unlock.\n"); diff --git a/drivers/fastboot/fb_fsl/fb_fsl_common.c b/drivers/fastboot/fb_fsl/fb_fsl_common.c index 6841e3e945..47e2974daa 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_common.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_common.c @@ -210,6 +210,9 @@ void board_fastboot_setup(void) } else if (is_imx8ulp()) { if (!env_get("soc_type")) env_set("soc_type", "imx8ulp"); + } else if (is_imx93()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx93"); } } diff --git a/drivers/fastboot/fb_fsl/fb_fsl_getvar.c b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c index 6970904528..ec96911c0b 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_getvar.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c @@ -118,7 +118,7 @@ static bool is_slotvar(char *cmd) return false; } -#ifdef CONFIG_SERIAL_TAG +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) static char serial[IMX_SERIAL_LEN]; #endif diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c index 4f930ac19c..a43c70db93 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c @@ -62,7 +62,7 @@ static ulong bootloader_mmc_offset(void) else /* target device is SD card, bootloader offset is 0x8000 */ return 0x8000; - } else if (is_imx8mn() || is_imx8mp() || is_imx8dxl() || is_imx8ulp()) { + } else if (is_imx8mn() || is_imx8mp() || is_imx8dxl() || is_imx8ulp() || is_imx93()) { /* target device is eMMC boot0 partition, bootloader offset is 0x0 */ if (env_get_ulong("emmc_dev", 10, 2) == fastboot_devinfo.dev_id) return 0; @@ -118,16 +118,16 @@ static int _fastboot_parts_add_ptable_entry(int ptable_index, !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_A) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_A) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_B) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B)) #else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE)) #endif - !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) - strcpy(ptable[ptable_index].fstype, "ext4"); + strcpy(ptable[ptable_index].fstype, "erofs"); + else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) + strcpy(ptable[ptable_index].fstype, "f2fs"); else strcpy(ptable[ptable_index].fstype, "raw"); return 0; diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 7695b03509..78e16d9170 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -94,6 +94,10 @@ static int scmi_bind_protocols(struct udevice *dev) if (IS_ENABLED(CONFIG_POWER_DOMAIN)) drv = DM_DRIVER_GET(scmi_power_domain); break; + case SCMI_PROTOCOL_ID_SENSOR: + if (IS_ENABLED(CONFIG_DM_THERMAL)) + drv = DM_DRIVER_GET(scmi_thermal); + break; default: break; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 522dfc195e..d93d3eded1 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -57,6 +57,15 @@ config GPIO_HOG is a mechanism providing automatic GPIO request and config- uration as part of the gpio-controller's driver probe function. +config SPL_GPIO_HOG + bool "Enable GPIO hog support in SPL" + depends on SPL_GPIO + help + Enable gpio hog support in SPL + The GPIO chip may contain GPIO hog definitions. GPIO hogging + is a mechanism providing automatic GPIO request and config- + uration as part of the gpio-controller's driver probe function. + config DM_GPIO_LOOKUP_LABEL bool "Enable searching for gpio labelnames" depends on DM_GPIO @@ -247,6 +256,12 @@ config MXS_GPIO help Support GPIO controllers on i.MX23 and i.MX28 platforms +config ADP5585_GPIO + bool "ADP5585 GPIO driver" + depends on DM_GPIO && DM_I2C + help + Support ADP5585 GPIO expander on i.MX93 platform + config OMAP_GPIO bool "TI OMAP GPIO driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 33f7d41b7d..8ce13ecb78 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -68,7 +68,4 @@ obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o -obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o -obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o -obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o -obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o +obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c new file mode 100644 index 0000000000..69ad9ea40d --- /dev/null +++ b/drivers/gpio/adp5585_gpio.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * ADP5585 I/O Expander Controller + * + * Author: Alice Guo (alice.guo@nxp.com) + */ + +#include <asm/gpio.h> +#include <dm.h> +#include <dt-bindings/gpio/gpio.h> +#include <i2c.h> + +#define ADP5585_ID 0x00 +#define ADP5585_INT_STATUS 0x01 +#define ADP5585_STATUS 0x02 +#define ADP5585_FIFO_1 0x03 +#define ADP5585_FIFO_2 0x04 +#define ADP5585_FIFO_3 0x05 +#define ADP5585_FIFO_4 0x06 +#define ADP5585_FIFO_5 0x07 +#define ADP5585_FIFO_6 0x08 +#define ADP5585_FIFO_7 0x09 +#define ADP5585_FIFO_8 0x0A +#define ADP5585_FIFO_9 0x0B +#define ADP5585_FIFO_10 0x0C +#define ADP5585_FIFO_11 0x0D +#define ADP5585_FIFO_12 0x0E +#define ADP5585_FIFO_13 0x0F +#define ADP5585_FIFO_14 0x10 +#define ADP5585_FIFO_15 0x11 +#define ADP5585_FIFO_16 0x12 +#define ADP5585_GPI_INT_STAT_A 0x13 +#define ADP5585_GPI_INT_STAT_B 0x14 +#define ADP5585_GPI_STATUS_A 0x15 +#define ADP5585_GPI_STATUS_B 0x16 +#define ADP5585_RPULL_CONFIG_A 0x17 +#define ADP5585_RPULL_CONFIG_B 0x18 +#define ADP5585_RPULL_CONFIG_C 0x19 +#define ADP5585_RPULL_CONFIG_D 0x1A +#define ADP5585_GPI_INT_LEVEL_A 0x1B +#define ADP5585_GPI_INT_LEVEL_B 0x1C +#define ADP5585_GPI_EVENT_EN_A 0x1D +#define ADP5585_GPI_EVENT_EN_B 0x1E +#define ADP5585_GPI_INTERRUPT_EN_A 0x1F +#define ADP5585_GPI_INTERRUPT_EN_B 0x20 +#define ADP5585_DEBOUNCE_DIS_A 0x21 +#define ADP5585_DEBOUNCE_DIS_B 0x22 +#define ADP5585_GPO_DATA_OUT_A 0x23 +#define ADP5585_GPO_DATA_OUT_B 0x24 +#define ADP5585_GPO_OUT_MODE_A 0x25 +#define ADP5585_GPO_OUT_MODE_B 0x26 +#define ADP5585_GPIO_DIRECTION_A 0x27 +#define ADP5585_GPIO_DIRECTION_B 0x28 +#define ADP5585_RESET1_EVENT_A 0x29 +#define ADP5585_RESET1_EVENT_B 0x2A +#define ADP5585_RESET1_EVENT_C 0x2B +#define ADP5585_RESET2_EVENT_A 0x2C +#define ADP5585_RESET2_EVENT_B 0x2D +#define ADP5585_RESET_CFG 0x2E +#define ADP5585_PWM_OFFT_LOW 0x2F +#define ADP5585_PWM_OFFT_HIGH 0x30 +#define ADP5585_PWM_ONT_LOW 0x31 +#define ADP5585_PWM_ONT_HIGH 0x32 +#define ADP5585_PWM_CFG 0x33 +#define ADP5585_LOGIC_CFG 0x34 +#define ADP5585_LOGIC_FF_CFG 0x35 +#define ADP5585_LOGIC_INT_EVENT_EN 0x36 +#define ADP5585_POLL_PTIME_CFG 0x37 +#define ADP5585_PIN_CONFIG_A 0x38 +#define ADP5585_PIN_CONFIG_B 0x39 +#define ADP5585_PIN_CONFIG_D 0x3A +#define ADP5585_GENERAL_CFG 0x3B +#define ADP5585_INT_EN 0x3C + +#define ADP5585_MAXGPIO 10 +#define ADP5585_BANK(offs) ((offs) > 4) +#define ADP5585_BIT(offs) (offs > 4 ? \ + 1u << (offs - 5) : 1u << (offs)) + +struct adp5585_plat { + fdt_addr_t addr; + uint8_t id; + uint8_t dat_out[2]; + uint8_t dir[2]; +}; + +static int adp5585_direction_input(struct udevice *dev, unsigned offset) +{ + int ret; + unsigned bank; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + + plat->dir[bank] &= ~ADP5585_BIT(offset); + ret = dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1); + + return ret; +} + +static int adp5585_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + int ret; + unsigned bank, bit; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + + plat->dir[bank] |= bit; + + if (value) + plat->dat_out[bank] |= bit; + else + plat->dat_out[bank] &= ~bit; + + ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1); + ret |= dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1); + + return ret; +} + +static int adp5585_get_value(struct udevice *dev, unsigned offset) +{ + struct adp5585_plat *plat = dev_get_plat(dev); + unsigned bank = ADP5585_BANK(offset); + unsigned bit = ADP5585_BIT(offset); + uint8_t val; + + if (plat->dir[bank] & bit) + val = plat->dat_out[bank]; + else + dm_i2c_read(dev, ADP5585_GPI_STATUS_A + bank, &val, 1); + + return !!(val & bit); +} + +static int adp5585_set_value(struct udevice *dev, unsigned offset, int value) +{ + int ret; + unsigned bank, bit; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + + if (value) + plat->dat_out[bank] |= bit; + else + plat->dat_out[bank] &= ~bit; + + ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1); + + return ret; +} + +static int adp5585_get_function(struct udevice *dev, unsigned offset) +{ + unsigned bank, bit, dir; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + dir = plat->dir[bank] & bit; + + if (!dir) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static int adp5585_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static const struct dm_gpio_ops adp5585_ops = { + .direction_input = adp5585_direction_input, + .direction_output = adp5585_direction_output, + .get_value = adp5585_get_value, + .set_value = adp5585_set_value, + .get_function = adp5585_get_function, + .xlate = adp5585_xlate, +}; + +static int adp5585_probe(struct udevice *dev) +{ + struct adp5585_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int ret; + + if (!plat) + return 0; + + plat->addr = dev_read_addr(dev); + if (plat->addr == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = dm_i2c_read(dev, ADP5585_ID, &plat->id, 1); + if (ret < 0) + return ret; + + uc_priv->gpio_count = ADP5585_MAXGPIO; + uc_priv->bank_name = "adp5585-gpio"; + + for(int i = 0; i < 2; i++) { + ret = dm_i2c_read(dev, ADP5585_GPO_DATA_OUT_A + i, &plat->dat_out[i], 1); + if (ret) + return ret; + + ret = dm_i2c_read(dev, ADP5585_GPIO_DIRECTION_A + i, &plat->dir[i], 1); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id adp5585_ids[] = { + { .compatible = "adp5585" }, + { } +}; + +U_BOOT_DRIVER(adp5585) = { + .name = "adp5585", + .id = UCLASS_GPIO, + .of_match = adp5585_ids, + .probe = adp5585_probe, + .ops = &adp5585_ops, + .plat_auto = sizeof(struct adp5585_plat), +}; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 125ae53d61..9075c7235d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1432,9 +1432,6 @@ void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc) static int gpio_post_bind(struct udevice *dev) { - struct udevice *child; - ofnode node; - #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev); static int reloc_done; @@ -1465,7 +1462,10 @@ static int gpio_post_bind(struct udevice *dev) } #endif - if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) { + if (CONFIG_IS_ENABLED(GPIO_HOG)) { + struct udevice *child; + ofnode node; + dev_for_each_subnode(node, dev) { if (ofnode_read_bool(node, "gpio-hog")) { const char *name = ofnode_get_name(node); diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index dc8911a8eb..acbfdfd57d 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -37,6 +37,8 @@ #define PCA_GPIO_MASK 0x00FF #define PCA_INT 0x0100 +#define PCA_PCAL BIT(9) +#define PCA_LATCH_INT (PCA_PCAL | PCA_INT) #define PCA953X_TYPE 0x1000 #define PCA957X_TYPE 0x2000 #define PCA_TYPE_MASK 0xF000 @@ -363,6 +365,8 @@ static const struct udevice_id pca953x_ids[] = { { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, + { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, + { .compatible = "maxim,max7310", .data = OF_953X(8, 0), }, { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 961a6b567d..9a652445aa 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -283,7 +283,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) bool mode; int i; - if (IS_ENABLED(CONFIG_CLK)) { + if (CONFIG_IS_ENABLED(CLK)) { clock_rate = clk_get_rate(&i2c_bus->per_clk); if (clock_rate <= 0) { dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate); @@ -463,7 +463,7 @@ static int imx_lpi2c_probe(struct udevice *bus) return ret; } - if (IS_ENABLED(CONFIG_CLK)) { + if (CONFIG_IS_ENABLED(CLK)) { ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk); if (ret) { dev_err(bus, "Failed to get per clk\n"); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6fcdb3bbb8..c4ae6f7d80 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -249,6 +249,13 @@ config IMX_M4_MU If you say Y here to enable Message Unit driver to work with Cortex M4 core on AMP Freescale i.MX processors. +config IMX_SENTINEL + bool "Enable i.MX Sentinel MU driver and API" + depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) + help + If you say Y here to enable Message Unit driver to work with + Sentinel core on some NXP i.MX processors. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0f4b7ec879..29a1d6762f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ -obj-$(CONFIG_IMX8ULP) += imx8ulp/ +obj-$(CONFIG_IMX_SENTINEL) += sentinel/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c deleted file mode 100644 index 18222f3ab2..0000000000 --- a/drivers/misc/imx8ulp/s400_api.c +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020 NXP - * - */ - -#include <common.h> -#include <hang.h> -#include <malloc.h> -#include <asm/io.h> -#include <dm.h> -#include <asm/arch/s400_api.h> -#include <misc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; - if (xrdc) - msg.data[0] = (0x78 << 8) | core_id; - else - msg.data[0] = (0x74 << 8) | core_id; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, core id %u, response 0x%x\n", - __func__, ret, core_id, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 3; - msg.command = AHAB_AUTH_OEM_CTNR_CID; - msg.data[0] = upper_32_bits(ctnr_addr); - msg.data[1] = lower_32_bits(ctnr_addr); - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n", - __func__, ret, ctnr_addr, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_release_container(u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 1; - msg.command = AHAB_RELEASE_CTNR_CID; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, response 0x%x\n", - __func__, ret, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_verify_image(u32 img_id, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_VERIFY_IMG_CID; - msg.data[0] = 1 << img_id; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, img_id %u, response 0x%x\n", - __func__, ret, img_id, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_forward_lifecycle(u16 life_cycle, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID; - msg.data[0] = life_cycle; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n", - __func__, ret, life_cycle, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - if (!fuse_words) { - printf("Invalid parameters for fuse read\n"); - return -EINVAL; - } - - if ((fuse_id != 1 && fuse_num != 1) || - (fuse_id == 1 && fuse_num != 4)) { - printf("Invalid fuse number parameter\n"); - return -EINVAL; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_READ_FUSE_REQ_CID; - msg.data[0] = fuse_id; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", - __func__, ret, fuse_id, msg.data[0]); - - if (response) - *response = msg.data[0]; - - fuse_words[0] = msg.data[1]; - if (fuse_id == 1) { - /* OTP_UNIQ_ID */ - fuse_words[1] = msg.data[2]; - fuse_words[2] = msg.data[3]; - fuse_words[3] = msg.data[4]; - } - - return ret; -} - -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 3; - msg.command = AHAB_WRITE_FUSE_REQ_CID; - msg.data[0] = (32 << 16) | (fuse_id << 5); - if (lock) - msg.data[0] |= (1 << 31); - - msg.data[1] = fuse_val; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", - __func__, ret, fuse_id, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_release_caam(u32 core_did, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_CAAM_RELEASE_CID; - msg.data[0] = core_did; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, response 0x%x\n", - __func__, ret, msg.data[0]); - - if (response) - *response = msg.data[0]; - - return ret; -} - -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - if (!fw_version) { - printf("Invalid parameters for f/w version read\n"); - return -EINVAL; - } - - if (!sha1) { - printf("Invalid parameters for commit sha1\n"); - return -EINVAL; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 1; - msg.command = AHAB_GET_FW_VERSION_CID; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) - printf("Error: %s: ret %d, response 0x%x\n", - __func__, ret, msg.data[0]); - - if (response) - *response = msg.data[0]; - - *fw_version = msg.data[1]; - *sha1 = msg.data[2]; - - return ret; -} - -int ahab_dump_buffer(u32 *buffer, u32 buffer_length) -{ - struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; - int ret, i = 0; - - if (!dev) { - printf("s400 dev is not initialized\n"); - return -ENODEV; - } - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 1; - msg.command = AHAB_LOG_CID; - - ret = misc_call(dev, false, &msg, size, &msg, size); - if (ret) { - printf("Error: %s: ret %d, response 0x%x\n", - __func__, ret, msg.data[0]); - - return ret; - } - - if (buffer){ - buffer[i++] = *(u32 *)&msg; /* Need dump the response header */ - for (; i < buffer_length && i < msg.size; i++) { - buffer[i] = msg.data[i - 1]; - } - } - - return i; -} diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/sentinel/Makefile index 927cc55216..446154cb20 100644 --- a/drivers/misc/imx8ulp/Makefile +++ b/drivers/misc/sentinel/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += s400_api.o imx8ulp_mu.o +obj-y += s400_api.o s4mu.o obj-$(CONFIG_CMD_FUSE) += fuse.o diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c index 090e702d9f..e2b6875766 100644 --- a/drivers/misc/imx8ulp/fuse.c +++ b/drivers/misc/sentinel/fuse.c @@ -10,7 +10,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/imx-regs.h> #include <env.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,6 +31,9 @@ struct s400_map_entry { u32 s400_index; }; +#if defined(CONFIG_IMX8ULP) +#define FSB_OTP_SHADOW 0x800 + struct fsb_map_entry fsb_mapping_table[] = { { 3, 8 }, { 4, 8 }, @@ -65,6 +68,53 @@ struct s400_map_entry s400_api_mapping_table[] = { { 23, 1, 4, 2 }, /* OTFAD */ { 25, 8 }, /* Test config2 */ }; +#elif defined(CONFIG_ARCH_IMX9) +#define FSB_OTP_SHADOW 0x8000 + +struct fsb_map_entry fsb_mapping_table[] = { + { 0, 8 }, + { 1, 8 }, + { 2, 8 }, + { 3, 8 }, + { 4, 8 }, + { 5, 8 }, + { 6, 4 }, + { -1, 260 }, + { 39, 8 }, + { 40, 8 }, + { 41, 8 }, + { 42, 8 }, + { 43, 8 }, + { 44, 8 }, + { 45, 8 }, + { 46, 8 }, + { 47, 8 }, + { 48, 8 }, + { 49, 8 }, + { 50, 8 }, + { 51, 8 }, + { 52, 8 }, + { 53, 8 }, + { 54, 8 }, + { 55, 8 }, + { 56, 8 }, + { 57, 8 }, + { 58, 8 }, + { 59, 8 }, + { 60, 8 }, + { 61, 8 }, + { 62, 8 }, + { 63, 8 }, +}; + +struct s400_map_entry s400_api_mapping_table[] = { + { 7, 1, 7, 63 }, + { 16, 8, }, + { 17, 8, }, + { 22, 1, 6 }, + { 23, 1, 4 }, +}; +#endif static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) { @@ -74,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) /* map the fuse from ocotp fuse map to FSB*/ for (i = 0; i < size; i++) { if (fsb_mapping_table[i].fuse_bank != -1 && - fsb_mapping_table[i].fuse_bank == bank) { + fsb_mapping_table[i].fuse_bank == bank && + fsb_mapping_table[i].fuse_words > word) { break; } @@ -118,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word) return s400_api_mapping_table[i].fuse_bank * 8 + word; } +#if defined(CONFIG_IMX8ULP) int fuse_sense(u32 bank, u32 word, u32 *val) { s32 word_index; @@ -128,7 +180,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) word_index = map_fsb_fuse_index(bank, word, &redundancy); if (word_index >= 0) { - *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2)); + *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); if (redundancy) *val = (*val >> ((word % 2) * 16)) & 0xFFFF; @@ -170,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val) return -ENOENT; } +#elif defined(CONFIG_ARCH_IMX9) +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + s32 word_index; + bool redundancy; + + if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) + return -EINVAL; + + word_index = map_fsb_fuse_index(bank, word, &redundancy); + if (word_index >= 0) { + *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); + if (redundancy) + *val = (*val >> ((word % 2) * 16)) & 0xFFFF; + + return 0; + } + + word_index = map_s400_fuse_index(bank, word); + if (word_index >= 0) { + u32 data; + u32 res, size = 1; + int ret; + + ret = ahab_read_common_fuse(word_index, &data, size, &res); + if (ret) { + printf("ahab read fuse failed %d, 0x%x\n", ret, res); + return ret; + } + + *val = data; + + return 0; + } + + return -ENOENT; +} +#endif int fuse_read(u32 bank, u32 word, u32 *val) { diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c new file mode 100644 index 0000000000..baab9b2c9b --- /dev/null +++ b/drivers/misc/sentinel/s400_api.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, 2022 NXP + * + */ + +#include <common.h> +#include <hang.h> +#include <malloc.h> +#include <asm/io.h> +#include <dm.h> +#include <asm/mach-imx/s400_api.h> +#include <misc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static uint32_t compute_crc(const struct sentinel_msg *msg) +{ + u32 crc = 0; + size_t i = 0; + u32 *data = (u32 *)msg; + + for (i = 0; i < (msg->size - 1); i++) + crc ^= data[i]; + + return crc; +} + +int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_RELEASE_RDC_REQ; + switch (xrdc) { + case 0: + msg.data[0] = (0x74 << 8) | core_id; + break; + case 1: + msg.data[0] = (0x78 << 8) | core_id; + break; + case 2: + msg.data[0] = (0x82 << 8) | core_id; + break; + case 3: + msg.data[0] = (0x86 << 8) | core_id; + break; + default: + printf("Error: wrong xrdc index %u\n", xrdc); + return -EINVAL; + } + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, core id %u, response 0x%x\n", + __func__, ret, core_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = ELE_OEM_CNTN_AUTH_REQ; + msg.data[0] = upper_32_bits(ctnr_addr); + msg.data[1] = lower_32_bits(ctnr_addr); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n", + __func__, ret, ctnr_addr, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_release_container(u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_RELEASE_CONTAINER_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_verify_image(u32 img_id, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_VERIFY_IMAGE_REQ; + msg.data[0] = 1 << img_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, img_id %u, response 0x%x\n", + __func__, ret, img_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_forward_lifecycle(u16 life_cycle, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_FWD_LIFECYCLE_UP_REQ; + msg.data[0] = life_cycle; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n", + __func__, ret, life_cycle, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!fuse_words) { + printf("Invalid parameters for fuse read\n"); + return -EINVAL; + } + + if ((fuse_id != 1 && fuse_num != 1) || + (fuse_id == 1 && fuse_num != 4)) { + printf("Invalid fuse number parameter\n"); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_READ_FUSE_REQ; + msg.data[0] = fuse_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + fuse_words[0] = msg.data[1]; + if (fuse_id == 1) { + /* OTP_UNIQ_ID */ + fuse_words[1] = msg.data[2]; + fuse_words[2] = msg.data[3]; + fuse_words[3] = msg.data[4]; + } + + return ret; +} + +int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_FUSE_REQ; + msg.data[0] = (32 << 16) | (fuse_id << 5); + if (lock) + msg.data[0] |= (1 << 31); + + msg.data[1] = fuse_val; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_release_caam(u32 core_did, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_RELEASE_CAAM_REQ; + msg.data[0] = core_did; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!fw_version) { + printf("Invalid parameters for f/w version read\n"); + return -EINVAL; + } + + if (!sha1) { + printf("Invalid parameters for commit sha1\n"); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_FW_VERSION_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + *fw_version = msg.data[1]; + *sha1 = msg.data[2]; + + return ret; +} + +int ahab_dump_buffer(u32 *buffer, u32 buffer_length) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret, i = 0; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_DUMP_DEBUG_BUFFER_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) { + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; + } + + if (buffer){ + buffer[i++] = *(u32 *)&msg; /* Need dump the response header */ + for (; i < buffer_length && i < msg.size; i++) { + buffer[i] = msg.data[i - 1]; + } + } + + return i; +} + +int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 4; + msg.command = ELE_GET_INFO_REQ; + msg.data[0] = upper_32_bits((ulong)info); + msg.data[1] = lower_32_bits((ulong)info); + msg.data[2] = sizeof(struct sentinel_get_info_data); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_get_fw_status(u32 *status, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_FW_STATUS_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + *status = msg.data[1] & 0xF; + + return ret; +} + +int ahab_release_m33_trout(void) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_ENABLE_RTC_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} + +int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret, i = 0; + u32 actual_events; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!events || !events_cnt || *events_cnt == 0) { + printf("Invalid parameters for %s\n", __func__); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_EVENTS_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + if (!ret) { + actual_events = msg.data[1] & 0xffff; + if (*events_cnt < actual_events) + actual_events = *events_cnt; + + for (; i < actual_events; i++) + events[i] = msg.data[i + 2]; + + *events_cnt = actual_events; + } + + return ret; +} + +int ahab_start_rng(void) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_START_RNG; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} + +int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, + u32 max_output_size) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 8; + msg.command = ELE_GENERATE_DEK_BLOB; + msg.data[0] = key_id; + msg.data[1] = 0x0; + msg.data[2] = src_paddr; + msg.data[3] = 0x0; + msg.data[4] = dst_paddr; + msg.data[5] = max_output_size; + msg.data[6] = compute_crc(&msg); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret 0x%x, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} + +int ahab_write_secure_fuse(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SECURE_FUSE_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +} diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/sentinel/s4mu.c index 6daad478f1..535eb33265 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/sentinel/s4mu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020 NXP + * Copyright 2020-2022 NXP */ #include <common.h> @@ -9,7 +9,7 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/device-internal.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/imx-regs.h> #include <linux/iopoll.h> #include <misc.h> @@ -22,7 +22,7 @@ struct imx8ulp_mu { #define MU_SR_TE0_MASK BIT(0) #define MU_SR_RF0_MASK BIT(0) -#define MU_TR_COUNT 4 +#define MU_TR_COUNT 8 #define MU_RR_COUNT 4 void mu_hal_init(ulong base) @@ -66,7 +66,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) int ret; u32 count = 10; - assert(reg_index < MU_TR_COUNT); + assert(reg_index < MU_RR_COUNT); debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr)); @@ -95,7 +95,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) static int imx8ulp_mu_read(struct mu_type *base, void *data) { - struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + struct sentinel_msg *msg = (struct sentinel_msg *)data; int ret; u8 count = 0; @@ -128,7 +128,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data) static int imx8ulp_mu_write(struct mu_type *base, void *data) { - struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + struct sentinel_msg *msg = (struct sentinel_msg *)data; int ret; u8 count = 0; @@ -181,7 +181,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, return ret; } - result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; + result = ((struct sentinel_msg *)rx_msg)->data[0]; if ((result & 0xff) == 0xd6) return 0; @@ -229,6 +229,7 @@ static struct misc_ops imx8ulp_mu_ops = { static const struct udevice_id imx8ulp_mu_ids[] = { { .compatible = "fsl,imx8ulp-mu" }, + { .compatible = "fsl,imx93-mu-s4" }, { } }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0ef89c5e3f..5aca78f25b 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -842,7 +842,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4af99a3a40..715e3f0b97 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3083,10 +3083,11 @@ int mmc_init_device(int num) } m = mmc_get_mmc_dev(dev); - m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ - if (!m) return 0; + + m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ + if (m->preinit) mmc_start_init(m); diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7524337746..86a1c4c81b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -136,6 +136,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 71e0cbafb4..ae7e2fe5be 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -334,7 +334,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || VF610 + depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX93 || VF610 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 8059996c7e..baea2a0799 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -49,7 +49,7 @@ #include <asm/gpio.h> #include <asm/io.h> #include <eth_phy.h> -#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) +#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX93) #include <asm/arch/clock.h> #include <asm/mach-imx/sys_proto.h> #endif @@ -759,6 +759,14 @@ static int eqos_stop_resets_tegra186(struct udevice *dev) return 0; } +static int eqos_start_resets_imx(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + writel(EQOS_DMA_MODE_SWR, &eqos->dma_regs->mode); + return 0; +} + static int eqos_calibrate_pads_tegra186(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1096,7 +1104,7 @@ static int eqos_read_rom_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); -#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) +#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX93) imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr); #endif return !is_valid_ethaddr(pdata->enetaddr); @@ -1937,9 +1945,10 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) static int eqos_remove_resources_stm32(struct udevice *dev) { -#ifdef CONFIG_CLK struct eqos_priv *eqos = dev_get_priv(dev); +#ifdef CONFIG_CLK + debug("%s(dev=%p):\n", __func__, dev); clk_free(&eqos->clk_tx); @@ -2150,7 +2159,7 @@ static struct eqos_ops eqos_imx_ops = { .eqos_probe_resources = eqos_probe_resources_imx, .eqos_remove_resources = eqos_remove_resources_imx, .eqos_stop_resets = eqos_null_ops, - .eqos_start_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_imx, .eqos_stop_clks = eqos_stop_clks_imx, .eqos_start_clks = eqos_start_clks_imx, .eqos_calibrate_pads = eqos_null_ops, diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index f09523b631..b67569b7cd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -630,7 +630,8 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() && + !is_imx93()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); @@ -883,6 +884,9 @@ static int fec_recv(struct eth_device *dev) ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); #endif + if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN)) + return 0; + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); @@ -1647,6 +1651,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx7d-fec" }, { .compatible = "fsl,mvf600-fec" }, { .compatible = "fsl,imx8qm-fec" }, + { .compatible = "fsl,imx93-fec" }, { } }; diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index 6669048181..e586dcf55d 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -172,7 +172,7 @@ static int pfe_fit_check(void) int pfe_spi_flash_init(void) { struct spi_flash *pfe_flash; - struct udevice *new; + struct udevice *new = NULL; int ret = 0; void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH); diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 24c3ea59bb..e3e2606275 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -457,6 +457,20 @@ static struct phy_driver RTL8211F_driver = { .writeext = &rtl8211f_phy_extwrite, }; +/* Support for RTL8211F-VD PHY */ +static struct phy_driver RTL8211FVD_driver = { + .name = "RealTek RTL8211F-VD", + .uid = 0x1cc878, + .mask = 0xffffff, + .features = PHY_GBIT_FEATURES, + .probe = &rtl8211f_probe, + .config = &rtl8211f_config, + .startup = &rtl8211f_startup, + .shutdown = &genphy_shutdown, + .readext = &rtl8211f_phy_extread, + .writeext = &rtl8211f_phy_extwrite, +}; + /* Support for RTL8201F PHY */ static struct phy_driver RTL8201F_driver = { .name = "RealTek RTL8201F 10/100Mbps Ethernet", @@ -476,6 +490,7 @@ int phy_realtek_init(void) phy_register(&RTL8211F_driver); phy_register(&RTL8211DN_driver); phy_register(&RTL8201F_driver); + phy_register(&RTL8211FVD_driver); return 0; } diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 72569fd101..6becaaddd4 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,15 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_IMX93_MIPI_DPHY + bool "NXP i.MX93 MIPI DPHY Driver" + depends on PHY + depends on ARCH_IMX9 + select REGMAP + help + Enable this to add support for the Synopsys DW MIPI DPHY as found + on NXP's i.MX93 SoC. + config PHY_XILINX_ZYNQMP tristate "Xilinx ZynqMP PHY driver" depends on PHY && ARCH_ZYNQMP diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index f6953a3451..5f195daffe 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_IMX93_MIPI_DPHY) += phy-imx93-mipi-dphy.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-imx93-mipi-dphy.c b/drivers/phy/phy-imx93-mipi-dphy.c new file mode 100644 index 0000000000..54f2d03c1d --- /dev/null +++ b/drivers/phy/phy-imx93-mipi-dphy.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <clk.h> +#include <regmap.h> +#include <dm/device_compat.h> +#include <phy-mipi-dphy.h> +#include <div64.h> + +/* DPHY registers */ +#define DSI_REG 0x4c +#define CFGCLKFREQRANGE_MASK GENMASK(5, 0) +#define CFGCLKFREQRANGE(x) FIELD_PREP(CFGCLKFREQRANGE_MASK, (x)) +#define CLKSEL_MASK GENMASK(7, 6) +#define CLKSEL_STOP FIELD_PREP(CLKSEL_MASK, 0) +#define CLKSEL_GEN FIELD_PREP(CLKSEL_MASK, 1) +#define CLKSEL_EXT FIELD_PREP(CLKSEL_MASK, 2) +#define HSFREQRANGE_MASK GENMASK(14, 8) +#define HSFREQRANGE(x) FIELD_PREP(HSFREQRANGE_MASK, (x)) +#define UPDATE_PLL BIT(17) +#define SHADOW_CLR BIT(18) +#define CLK_EXT BIT(19) + +#define DSI_WRITE_REG0 0x50 +#define M_MASK GENMASK(9, 0) +#define M(x) FIELD_PREP(M_MASK, ((x) - 2)) +#define N_MASK GENMASK(13, 10) +#define N(x) FIELD_PREP(N_MASK, ((x) - 1)) +#define VCO_CTRL_MASK GENMASK(19, 14) +#define VCO_CTRL(x) FIELD_PREP(VCO_CTRL_MASK, (x)) +#define PROP_CTRL_MASK GENMASK(25, 20) +#define PROP_CTRL(x) FIELD_PREP(PROP_CTRL_MASK, (x)) +#define INT_CTRL_MASK GENMASK(31, 26) +#define INT_CTRL(x) FIELD_PREP(INT_CTRL_MASK, (x)) + +#define DSI_WRITE_REG1 0x54 +#define GMP_CTRL_MASK GENMASK(1, 0) +#define GMP_CTRL(x) FIELD_PREP(GMP_CTRL_MASK, (x)) +#define CPBIAS_CTRL_MASK GENMASK(8, 2) +#define CPBIAS_CTRL(x) FIELD_PREP(CPBIAS_CTRL_MASK, (x)) +#define PLL_SHADOW_CTRL BIT(9) + +#define DSI_READ_REG1 0x5c +#define LOCK_PLL BIT(10) + +#define MHZ(x) ((x) * 1000000UL) + +#define REF_CLK_RATE_MAX MHZ(64) +#define REF_CLK_RATE_MIN MHZ(2) +#define FOUT_MAX MHZ(1250) +#define FOUT_MIN MHZ(40) +#define FVCO_DIV_FACTOR MHZ(80) + +#define MBPS(x) ((x) * 1000000UL) + +#define DATA_RATE_MAX_SPEED MBPS(2500) +#define DATA_RATE_MIN_SPEED MBPS(80) + +#define M_MAX 625UL +#define M_MIN 64UL + +#define N_MAX 16U +#define N_MIN 1U + +#define PLL_LOCK_SLEEP 10 +#define PLL_LOCK_TIMEOUT 1000 + +struct dw_dphy_cfg { + u32 m; /* PLL Feedback Multiplication Ratio */ + u32 n; /* PLL Input Frequency Division Ratio */ +}; + +struct dw_dphy_priv { + struct regmap *regmap; + struct clk ref_clk; + struct clk cfg_clk; + unsigned long ref_clk_rate; +}; + +struct dw_dphy_vco_prop { + unsigned int max_fout; + u8 vco_cntl; + u8 prop_cntl; +}; + +struct dw_dphy_hsfreqrange { + unsigned int max_mbps; + u8 hsfreqrange; +}; + +/* Databook Table 3-13 Charge-pump Programmability */ +static const struct dw_dphy_vco_prop vco_prop_map[] = { + { 55, 0x3f, 0x0d }, + { 82, 0x37, 0x0d }, + { 110, 0x2f, 0x0d }, + { 165, 0x27, 0x0d }, + { 220, 0x1f, 0x0d }, + { 330, 0x17, 0x0d }, + { 440, 0x0f, 0x0d }, + { 660, 0x07, 0x0d }, + { 1149, 0x03, 0x0d }, + { 1152, 0x01, 0x0d }, + { 1250, 0x01, 0x0e }, +}; + +/* Databook Table 5-7 Frequency Ranges and Defaults */ +static const struct dw_dphy_hsfreqrange hsfreqrange_map[] = { + { 89, 0x00 }, + { 99, 0x10 }, + { 109, 0x20 }, + { 119, 0x30 }, + { 129, 0x01 }, + { 139, 0x11 }, + { 149, 0x21 }, + { 159, 0x31 }, + { 169, 0x02 }, + { 179, 0x12 }, + { 189, 0x22 }, + { 204, 0x32 }, + { 219, 0x03 }, + { 234, 0x13 }, + { 249, 0x23 }, + { 274, 0x33 }, + { 299, 0x04 }, + { 324, 0x14 }, + { 349, 0x25 }, + { 399, 0x35 }, + { 449, 0x05 }, + { 499, 0x16 }, + { 549, 0x26 }, + { 599, 0x37 }, + { 649, 0x07 }, + { 699, 0x18 }, + { 749, 0x28 }, + { 799, 0x39 }, + { 849, 0x09 }, + { 899, 0x19 }, + { 949, 0x29 }, + { 999, 0x3a }, + { 1049, 0x0a }, + { 1099, 0x1a }, + { 1149, 0x2a }, + { 1199, 0x3b }, + { 1249, 0x0b }, + { 1299, 0x1b }, + { 1349, 0x2b }, + { 1399, 0x3c }, + { 1449, 0x0c }, + { 1499, 0x1c }, + { 1549, 0x2c }, + { 1599, 0x3d }, + { 1649, 0x0d }, + { 1699, 0x1d }, + { 1749, 0x2e }, + { 1799, 0x3e }, + { 1849, 0x0e }, + { 1899, 0x1e }, + { 1949, 0x2f }, + { 1999, 0x3f }, + { 2049, 0x0f }, + { 2099, 0x40 }, + { 2149, 0x41 }, + { 2199, 0x42 }, + { 2249, 0x43 }, + { 2299, 0x44 }, + { 2349, 0x45 }, + { 2399, 0x46 }, + { 2449, 0x47 }, + { 2499, 0x48 }, + { 2500, 0x49 }, +}; + +static int phy_write(struct phy *phy, u32 value, unsigned int reg) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = regmap_write(priv->regmap, reg, value); + if (ret < 0) + dev_err(phy->dev, "failed to write reg %u: %d\n", reg, ret); + return ret; +} + +static inline unsigned long data_rate_to_fout(unsigned long data_rate) +{ + /* Fout is half of data rate */ + return data_rate / 2; +} + +static int +dw_dphy_config_from_opts(struct phy *phy, + struct phy_configure_opts_mipi_dphy *dphy_opts, + struct dw_dphy_cfg *cfg) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + unsigned long fin = priv->ref_clk_rate; + unsigned long fout; + unsigned long best_fout = 0; + unsigned int fvco_div; + unsigned int min_n, max_n, n, best_n; + unsigned long m, best_m; + unsigned long min_delta = ULONG_MAX; + unsigned long tmp, delta; + + if (dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED || + dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED) { + dev_dbg(phy->dev, "invalid data rate per lane: %lu\n", + dphy_opts->hs_clk_rate); + return -EINVAL; + } + + fout = data_rate_to_fout(dphy_opts->hs_clk_rate); + + /* Fout = Fvco / Fvco_div = (Fin * M) / (Fvco_div * N) */ + fvco_div = 8UL / min(DIV_ROUND_UP(fout, FVCO_DIV_FACTOR), 8UL); + + /* limitation: 2MHz <= Fin / N <= 8MHz */ + min_n = DIV_ROUND_UP(fin, MHZ(8)); + max_n = DIV_ROUND_DOWN_ULL(fin, MHZ(2)); + + /* clamp possible N(s) */ + min_n = clamp(min_n, N_MIN, N_MAX); + max_n = clamp(max_n, N_MIN, N_MAX); + + dev_dbg(phy->dev, "Fout = %lu, Fvco_div = %u, n_range = [%u, %u]\n", + fout, fvco_div, min_n, max_n); + + for (n = min_n; n <= max_n; n++) { + /* M = (Fout * N * Fvco_div) / Fin */ + tmp = fout * n * fvco_div; + m = DIV_ROUND_CLOSEST(tmp, fin); + + /* check M range */ + if (m < M_MIN || m > M_MAX) + continue; + + /* calculate temporary Fout */ + tmp = m * fin; + do_div(tmp, n * fvco_div); + if (tmp < FOUT_MIN || tmp > FOUT_MAX) + continue; + + delta = abs(fout - tmp); + if (delta < min_delta) { + best_n = n; + best_m = m; + min_delta = delta; + best_fout = tmp; + } + } + + if (best_fout) { + cfg->m = best_m; + cfg->n = best_n; + dphy_opts->hs_clk_rate = best_fout * 2; + dev_dbg(phy->dev, "best Fout = %lu, m = %u, n = %u\n", + best_fout, cfg->m, cfg->n); + } else { + dev_dbg(phy->dev, "failed to find best Fout\n"); + return -EINVAL; + } + + return 0; +} + +static void dw_dphy_clear_shadow(struct phy *phy) +{ + /* Select clock generation first. */ + phy_write(phy, CLKSEL_GEN, DSI_REG); + + /* Clear shadow after clock selection is done a while. */ + udelay(2); + phy_write(phy, CLKSEL_GEN | SHADOW_CLR, DSI_REG); + + /* + * A minimum pulse of 5ns on shadow_clear signal, + * according to Databook Figure 3-3 Initialization Timing Diagram. + */ + udelay(2); + phy_write(phy, CLKSEL_GEN, DSI_REG); +} + +static u32 dw_dphy_get_cfgclkrange(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + + return (clk_get_rate(&priv->cfg_clk) / MHZ(1) - 17) * 4; +} + +static u8 dw_dphy_get_hsfreqrange(struct phy_configure_opts_mipi_dphy *dphy_opts) +{ + unsigned int mbps = dphy_opts->hs_clk_rate / MHZ(1); + int i; + + for (i = 0; i < ARRAY_SIZE(hsfreqrange_map); i++) + if (mbps <= hsfreqrange_map[i].max_mbps) + return hsfreqrange_map[i].hsfreqrange; + + return 0; +} + +static u8 dw_dphy_get_vco(struct phy_configure_opts_mipi_dphy *dphy_opts) +{ + unsigned int fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1); + int i; + + for (i = 0; i < ARRAY_SIZE(vco_prop_map); i++) + if (fout <= vco_prop_map[i].max_fout) + return vco_prop_map[i].vco_cntl; + + return 0; +} + +static u8 dw_dphy_get_prop(struct phy_configure_opts_mipi_dphy *dphy_opts) +{ + unsigned int fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1); + int i; + + for (i = 0; i < ARRAY_SIZE(vco_prop_map); i++) + if (fout <= vco_prop_map[i].max_fout) + return vco_prop_map[i].prop_cntl; + + return 0; +} + +static int dw_dphy_configure(struct phy *phy, void *params) +{ + struct dw_dphy_cfg cfg = { 0 }; + u32 val; + int ret; + struct phy_configure_opts_mipi_dphy *opts = (struct phy_configure_opts_mipi_dphy *)params; + + ret = dw_dphy_config_from_opts(phy, opts, &cfg); + if (ret) + return ret; + + dw_dphy_clear_shadow(phy); + + /* reg */ + val = CLKSEL_GEN | + CFGCLKFREQRANGE(dw_dphy_get_cfgclkrange(phy)) | + HSFREQRANGE(dw_dphy_get_hsfreqrange(opts)); + phy_write(phy, val, DSI_REG); + + /* w_reg0 */ + val = M(cfg.m) | N(cfg.n) | INT_CTRL(0) | + VCO_CTRL(dw_dphy_get_vco(opts)) | + PROP_CTRL(dw_dphy_get_prop(opts)); + phy_write(phy, val, DSI_WRITE_REG0); + + /* w_reg1 */ + phy_write(phy, GMP_CTRL(1) | CPBIAS_CTRL(0x10), DSI_WRITE_REG1); + + return 0; +} + +static void dw_dphy_clear_reg(struct phy *phy) +{ + phy_write(phy, 0, DSI_REG); + phy_write(phy, 0, DSI_WRITE_REG0); + phy_write(phy, 0, DSI_WRITE_REG1); +} + +static int dw_dphy_init(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(&priv->cfg_clk); + if (ret < 0) { + dev_err(phy->dev, "failed to enable config clock: %d\n", ret); + return ret; + } + + dw_dphy_clear_reg(phy); + + return 0; +} + +static int dw_dphy_exit(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + + dw_dphy_clear_reg(phy); + clk_disable_unprepare(&priv->cfg_clk); + + return 0; +} + +static int dw_dphy_update_pll(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = regmap_update_bits(priv->regmap, DSI_REG, UPDATE_PLL, UPDATE_PLL); + if (ret < 0) { + dev_err(phy->dev, "failed to set UPDATE_PLL: %d\n", ret); + return ret; + } + + /* + * The updatepll signal should be asserted for a minimum of four clkin + * cycles, according to Databook Figure 3-3 Initialization Timing + * Diagram. + */ + udelay(10); + + ret = regmap_update_bits(priv->regmap, DSI_REG, UPDATE_PLL, 0); + if (ret < 0) { + dev_err(phy->dev, "failed to clear UPDATE_PLL: %d\n", ret); + return ret; + } + + return 0; +} + +static int dw_dphy_power_on(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(&priv->ref_clk); + if (ret < 0) { + dev_err(phy->dev, "failed to enable ref clock: %d\n", ret); + return ret; + } + + /* + * At least 10 refclk cycles are required before updatePLL assertion, + * according to Databook Figure 3-3 Initialization Timing Diagram. + */ + udelay(10); + + ret = dw_dphy_update_pll(phy); + if (ret < 0) { + clk_disable_unprepare(&priv->ref_clk); + return ret; + } + + return 0; +} + +static int dw_dphy_power_off(struct phy *phy) +{ + struct dw_dphy_priv *priv = dev_get_priv(phy->dev); + + dw_dphy_clear_reg(phy); + clk_disable_unprepare(&priv->ref_clk); + + return 0; +} + +static const struct phy_ops imx_dw_dphy_phy_ops = { + .init = dw_dphy_init, + .exit = dw_dphy_exit, + .power_on = dw_dphy_power_on, + .power_off = dw_dphy_power_off, + .configure = dw_dphy_configure, +}; + +static int imx_dw_dphy_probe(struct udevice *dev) +{ + struct dw_dphy_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(ofnode_get_parent(dev_ofnode(dev)), &priv->regmap); + if (ret) { + dev_err(dev, "failed to get regmap %d\n", ret); + return ret; + } + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "phy_cfg", &priv->cfg_clk); + if (ret) { + dev_err(dev, "failed to get config clock %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "phy_ref", &priv->ref_clk); + if (ret) { + dev_err(dev, "failed to get ref clock %d\n", ret); + return ret; + } + + priv->ref_clk_rate = clk_get_rate(&priv->ref_clk); + if (priv->ref_clk_rate < REF_CLK_RATE_MIN || + priv->ref_clk_rate > REF_CLK_RATE_MAX) { + dev_err(dev, "invalid ref clock rate %lu\n", + priv->ref_clk_rate); + return -EINVAL; + } + dev_dbg(dev, "ref clock rate: %lu\n", priv->ref_clk_rate); +#endif + + return 0; +} + +static int imx_dw_dphy_remove(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id imx_dw_mipi_dphy_of_match[] = { + { .compatible = "fsl,imx93-mipi-dphy" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx_dw_mipi_dphy) = { + .name = "imx_dw_mipi_dphy", + .id = UCLASS_PHY, + .of_match = imx_dw_mipi_dphy_of_match, + .probe = imx_dw_dphy_probe, + .remove = imx_dw_dphy_remove, + .ops = &imx_dw_dphy_phy_ops, + .priv_auto = sizeof(struct dw_dphy_priv), +}; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 0051af41ad..d991d5b5cc 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -101,6 +101,19 @@ config PINCTRL_IMX8M only parses the 'fsl,pins' property and configure related registers. +config PINCTRL_IMX93 + bool "IMX8M pinctrl driver" + depends on ARCH_IMX9 && PINCTRL_FULL + select PINCTRL_IMX + help + Say Y here to enable the imx8m pinctrl driver + + This provides a simple pinctrl driver for i.MX8M SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. + config PINCTRL_MXS bool "NXP MXS pinctrl driver" depends on ARCH_MX28 && PINCTRL_FULL diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index f2fe0d8efa..331cd63300 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o +obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c index 6ea66a080b..316fe284d2 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8m.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -10,6 +10,10 @@ static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data"); +static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info = { + .flags = ZERO_OFFSET_VALID, +}; + static int imx8mq_pinctrl_probe(struct udevice *dev) { struct imx_pinctrl_soc_info *info = @@ -23,6 +27,7 @@ static const struct udevice_id imx8m_pinctrl_match[] = { { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, { .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, { .compatible = "fsl,imx8mp-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, + { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, { /* sentinel */ } }; diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 8b83fcbcdf..2fe1b1d387 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -39,6 +39,12 @@ config IMX8M_POWER_DOMAIN Enable support for manipulating NXP i.MX8M on-SoC power domains via requests to the ATF. +config IMX93_BLK_CTRL + bool "Enable i.MX93 block control driver" + depends on POWER_DOMAIN && ARCH_IMX9 + help + Enable support for manipulating NXP i.MX93 on-SoC block control driver + config MTK_POWER_DOMAIN bool "Enable the MediaTek power domain driver" depends on POWER_DOMAIN && ARCH_MEDIATEK diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 054fd2529d..17a1e22e0e 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o +obj-$(CONFIG_IMX93_BLK_CTRL) += imx93-blk-ctrl.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o diff --git a/drivers/power/domain/imx93-blk-ctrl.c b/drivers/power/domain/imx93-blk-ctrl.c new file mode 100644 index 0000000000..71c0d27188 --- /dev/null +++ b/drivers/power/domain/imx93-blk-ctrl.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <power-domain-uclass.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <dt-bindings/power/imx93-power.h> +#include <clk.h> + +#define BLK_SFT_RSTN 0x0 +#define BLK_CLK_EN 0x4 + +#define BLK_MAX_CLKS 4 +#define DOMAIN_MAX_CLKS 4 + +struct imx93_blk_ctrl_domain { + struct clk clks[DOMAIN_MAX_CLKS]; +}; + +struct imx93_blk_ctrl { + void __iomem *base; + struct clk clks[BLK_MAX_CLKS]; + struct imx93_blk_ctrl_domain *domains; +}; + +struct imx93_blk_ctrl_domain_data { + const char *name; + const char * const *clk_names; + int num_clks; + u32 rst_mask; + u32 clk_mask; +}; + +struct imx93_blk_ctrl_data { + int max_reg; + const struct imx93_blk_ctrl_domain_data *domains; + const struct imx93_blk_ctrl_domain_data *bus; + int num_domains; +}; + +static int imx93_blk_ctrl_request(struct power_domain *power_domain) +{ + return 0; +} + +static int imx93_blk_ctrl_free(struct power_domain *power_domain) +{ + return 0; +} + +static int imx93_blk_ctrl_enable_bus_clk(struct udevice *dev, bool enable) +{ + int ret, i; + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + struct imx93_blk_ctrl_data *drv_data = + (struct imx93_blk_ctrl_data *)dev_get_driver_data(dev); + + for (i = 0; i < drv_data->bus->num_clks; i++) { + if (enable) + ret = clk_enable(&priv->clks[i]); + else + ret = clk_disable(&priv->clks[i]); + if (ret) { + printf("Failed to %s bus clk %s\n", enable ? "enable" : "disable", drv_data->bus->clk_names[i]); + return ret; + } + } + + return 0; +} + +static int imx93_blk_ctrl_enable_domain_clk(struct udevice *dev, ulong domain_id, bool enable) +{ + int ret, i; + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + struct imx93_blk_ctrl_data *drv_data = + (struct imx93_blk_ctrl_data *)dev_get_driver_data(dev); + + debug("%s num_clk %u\n", __func__, drv_data->domains[domain_id].num_clks); + + for (i = 0; i < drv_data->domains[domain_id].num_clks; i++) { + debug("%s clk %s\n", __func__, drv_data->domains[domain_id].clk_names[i]); + if (enable) + ret = clk_enable(&priv->domains[domain_id].clks[i]); + else + ret = clk_disable(&priv->domains[domain_id].clks[i]); + if (ret) { + printf("Failed to %s domain clk %s\n", enable ? "enable" : "disable", drv_data->domains[domain_id].clk_names[i]); + return ret; + } + } + + return 0; +} + +static int imx93_blk_ctrl_power_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + struct imx93_blk_ctrl_data *drv_data = + (struct imx93_blk_ctrl_data *)dev_get_driver_data(dev); + + debug("%s, id %lu\n", __func__, power_domain->id); + + imx93_blk_ctrl_enable_bus_clk(dev, true); + imx93_blk_ctrl_enable_domain_clk(dev, power_domain->id, true); + + /* ungate clk */ + clrbits_le32(priv->base + BLK_CLK_EN, drv_data->domains[power_domain->id].clk_mask); + + /* release reset */ + setbits_le32(priv->base + BLK_SFT_RSTN, drv_data->domains[power_domain->id].rst_mask); + + return 0; +} + +static int imx93_blk_ctrl_power_off(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + struct imx93_blk_ctrl_data *drv_data = + (struct imx93_blk_ctrl_data *)dev_get_driver_data(dev); + + debug("%s, id %lu\n", __func__, power_domain->id); + + /* assert reset */ + clrbits_le32(priv->base + BLK_SFT_RSTN, drv_data->domains[power_domain->id].rst_mask); + + /* gate clk */ + setbits_le32(priv->base + BLK_CLK_EN, drv_data->domains[power_domain->id].clk_mask); + + imx93_blk_ctrl_enable_domain_clk(dev, power_domain->id, false); + + imx93_blk_ctrl_enable_bus_clk(dev, false); + + return 0; +} + +static int imx93_blk_ctrl_probe(struct udevice *dev) +{ + int ret, i, j; + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + struct imx93_blk_ctrl_data *drv_data = + (struct imx93_blk_ctrl_data *)dev_get_driver_data(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + priv->domains = kcalloc(drv_data->num_domains, sizeof(struct imx93_blk_ctrl_domain), GFP_KERNEL); + + for (i = 0; i < drv_data->bus->num_clks; i++) { + ret = clk_get_by_name(dev, drv_data->bus->clk_names[i], &priv->clks[i]); + if (ret) { + printf("Failed to get clk %s\n", drv_data->bus->clk_names[i]); + return ret; + } + } + + for (j = 0; j < drv_data->num_domains; j++) { + for (i = 0; i < drv_data->domains[j].num_clks; i++) { + ret = clk_get_by_name(dev, drv_data->domains[j].clk_names[i], &priv->domains[j].clks[i]); + if (ret) { + printf("Failed to get clk %s\n", drv_data->domains[j].clk_names[i]); + return ret; + } + } + } + + return 0; +} + +static int imx93_blk_ctrl_remove(struct udevice *dev) +{ + struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev); + + kfree(priv->domains); + + return 0; +} + +static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_bus_data = { + .clk_names = (const char *[]){ "axi", "apb", "nic", }, + .num_clks = 3, +}; + +static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_domain_data[] = { + [IMX93_MEDIABLK_PD_MIPI_DSI] = { + .name = "mediablk-mipi-dsi", + .clk_names = (const char *[]){ "dsi" }, + .num_clks = 1, + .rst_mask = BIT(11) | BIT(12), + .clk_mask = BIT(11) | BIT(12), + }, + [IMX93_MEDIABLK_PD_MIPI_CSI] = { + .name = "mediablk-mipi-csi", + .clk_names = (const char *[]){ "cam", "csi" }, + .num_clks = 2, + .rst_mask = BIT(9) | BIT(10), + .clk_mask = BIT(9) | BIT(10), + }, + [IMX93_MEDIABLK_PD_PXP] = { + .name = "mediablk-pxp", + .clk_names = (const char *[]){ "pxp" }, + .num_clks = 1, + .rst_mask = BIT(7) | BIT(8), + .clk_mask = BIT(7) | BIT(8), + }, + [IMX93_MEDIABLK_PD_LCDIF] = { + .name = "mediablk-lcdif", + .clk_names = (const char *[]){ "disp", "lcdif" }, + .num_clks = 2, + .rst_mask = BIT(4) | BIT(5) | BIT(6), + .clk_mask = BIT(4) | BIT(5) | BIT(6), + }, + [IMX93_MEDIABLK_PD_ISI] = { + .name = "mediablk-isi", + .clk_names = (const char *[]){ "isi" }, + .num_clks = 1, + .rst_mask = BIT(2) | BIT(3), + .clk_mask = BIT(2) | BIT(3), + }, +}; + +static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = { + .max_reg = 0x8, + .domains = imx93_media_blk_ctl_domain_data, + .bus = &imx93_media_blk_ctl_bus_data, + .num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data), +}; + +static const struct udevice_id imx93_blk_ctrl_ids[] = { + { .compatible = "fsl,imx93-media-blk-ctrl", .data = (ulong)&imx93_media_blk_ctl_dev_data }, + { } +}; + +struct power_domain_ops imx93_blk_ctrl_ops = { + .request = imx93_blk_ctrl_request, + .rfree = imx93_blk_ctrl_free, + .on = imx93_blk_ctrl_power_on, + .off = imx93_blk_ctrl_power_off, +}; + +U_BOOT_DRIVER(imx93_blk_ctrl) = { + .name = "imx93_blk_ctrl", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx93_blk_ctrl_ids, + .bind = dm_scan_fdt_dev, + .probe = imx93_blk_ctrl_probe, + .remove = imx93_blk_ctrl_remove, + .priv_auto = sizeof(struct imx93_blk_ctrl), + .ops = &imx93_blk_ctrl_ops, +}; diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 495ddd3dce..fbc3f212af 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -45,7 +45,11 @@ int power_domain_lookup_name(const char *name, struct power_domain *power_domain ret = uclass_find_device_by_name(UCLASS_POWER_DOMAIN, name, &dev); if (!ret) { /* Probe the dev */ - device_probe(dev); + ret = device_probe(dev); + if (ret) { + printf("Power domain probe device %s failed: %d\n", name, ret); + return ret; + } ops = power_domain_dev_ops(dev); power_domain->dev = dev; @@ -177,8 +181,7 @@ static int dev_power_domain_ctrl(struct udevice *dev, bool on) * off their power-domain parent. So we will get here again and * again and will be stuck in an endless loop. */ - if (!on && dev_get_parent(dev) == pd.dev && - device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN) + if (!on && dev_get_parent(dev) == pd.dev) return ret; /* diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2394b196c5..4bd8c00a37 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -84,6 +84,7 @@ static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450a", .data = 0x25, }, { .compatible = "nxp,pca9450b", .data = 0x25, }, { .compatible = "nxp,pca9450c", .data = 0x25, }, + { .compatible = "nxp,pca9451a", .data = 0x25, }, { } }; diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index d0700252ad..064c4c7406 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -54,11 +54,7 @@ #define FIFO_RXSIZE_MASK 0x7 #define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 -#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT) #define FIFO_RXFE 0x08 -#else -#define FIFO_RXFE 0x40 -#endif #define WATER_TXWATER_OFF 0 #define WATER_RXWATER_OFF 16 diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index a21f8b838c..6274640c41 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -27,10 +27,10 @@ config IMX_SCU_THERMAL trip is crossed config IMX_TMU - bool "Thermal Management Unit driver for NXP i.MX8M" - depends on ARCH_IMX8M + bool "Thermal Management Unit driver for NXP i.MX8M and iMX93" + depends on ARCH_IMX8M || IMX93 help - Support for Temperature sensors on NXP i.MX8M. + Support for Temperature sensors on NXP i.MX8M and iMX93. It supports one critical trip point and one passive trip point. The boot is hold to the cool device to throttle CPUs when the passive trip is crossed @@ -42,6 +42,12 @@ config IMX_PMC_TEMPERATURE Enable PMC Temperature Sensor on NXP i.MX8ULP. The driver supports reading CPU temperature. +config SCMI_THERMAL + bool "SCMI Sensor based thermal driver" + select SCMI_FIRMWARE + help + Enable SCMI Sensor protocol based thermal driver to get temperature. + config TI_DRA7_THERMAL bool "Temperature sensor driver for TI dra7xx SOCs" help diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index a3b72418fc..779f7d9642 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o obj-$(CONFIG_IMX_TMU) += imx_tmu.o obj-$(CONFIG_IMX_PMC_TEMPERATURE) += imx_pmc_temperature.o +obj-$(CONFIG_SCMI_THERMAL) += scmi_thermal.o diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index ca45abbb8e..893e674455 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 +#define FLAGS_VER4 0x4 #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 @@ -75,6 +76,46 @@ struct imx_tmu_regs { u32 ttr3cr; /* Temperature Range 3 Control Register */ }; +struct imx_tmu_regs_v4 { + u32 tmr; /* Mode Register */ + u32 tsr; /* Status Register */ + u32 tmsr; /* Monitor Site Register */ + u32 tmtmir; /* Temperature measurement interval Register */ + u8 res0[0x10]; + u32 tier; /* Interrupt Enable Register */ + u32 tidr; /* Interrupt Detect Register */ + u8 res1[0x8]; + u32 tiiscr; /* Interrupt Immediate Site Capture Register */ + u32 tiascr; /* Interrupt Average Site Capture Register */ + u32 ticscr; /* Interrupt Critical Site Capture Register */ + u8 res2[0x4]; + u32 tmhtcr; /* Monitor High Temperature Capture Register */ + u32 tmltcr; /* MonitorLow Temperature Capture Register */ + u32 tmrtrcr; /* Monitor Rising Temperature Rate Capture Register */ + u32 tmftrcr; /* Monitor Falling Temperature Rate Capture Register */ + u32 tmhtitr; /* Monitor High Temperature Immediate Threshold */ + u32 tmhtatr; /* Monitor High Temperature Average Threshold */ + u32 tmhtactr; /* Monitor High Temperature Average Crit Threshold */ + u8 res3[0x4]; + u32 tmltitr; /* Monitor Low Temperature Immediate Threshold */ + u32 tmltatr; /* Monitor Low Temperature Average Threshold */ + u32 tmltactr; /* Monitor Low Temperature Average Crit Threshold */ + u8 res4[0x4]; + u32 tmrtrctr; /* Monitor Rising Temperature Rate Critical Threshold Register */ + u32 tmftrctr; /* Monitor Falling Temperature Rate Critical Threshold Register */ + u8 res5[0x8]; + u32 ttcfgr; /* Temperature Configuration Register */ + u32 tscfgr; /* Sensor Configuration Register */ + u8 res6[0x78]; + u32 tritsr0; /* Immediate Temperature Site Register */ + u32 tratsr0; /* Average Temperature Site Register */ + u8 res7[0xdf8]; + u32 tcmcfg; /* Central Module Configuration */ + u8 res8[0xc]; + u32 ttrcr[16]; /* Temperature Range Control Register */ +}; + + struct imx_tmu_regs_v2 { u32 ter; /* TMU enable Register */ u32 tsr; /* Status Register */ @@ -114,6 +155,7 @@ union tmu_regs { struct imx_tmu_regs regs_v1; struct imx_tmu_regs_v2 regs_v2; struct imx_tmu_regs_v3 regs_v3; + struct imx_tmu_regs_v4 regs_v4; }; struct imx_tmu_plat { @@ -147,6 +189,9 @@ static int read_temperature(struct udevice *dev, int *temp) * only reflects the RAW uncalibrated data */ valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1; + } else if (drv_data & FLAGS_VER4) { + val = readl(&pdata->regs->regs_v4.tritsr0); + valid = val & 0x80000000; } else { val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); valid = val & 0x80000000; @@ -164,6 +209,13 @@ static int read_temperature(struct udevice *dev, int *temp) return -EINVAL; *temp *= 1000; + } else if (drv_data & FLAGS_VER4) { + *temp = (val & 0x1ff) * 1000; + if (val & 0x200) + *temp += 500; + + /* Convert Kelvin to Celsius */ + *temp -= 273000; } else { *temp = (val & 0xff) * 1000; } @@ -215,6 +267,26 @@ static int imx_tmu_calibration(struct udevice *dev) if (drv_data & (FLAGS_VER2 | FLAGS_VER3)) return 0; + if (drv_data & FLAGS_VER4) { + int index; + calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); + if (!calibration || len % 8 || len > 128) { + printf("TMU: invalid calibration data.\n"); + return -ENODEV; + } + + for (i = 0; i < len; i += 8, calibration += 2) { + index = i / 8; + writel(index, &pdata->regs->regs_v4.ttcfgr); + val = fdt32_to_cpu(*calibration); + writel(val, &pdata->regs->regs_v4.tscfgr); + val = fdt32_to_cpu(*(calibration + 1)); + writel((1 << 31) | val, &pdata->regs->regs_v4.ttrcr[index]); + } + + return 0; + } + ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4); if (ret) { printf("TMU: missing calibration range, ret = %d.\n", ret); @@ -267,6 +339,15 @@ static void imx_tmu_init(struct udevice *dev) /* Disable interrupt, using polling instead */ writel(0x0, &pdata->regs->regs_v2.tier); + } else if (drv_data & FLAGS_VER4) { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_v4.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_v4.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir); } else { /* Disable monitoring */ writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); @@ -319,6 +400,22 @@ static int imx_tmu_enable_msite(struct udevice *dev) /* Enable monitor */ reg |= TER_EN; writel(reg, &pdata->regs->regs_v2.ter); + } else if (drv_data & FLAGS_VER4) { + reg = readl(&pdata->regs->regs_v4.tcmcfg); + reg |= (1 << 30) | (1 << 28); + reg &= ~0xF000; /* set SAR clk = IPG clk /16 */ + writel(reg, &pdata->regs->regs_v4.tcmcfg); + + /* Set ALPF*/ + reg = readl(&pdata->regs->regs_v4.tmr); + reg |= TMR_ALPF; + writel(reg, &pdata->regs->regs_v4.tmr); + + writel(1, &pdata->regs->regs_v4.tmsr); + + /* Enable ME */ + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_v4.tmr); } else { /* Clear the ME before setting MSITE and ALPF*/ reg = readl(&pdata->regs->regs_v1.tmr); @@ -460,6 +557,7 @@ static const struct udevice_id imx_tmu_ids[] = { { .compatible = "fsl,imx8mq-tmu", }, { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, }, { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, }, + { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, }, { } }; diff --git a/drivers/thermal/scmi_thermal.c b/drivers/thermal/scmi_thermal.c new file mode 100644 index 0000000000..bccfd28c2f --- /dev/null +++ b/drivers/thermal/scmi_thermal.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <thermal.h> +#include <scmi_agent.h> +#include <scmi_protocols.h> +#include <asm/types.h> +#include <dm/device-internal.h> +#include <dm/device.h> + +struct scmi_thermal_priv { + s16 num_sensors; + s16 thermal_id; + struct scmi_sensor_descrition_get_p2a *desc_buf; + size_t desc_buf_size; +}; + +static int scmi_thermal_get_temp(struct udevice *dev, int *temp) +{ + struct scmi_thermal_priv *priv = dev_get_priv(dev); + struct scmi_sensor_reading_get_a2p in = { priv->thermal_id }; + struct scmi_sensor_reading_get_p2a out = { 0 }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_SENSOR, + .message_id = SCMI_SENSOR_READING_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev->parent, &msg); + if (ret) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + *temp = out.val.value_low; + + return ret; +} + +static int scmi_sensor_attributes_get(struct udevice *dev) +{ + struct scmi_protocol_attributes_p2a_sensor out = { 0 }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_SENSOR, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .in_msg = NULL, + .in_msg_sz = 0, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + struct scmi_thermal_priv *priv = dev_get_priv(dev); + + ret = devm_scmi_process_msg(dev->parent, &msg); + if (ret) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + priv->num_sensors = out.num_sensors; + + dev_dbg(dev,"num_sensors %d\n", priv->num_sensors); + + return 0; +} + +static int scmi_sensor_description_get(struct udevice *dev, u32 start_ind, + struct scmi_sensor_descrition_get_p2a *desc_buf, size_t desc_buf_size) +{ + struct scmi_sensor_description_get_a2p in = { start_ind }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_SENSOR, + .message_id = SCMI_SENSOR_DESCRIPTION_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)desc_buf, + .out_msg_sz = desc_buf_size, + }; + int ret; + + ret = devm_scmi_process_msg(dev->parent, &msg); + if (ret) + return ret; + + ret = scmi_to_linux_errno(desc_buf->status); + if (ret < 0) + return ret; + + return ret; +} + +static const struct dm_thermal_ops scmi_thermal_ops = { + .get_temp = scmi_thermal_get_temp, +}; + +static int scmi_thermal_probe(struct udevice *dev) +{ + int ret; + u16 num_returned, num_remaining, cnt; + u32 index = 0; + bool find = false; + struct scmi_sensor_desc *desc; + struct scmi_thermal_priv *priv = dev_get_priv(dev); + + ret = scmi_sensor_attributes_get(dev); + if (ret){ + dev_err(dev, "scmi_sensor_attributes_get failure %d\n", ret); + return ret; + } + + priv->desc_buf_size = sizeof(struct scmi_sensor_descrition_get_p2a) + + (priv->num_sensors - 1) * sizeof(struct scmi_sensor_desc); + priv->desc_buf = (struct scmi_sensor_descrition_get_p2a *)calloc(1, priv->desc_buf_size); + if (!priv->desc_buf) { + dev_err(dev, "allocate desc_buffer failure\n"); + return -ENOMEM; + } + + do { + ret = scmi_sensor_description_get(dev, index, priv->desc_buf, priv->desc_buf_size); + if (ret){ + dev_err(dev, "scmi_sensor_description_get failure %d\n", ret); + return ret; + } + + num_returned = priv->desc_buf->num_sensor_flags & 0xffff; + num_remaining = (priv->desc_buf->num_sensor_flags >> 16) & 0xffff; + + if (index + num_returned > priv->num_sensors) { + dev_err(dev, "Num of sensors can't exceed %d", + priv->num_sensors); + return -EINVAL; + } + + for (cnt = 0; cnt < num_returned; cnt++) { + desc = &priv->desc_buf->desc[cnt]; + if ((desc->attr_high & 0xff) == 0x2) { + priv->thermal_id = desc->id; /* Only get one thermal sensor */ + dev_dbg(dev, "thermal id %u\n", priv->thermal_id); + find = true; + break; + } + } + + index += num_returned; + } while (num_returned && num_remaining && !find); + + if (!find) { + dev_err(dev, "Can't find thermal sensor device\n"); + return -ENODEV; + } + + return 0; +} + +U_BOOT_DRIVER(scmi_thermal) = { + .name = "scmi_thermal", + .id = UCLASS_THERMAL, + .ops = &scmi_thermal_ops, + .probe = scmi_thermal_probe, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto = sizeof(struct scmi_thermal_priv), +}; diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 5bd80cf986..730454c66e 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -55,7 +55,7 @@ static struct usb_request *next_request(struct list_head *list) static void select_ep(struct usb_ss_dev *usb_ss, u32 ep) { if (!usb_ss || !usb_ss->regs) { - dev_err(&usb_ss->dev, "Failed to select endpoint!\n"); + printf("Failed to select endpoint!\n"); return; } diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 318f746b05..37b5b6c4d8 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1051,7 +1051,7 @@ static int ci_udc_otg_phy_mode2(void *__iomem phy_base) return USB_INIT_DEVICE; else return USB_INIT_HOST; - } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) { phy_status = (void __iomem *)(phy_base + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); @@ -1379,7 +1379,7 @@ int __weak board_ci_udc_phy_mode(void *__iomem phy_base, int phy_off) return USB_INIT_DEVICE; else return USB_INIT_HOST; - } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) { phy_status = (void __iomem *)(phy_base + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); @@ -1433,7 +1433,7 @@ static int ci_udc_otg_probe(struct udevice *dev) ret = pinctrl_select_state(&priv->otgdev, "default"); if (ret) - printf("Failed to configure default pinctrl\n"); + DBG("Failed to configure default pinctrl\n"); #if defined(CONFIG_MX6) if (usb_fused((u32)ehci)) { diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index fa9202cb1e..b42a800ed3 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -189,9 +189,9 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 || IMX8M - select PHY if IMX8M - select NOP_PHY if IMX8M + depends on ARCH_MX7 || IMX8M || IMX93 + select PHY if IMX8M || IMX93 + select NOP_PHY if IMX8M || IMX93 default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 368b493ef4..bc57630e38 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -351,7 +351,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) priv->init_type = USB_INIT_DEVICE; else priv->init_type = USB_INIT_HOST; - } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) { phy_status = (void __iomem *)(addr + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 9c9cc524f3..ed77bb336d 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -446,6 +446,15 @@ config VIDEO_LCD_RAYDIUM_RM67191 Say Y here if you want to enable support for Raydium RM68200 1080x1920 DSI video mode panel. +config VIDEO_LCD_USMP_RM67162 + bool "RM67162 DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + help + Say Y here if you want to enable support for USMP RM67162 + 400x400 DSI video mode panel. + config VIDEO_LCD_ROCKTECH_HIMAX8394F bool "Rocktech Himax8394f 720x1280 DSI video mode panel" depends on DM_VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 5347ba52a8..2f0578d35c 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM67191) += raydium-rm67191.o obj-$(CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F) += rocktech-hx8394f.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_LCD_USMP_RM67162) += usmp-rm67162.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-$(CONFIG_VIDEO_ADV7535) += adv7535.o obj-${CONFIG_VIDEO_MESON} += meson/ diff --git a/drivers/video/adv7535.c b/drivers/video/adv7535.c index 48df72e671..80f9c6ee19 100644 --- a/drivers/video/adv7535.c +++ b/drivers/video/adv7535.c @@ -236,7 +236,7 @@ static const struct panel_ops adv7535_ops = { }; static const struct udevice_id adv7535_ids[] = { - { .compatible = "adi,adv7533" }, + { .compatible = "adi,adv7535" }, { } }; diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index 0391ccf20c..abee8d293e 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -49,6 +49,16 @@ int video_bridge_check_attached(struct udevice *dev) return ops->check_attached(dev); } +int video_bridge_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct video_bridge_ops *ops = video_bridge_get_ops(dev); + + if (ops->check_timing) + return ops->check_timing(dev, timing); + + return 0; +} + int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size) { struct video_bridge_ops *ops = video_bridge_get_ops(dev); diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index a5b38acabd..0cd50fd465 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -513,7 +513,7 @@ static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi) * timeout clock division should be computed with the * high speed transmission counter timeout and byte lane... */ - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | + dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) | TX_ESC_CLK_DIVISION(esc_clk_division)); } @@ -538,9 +538,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, break; } - if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH) + if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW) val |= VSYNC_ACTIVE_LOW; - if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH) + if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW) val |= HSYNC_ACTIVE_LOW; dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); @@ -552,7 +552,7 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, * should be computed according to byte lane, lane number and only * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) */ - dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) + dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(0x10) | INVACT_LPCMD_TIME(4)); } @@ -621,8 +621,8 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, htotal = timings->hactive.typ + timings->hfront_porch.typ + timings->hback_porch.typ + timings->hsync_len.typ; - hsa = timings->hback_porch.typ; - hbp = timings->hsync_len.typ; + hsa = timings->hsync_len.typ; + hbp = timings->hback_porch.typ; /* * TODO dw drv improvements @@ -644,9 +644,9 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, u32 vactive, vsa, vfp, vbp; vactive = timings->vactive.typ; - vsa = timings->vback_porch.typ; - vfp = timings->vfront_porch.typ; - vbp = timings->vsync_len.typ; + vsa = timings->vsync_len.typ; + vfp = timings->vfront_porch.typ; + vbp = timings->vback_porch.typ; dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); dsi_write(dsi, DSI_VID_VSA_LINES, vsa); @@ -807,14 +807,11 @@ static int dw_mipi_dsi_init(struct udevice *dev, } ret = clk_get_by_name(device->dev, "px_clk", &clk); - if (ret) { - dev_err(device->dev, "peripheral clock get error %d\n", ret); - return ret; + if (!ret) { + /* get the pixel clock set by the clock framework */ + timings->pixelclock.typ = clk_get_rate(&clk); } - /* get the pixel clock set by the clock framework */ - timings->pixelclock.typ = clk_get_rate(&clk); - dw_mipi_dsi_bridge_set(dsi, timings); return 0; @@ -840,9 +837,19 @@ static int dw_mipi_dsi_probe(struct udevice *dev) return 0; } +#if (IS_ENABLED(CONFIG_VIDEO_IMX_DW_DSI)) +static const struct udevice_id dw_mipi_dsi_ids[] = { + { .compatible = "synopsys,dw-mipi-dsi" }, + { } +}; +#endif + U_BOOT_DRIVER(dw_mipi_dsi) = { .name = "dw_mipi_dsi", .id = UCLASS_DSI_HOST, +#if (IS_ENABLED(CONFIG_VIDEO_IMX_DW_DSI)) + .of_match = dw_mipi_dsi_ids, +#endif .probe = dw_mipi_dsi_probe, .ops = &dw_mipi_dsi_ops, .priv_auto = sizeof(struct dw_mipi_dsi), diff --git a/drivers/video/nxp/imx/Kconfig b/drivers/video/nxp/imx/Kconfig index 05dacc8818..1824b969fb 100644 --- a/drivers/video/nxp/imx/Kconfig +++ b/drivers/video/nxp/imx/Kconfig @@ -100,9 +100,18 @@ config VIDEO_IMX_NW_DSI This option enables support DSI internal bridge which can be used on devices which have DSI devices connected. +config VIDEO_IMX_DW_DSI + bool "Enable Synopsys DW DSI video support" + select VIDEO_BRIDGE + select VIDEO_DW_MIPI_DSI + select VIDEO_LINK + help + This option enables support DSI internal bridge which can be used on + devices which have DSI devices connected. + config VIDEO_IMX_LCDIFV3 bool "i.MX LCDIFv3 support" - depends on DM_VIDEO && IMX8MP + depends on DM_VIDEO && (IMX8MP || ARCH_IMX9) select VIDEO_LINK help Support for i.MX8MP LCDIFv3 controller. @@ -114,3 +123,10 @@ config VIDEO_IMX_DCNANO help Support for i.MX8ULP DCNANO LCD controller. +config VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT + bool "Support for i.MX93 parallel display format" + select VIDEO_BRIDGE + select VIDEO_LINK + help + Choose this to enable the internal parallel display format + configuration found on i.MX93 processors. diff --git a/drivers/video/nxp/imx/Makefile b/drivers/video/nxp/imx/Makefile index 1315033e35..019789fe0c 100644 --- a/drivers/video/nxp/imx/Makefile +++ b/drivers/video/nxp/imx/Makefile @@ -13,5 +13,7 @@ obj-$(CONFIG_VIDEO_IMX_SEC_DSI) += sec_dsim_imx.o obj-$(CONFIG_VIDEO_IMX_LCDIFV3) += imx_lcdifv3.o obj-$(CONFIG_VIDEO_NW_MIPI_DSI) += mipi_dsi_northwest.o obj-$(CONFIG_VIDEO_IMX_NW_DSI) += nw_dsi_imx.o +obj-$(CONFIG_VIDEO_IMX_DW_DSI) += dw_dsi_imx.o obj-$(CONFIG_VIDEO_IMX_DCNANO) += dcnano.o +obj-$(CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT) += imx93-parallel-disp-fmt.o obj-y += hdmi/ diff --git a/drivers/video/nxp/imx/dw_dsi_imx.c b/drivers/video/nxp/imx/dw_dsi_imx.c new file mode 100644 index 0000000000..6bdd382621 --- /dev/null +++ b/drivers/video/nxp/imx/dw_dsi_imx.c @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dsi_host.h> +#include <mipi_dsi.h> +#include <panel.h> +#include <reset.h> +#include <video.h> +#include <video_bridge.h> +#include <video_link.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <dm/device-internal.h> +#include <linux/iopoll.h> +#include <linux/err.h> +#include <phy-mipi-dphy.h> +#include <generic-phy.h> + +#define MSEC_PER_SEC 1000 + +struct dw_dsi_imx_priv { + struct mipi_dsi_device device; + struct udevice *panel; + struct udevice *dsi_host; + + struct clk byte_clk; + + struct phy phy; + struct phy_configure_opts_mipi_dphy phy_cfg; + + unsigned int lane_mbps; /* per lane */ + u32 lanes; + u32 format; + struct display_timing adj; +}; + +static int dw_mipi_dsi_imx_phy_init(void *priv_data) +{ + struct dw_dsi_imx_priv *dsi = priv_data; + int ret; + + ret = generic_phy_init(&dsi->phy); + if (ret < 0) { + dev_err(dsi->device.dev, "failed to init phy: %d\n", ret); + return ret; + } + + ret = generic_phy_configure(&dsi->phy, &dsi->phy_cfg); + if (ret < 0) { + dev_err(dsi->device.dev, "failed to configure phy: %d\n", ret); + goto uninit_phy; + } + + ret = generic_phy_power_on(&dsi->phy); + if (ret < 0) { + dev_err(dsi->device.dev, "failed to power on phy: %d\n", ret); + goto uninit_phy; + } + + return ret; + +uninit_phy: + generic_phy_exit(&dsi->phy); + return ret; +} + +static int +dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, + u32 lanes, u32 format, unsigned int *lane_mbps) +{ + struct dw_dsi_imx_priv *dsi = priv_data; + int bpp; + int ret; + + bpp = mipi_dsi_pixel_format_to_bpp(format); + if (bpp < 0) { + dev_dbg(dsi->device.dev, + "failed to get bpp for pixel format %d\n", + format); + return bpp; + } + + dsi->lane_mbps = DIV_ROUND_UP((timings->pixelclock.typ / 1000) * (bpp / lanes), MSEC_PER_SEC); + *lane_mbps = dsi->lane_mbps; + + debug("lane_mbps %u, bpp %d\n", *lane_mbps, bpp); + + ret = phy_mipi_dphy_get_default_config(timings->pixelclock.typ, + bpp, lanes, + &dsi->phy_cfg); + if (ret < 0) { + dev_dbg(dsi->device.dev, "failed to get default phy cfg %d\n", ret); + return ret; + } + + return 0; +} + +struct hstt { + unsigned int maxfreq; + struct mipi_dsi_phy_timing timing; +}; + +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ +{ \ + .maxfreq = (_maxfreq), \ + .timing = { \ + .clk_lp2hs = (_c_lp2hs), \ + .clk_hs2lp = (_c_hs2lp), \ + .data_lp2hs = (_d_lp2hs), \ + .data_hs2lp = (_d_hs2lp), \ + } \ +} + +/* Table A-4 High-Speed Transition Times */ +struct hstt hstt_table[] = { + HSTT(80, 21, 17, 15, 10), + HSTT(90, 23, 17, 16, 10), + HSTT(100, 22, 17, 16, 10), + HSTT(110, 25, 18, 17, 11), + HSTT(120, 26, 20, 18, 11), + HSTT(130, 27, 19, 19, 11), + HSTT(140, 27, 19, 19, 11), + HSTT(150, 28, 20, 20, 12), + HSTT(160, 30, 21, 22, 13), + HSTT(170, 30, 21, 23, 13), + HSTT(180, 31, 21, 23, 13), + HSTT(190, 32, 22, 24, 13), + HSTT(205, 35, 22, 25, 13), + HSTT(220, 37, 26, 27, 15), + HSTT(235, 38, 28, 27, 16), + HSTT(250, 41, 29, 30, 17), + HSTT(275, 43, 29, 32, 18), + HSTT(300, 45, 32, 35, 19), + HSTT(325, 48, 33, 36, 18), + HSTT(350, 51, 35, 40, 20), + HSTT(400, 59, 37, 44, 21), + HSTT(450, 65, 40, 49, 23), + HSTT(500, 71, 41, 54, 24), + HSTT(550, 77, 44, 57, 26), + HSTT(600, 82, 46, 64, 27), + HSTT(650, 87, 48, 67, 28), + HSTT(700, 94, 52, 71, 29), + HSTT(750, 99, 52, 75, 31), + HSTT(800, 105, 55, 82, 32), + HSTT(850, 110, 58, 85, 32), + HSTT(900, 115, 58, 88, 35), + HSTT(950, 120, 62, 93, 36), + HSTT(1000, 128, 63, 99, 38), + HSTT(1050, 132, 65, 102, 38), + HSTT(1100, 138, 67, 106, 39), + HSTT(1150, 146, 69, 112, 42), + HSTT(1200, 151, 71, 117, 43), + HSTT(1250, 153, 74, 120, 45), + HSTT(1300, 160, 73, 124, 46), + HSTT(1350, 165, 76, 130, 47), + HSTT(1400, 172, 78, 134, 49), + HSTT(1450, 177, 80, 138, 49), + HSTT(1500, 183, 81, 143, 52), + HSTT(1550, 191, 84, 147, 52), + HSTT(1600, 194, 85, 152, 52), + HSTT(1650, 201, 86, 155, 53), + HSTT(1700, 208, 88, 161, 53), + HSTT(1750, 212, 89, 165, 53), + HSTT(1800, 220, 90, 171, 54), + HSTT(1850, 223, 92, 175, 54), + HSTT(1900, 231, 91, 180, 55), + HSTT(1950, 236, 95, 185, 56), + HSTT(2000, 243, 97, 190, 56), + HSTT(2050, 248, 99, 194, 58), + HSTT(2100, 252, 100, 199, 59), + HSTT(2150, 259, 102, 204, 61), + HSTT(2200, 266, 105, 210, 62), + HSTT(2250, 269, 109, 213, 63), + HSTT(2300, 272, 109, 217, 65), + HSTT(2350, 281, 112, 225, 66), + HSTT(2400, 283, 115, 226, 66), + HSTT(2450, 282, 115, 226, 67), + HSTT(2500, 281, 118, 227, 67), +}; + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct mipi_dsi_phy_timing *timing) +{ + struct dw_dsi_imx_priv *dsi = priv_data; + int i; + + for (i = 0; i < ARRAY_SIZE(hstt_table); i++) + if (lane_mbps <= hstt_table[i].maxfreq) + break; + + if (i == ARRAY_SIZE(hstt_table)) + i--; + + *timing = hstt_table[i].timing; + + dev_dbg(dsi->device.dev, "get phy timing for %u <= %u (lane_mbps)\n", + lane_mbps, hstt_table[i].maxfreq); + + return 0; +} + +static const struct mipi_dsi_phy_ops dsi_imx_phy_ops = { + .init = dw_mipi_dsi_imx_phy_init, + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, + .get_timing = dw_mipi_dsi_phy_get_timing, +}; + +static bool dw_dsi_imx_hcomponents_need_fixup(struct dw_dsi_imx_priv *dsi, + int bpp, + struct display_timing *timings) +{ + int htotal = timings->hactive.typ + timings->hfront_porch.typ + + timings->hback_porch.typ + timings->hsync_len.typ; + int hsa = timings->hsync_len.typ; + int hbp = timings->hback_porch.typ; + int divisor = dsi->lanes * 8; + + /* + * It appears that (hcomponent * bpp) / (8 * lanes) + * should be no remainder. + */ + return !!((htotal * bpp) % divisor) || + !!((hsa * bpp) % divisor) || + !!((hbp * bpp) % divisor); +} + +static int dw_dsi_imx_fixup_hcomponent(struct dw_dsi_imx_priv *dsi, + int bpp, int component) +{ + int divisor, i; + + divisor = dsi->lanes * 8; + + for (i = 0; i < divisor; i++) { + if ((bpp * (component + i)) % divisor == 0) { + component += i; + break; + } + } + + return component; +} + +static void dw_dsi_imx_fixup_hcomponents(struct dw_dsi_imx_priv *dsi, + int bpp, + struct display_timing *timings, + struct display_timing *adj) +{ + int hfp = timings->hfront_porch.typ; + int hsa = timings->hsync_len.typ; + int hbp = timings->hback_porch.typ; + + adj->hfront_porch.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hfp); + adj->hsync_len.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hsa); + adj->hback_porch.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hbp); +} + +static int dw_dsi_imx_attach(struct udevice *dev) +{ + struct dw_dsi_imx_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct mipi_dsi_panel_plat *mplat; + struct display_timing timings; + int ret, bpp; + + priv->panel = video_link_get_next_device(dev); + if (!priv->panel || + device_get_uclass_id(priv->panel) != UCLASS_PANEL) { + dev_err(dev, "get panel device error\n"); + return -ENODEV; + } + + mplat = dev_get_plat(priv->panel); + mplat->device = &priv->device; + + ret = video_link_get_display_timings(&timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + + bpp = mipi_dsi_pixel_format_to_bpp(device->format); + if (bpp < 0) { + dev_err(dev, "failed to get bpp for pixel format %d\n", device->format); + return bpp; + } + + priv->lanes = device->lanes; + priv->format = device->format; + + priv->adj = timings; + if (dw_dsi_imx_hcomponents_need_fixup(priv, bpp, &timings)) + dw_dsi_imx_fixup_hcomponents(priv, bpp, &timings, &priv->adj); + + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); + if (ret) { + dev_err(dev, "No video dsi host detected %d\n", ret); + return ret; + } + + ret = dsi_host_init(priv->dsi_host, device, &priv->adj, + 4, + &dsi_imx_phy_ops); + if (ret) { + dev_err(dev, "failed to initialize mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int dw_dsi_imx_set_backlight(struct udevice *dev, int percent) +{ + struct dw_dsi_imx_priv *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", + priv->panel->name, ret); + return ret; + } + + ret = dsi_host_enable(priv->dsi_host); + if (ret) { + dev_err(dev, "failed to enable mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int dw_dsi_imx_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct dw_dsi_imx_priv *priv = dev_get_priv(dev); + + /* Ensure the bridge device attached to panel */ + if (!priv->panel) { + dev_err(dev, "%s No panel device attached\n", __func__); + return -ENOTCONN; + } + + /* DSI force the Polarities as high */ + priv->adj.flags &= ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW); + priv->adj.flags |= DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH; + + *timing = priv->adj; + + return 0; +} + +static int dw_dsi_imx_probe(struct udevice *dev) +{ + struct dw_dsi_imx_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + int ret; + + device->dev = dev; + + ret = clk_get_by_name(device->dev, "byte", &priv->byte_clk); + if (ret) { + dev_err(dev, "byte clock get error %d\n", ret); + return ret; + } + + ret = clk_enable(&priv->byte_clk); + if (ret) { + dev_err(dev, "byte clock enable error %d\n", ret); + return ret; + } + + ret = generic_phy_get_by_name(dev, "dphy", &priv->phy); + if (ret) { + dev_err(dev, "failed to get phy: %d\n", ret); + clk_disable(&priv->byte_clk); + return ret; + } + + return ret; +} + +static int dw_dsi_imx_remove(struct udevice *dev) +{ + struct dw_dsi_imx_priv *priv = dev_get_priv(dev); + int ret; + + if (priv->panel) + device_remove(priv->panel, DM_REMOVE_NORMAL); + + ret = dsi_host_disable(priv->dsi_host); + if (ret < 0 && ret != -ENOSYS) + dev_err(dev, "failed to disable mipi dsi host\n"); + + ret = generic_phy_power_off(&priv->phy); + if (ret < 0) + dev_err(dev, "failed to power off phy: %d\n", ret); + + ret = generic_phy_exit(&priv->phy); + if (ret < 0) + dev_err(dev, "failed to exit phy: %d\n", ret); + + device_remove(priv->phy.dev, DM_REMOVE_NORMAL); + + ret = clk_disable(&priv->byte_clk); + if (ret) + dev_err(dev, "byte clock disable error %d\n", ret); + + return 0; +} + +struct video_bridge_ops dw_dsi_imx_ops = { + .attach = dw_dsi_imx_attach, + .set_backlight = dw_dsi_imx_set_backlight, + .check_timing = dw_dsi_imx_check_timing, +}; + +static const struct udevice_id dw_dsi_imx_ids[] = { + { .compatible = "fsl,imx93-mipi-dsi" }, + { } +}; + +U_BOOT_DRIVER(dw_dsi_imx) = { + .name = "dw_dsi_imx", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = dw_dsi_imx_ids, + .bind = dm_scan_fdt_dev, + .remove = dw_dsi_imx_remove, + .probe = dw_dsi_imx_probe, + .ops = &dw_dsi_imx_ops, + .priv_auto = sizeof(struct dw_dsi_imx_priv), +}; diff --git a/drivers/video/nxp/imx/imx8_lvds.c b/drivers/video/nxp/imx/imx8_lvds.c index d9162dbbc2..87b0108838 100644 --- a/drivers/video/nxp/imx/imx8_lvds.c +++ b/drivers/video/nxp/imx/imx8_lvds.c @@ -80,6 +80,20 @@ static int imx8_ldb_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_cloc return -EIO; } + err = sc_pm_set_clock_parent(-1, lvds_rsrc, SC_PM_CLK_PER, SC_PM_PARENT_BYPS); + if (err) { + printf("LVDS set SC_PM_CLK_PER parent failed! (error = %d)\n", + err); + return -EIO; + } + + err = sc_pm_set_clock_parent(-1, lvds_rsrc, SC_PM_CLK_PHY, SC_PM_PARENT_BYPS); + if (err) { + printf("LVDS set SC_PM_CLK_PHY parent failed! (error = %d)\n", + err); + return -EIO; + } + err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PER, &pixel_clock); if (err) { printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); diff --git a/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c b/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c new file mode 100644 index 0000000000..72af93873f --- /dev/null +++ b/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <panel.h> +#include <reset.h> +#include <video.h> +#include <video_bridge.h> +#include <video_link.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <dm/device-internal.h> +#include <linux/iopoll.h> +#include <linux/err.h> +#include <media_bus_format.h> + +#define DISPLAY_MUX_CTRL 0x60 +#define PARALLEL_DISP_FORMAT 0x700 + +enum imx93_pdf_format { + RGB888_TO_RGB888 = 0x0, + RGB888_TO_RGB666 = 0x1 << 8, + RGB565_TO_RGB565 = 0x2 << 8, +}; + +struct imx93_pdf_priv { + struct udevice *panel; + struct display_timing adj; + enum imx93_pdf_format format; + void *__iomem addr; +}; + +static int imx93_pdf_attach(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + struct display_timing timings; + int ret; + + priv->panel = video_link_get_next_device(dev); + if (!priv->panel || + device_get_uclass_id(priv->panel) != UCLASS_PANEL) { + dev_err(dev, "get panel device error\n"); + return -ENODEV; + } + + ret = video_link_get_display_timings(&timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + + priv->adj = timings; + + writel(priv->format, priv->addr + DISPLAY_MUX_CTRL); + + return 0; +} + +static int imx93_pdf_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + + /* Ensure the bridge device attached to panel */ + if (!priv->panel) { + dev_err(dev, "%s No panel device attached\n", __func__); + return -ENOTCONN; + } + + *timing = priv->adj; + + return 0; +} + +static int imx93_pdf_probe(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + const char *fmt; + u32 bus_format; + int ret; + + priv->addr = (void __iomem *)dev_read_addr(dev_get_parent(dev)); + if ((fdt_addr_t)priv->addr == FDT_ADDR_T_NONE) { + dev_err(dev, "not able to get addr\n"); + return -EINVAL; + } + + ret = ofnode_read_string_index(dev_ofnode(dev), "fsl,interface-pix-fmt", 0, &fmt); + if (!ret) { + if (!strcmp(fmt, "rgb565")) + bus_format = MEDIA_BUS_FMT_RGB565_1X16; + else if (!strcmp(fmt, "rgb666")) + bus_format = MEDIA_BUS_FMT_RGB666_1X18; + else if (!strcmp(fmt, "rgb888")) + bus_format = MEDIA_BUS_FMT_RGB888_1X24; + + } + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + priv->format = RGB565_TO_RGB565; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + priv->format = RGB888_TO_RGB666; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + priv->format = RGB888_TO_RGB888; + break; + default: + dev_dbg(dev, "invalid bus format 0x%x\n", bus_format); + return -EINVAL; + } + + + return 0; +} + +static int imx93_pdf_remove(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + + if (priv->panel) + device_remove(priv->panel, DM_REMOVE_NORMAL); + + return 0; +} + +static int imx93_pdf_set_backlight(struct udevice *dev, int percent) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", priv->panel->name, ret); + return ret; + } + + return 0; +} + +struct video_bridge_ops imx93_pdf_ops = { + .attach = imx93_pdf_attach, + .check_timing = imx93_pdf_check_timing, + .set_backlight = imx93_pdf_set_backlight, +}; + +static const struct udevice_id imx93_pdf_ids[] = { + { .compatible = "fsl,imx93-parallel-display-format" }, + { } +}; + +U_BOOT_DRIVER(imx93_pdf_driver) = { + .name = "imx93_pdf_driver", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = imx93_pdf_ids, + .bind = dm_scan_fdt_dev, + .remove = imx93_pdf_remove, + .probe = imx93_pdf_probe, + .ops = &imx93_pdf_ops, + .priv_auto = sizeof(struct imx93_pdf_priv), +}; diff --git a/drivers/video/nxp/imx/imx_lcdifv3.c b/drivers/video/nxp/imx/imx_lcdifv3.c index 1eb9938777..66e6ad6a86 100644 --- a/drivers/video/nxp/imx/imx_lcdifv3.c +++ b/drivers/video/nxp/imx/imx_lcdifv3.c @@ -99,8 +99,15 @@ static void lcdifv3_set_mode(struct lcdifv3_priv *priv, writel(ctrldescl0_1, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_1)); /* Polarities */ - writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); - writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + else + writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_SET)); + + if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + else + writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_SET)); /* SEC MIPI DSI specific */ writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); @@ -316,7 +323,6 @@ static void lcdifv3_of_parse_thres(struct udevice *dev) } } - static int lcdifv3_video_probe(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); @@ -353,6 +359,12 @@ static int lcdifv3_video_probe(struct udevice *dev) return ret; } + ret = video_bridge_check_timing(priv->disp_dev, &timings); + if (ret) { + dev_err(dev, "fail to check timing\n"); + return ret; + } + ret = video_bridge_set_backlight(priv->disp_dev, 80); if (ret) { dev_err(dev, "fail to set backlight\n"); @@ -371,6 +383,13 @@ static int lcdifv3_video_probe(struct udevice *dev) mode.hsync_len = timings.hsync_len.typ; mode.vsync_len = timings.vsync_len.typ; mode.pixclock = HZ2PS(timings.pixelclock.typ); + mode.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT; + + if (timings.flags & DISPLAY_FLAGS_HSYNC_LOW ) + mode.sync &= ~FB_SYNC_HOR_HIGH_ACT; + + if (timings.flags & DISPLAY_FLAGS_VSYNC_LOW ) + mode.sync &= ~FB_SYNC_VERT_HIGH_ACT; lcdifv3_init(dev, &mode, GDF_32BIT_X888RGB); @@ -416,6 +435,7 @@ static int lcdifv3_video_remove(struct udevice *dev) static const struct udevice_id lcdifv3_video_ids[] = { { .compatible = "fsl,imx8mp-lcdif1" }, + { .compatible = "fsl,imx93-lcdif" }, { /* sentinel */ } }; diff --git a/drivers/video/nxp/imx/sec_dsim_imx.c b/drivers/video/nxp/imx/sec_dsim_imx.c index 2e6aa467f7..9c6e7d2bca 100644 --- a/drivers/video/nxp/imx/sec_dsim_imx.c +++ b/drivers/video/nxp/imx/sec_dsim_imx.c @@ -32,6 +32,7 @@ struct imx_sec_dsim_priv { struct reset_ctl_bulk soft_resetn; struct reset_ctl_bulk clk_enable; struct reset_ctl_bulk mipi_reset; + struct display_timing adj; }; #if IS_ENABLED(CONFIG_DM_RESET) @@ -120,6 +121,8 @@ static int imx_sec_dsim_attach(struct udevice *dev) return ret; } + priv->adj = timings; + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); if (ret) { dev_err(dev, "No video dsi host detected %d\n", ret); @@ -209,9 +212,23 @@ static int imx_sec_dsim_remove(struct udevice *dev) return 0; } +static int imx_sec_dsim_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + + /* DSI force the Polarities as high */ + priv->adj.flags &= ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW); + priv->adj.flags |= DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH; + + *timing = priv->adj; + + return 0; +} + struct video_bridge_ops imx_sec_dsim_ops = { .attach = imx_sec_dsim_attach, .set_backlight = imx_sec_dsim_set_backlight, + .check_timing = imx_sec_dsim_check_timing, }; static const struct udevice_id imx_sec_dsim_ids[] = { diff --git a/drivers/video/raydium-rm67191.c b/drivers/video/raydium-rm67191.c index ea61d960f7..883845268d 100644 --- a/drivers/video/raydium-rm67191.c +++ b/drivers/video/raydium-rm67191.c @@ -214,7 +214,7 @@ static const cmd_set_table mcs_rm67199[] = { static const struct display_timing default_timing = { - .pixelclock.typ = 132000000, + .pixelclock.typ = 121000000, .hactive.typ = 1080, .hfront_porch.typ = 20, .hback_porch.typ = 34, diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index c8f7022ea6..f9281d5e83 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -23,12 +23,14 @@ static int simple_panel_enable_backlight(struct udevice *dev) struct simple_panel_priv *priv = dev_get_priv(dev); int ret; - debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); dm_gpio_set_value(&priv->enable, 1); - ret = backlight_enable(priv->backlight); - debug("%s: done, ret = %d\n", __func__, ret); - if (ret) - return ret; + if (priv->backlight) { + debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); + ret = backlight_enable(priv->backlight); + debug("%s: done, ret = %d\n", __func__, ret); + if (ret) + return ret; + } return 0; } @@ -40,10 +42,12 @@ static int simple_panel_set_backlight(struct udevice *dev, int percent) debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); dm_gpio_set_value(&priv->enable, 1); - ret = backlight_set_brightness(priv->backlight, percent); - debug("%s: done, ret = %d\n", __func__, ret); - if (ret) - return ret; + if (priv->backlight) { + ret = backlight_set_brightness(priv->backlight, percent); + debug("%s: done, ret = %d\n", __func__, ret); + if (ret) + return ret; + } return 0; } @@ -66,9 +70,10 @@ static int simple_panel_of_to_plat(struct udevice *dev) ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, "backlight", &priv->backlight); if (ret) { - debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); + printf("%s: Cannot get backlight: ret=%d\n", __func__, ret); + priv->backlight = NULL; } + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, GPIOD_IS_OUT); if (ret) { diff --git a/drivers/video/usmp-rm67162.c b/drivers/video/usmp-rm67162.c new file mode 100644 index 0000000000..6820262f1c --- /dev/null +++ b/drivers/video/usmp-rm67162.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + */ + +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <mipi_dsi.h> +#include <panel.h> +#include <asm/gpio.h> +#include <linux/err.h> +#include <linux/delay.h> + +#define CMD_TABLE_LEN 2 +typedef u8 cmd_set_table[CMD_TABLE_LEN]; + +/* Write Manufacture Command Set Control */ +#define WRMAUCCTR 0xFE + +struct rm67162_panel_priv { + struct gpio_desc reset; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; +}; + +static const cmd_set_table mcs_rm67162_400x400[] = { + /* Page 3:GOA */ + {0xFE, 0x04}, + /* GOA SETTING */ + {0x00, 0xDC}, + {0x01, 0x00}, + {0x02, 0x02}, + {0x03, 0x00}, + {0x04, 0x00}, + {0x05, 0x03}, + {0x06, 0x16}, + {0x07, 0x13}, + {0x08, 0x08}, + {0x09, 0xDC}, + {0x0A, 0x00}, + {0x0B, 0x02}, + {0x0C, 0x00}, + {0x0D, 0x00}, + {0x0E, 0x02}, + {0x0F, 0x16}, + {0x10, 0x18}, + {0x11, 0x08}, + {0x12, 0x92}, + {0x13, 0x00}, + {0x14, 0x02}, + {0x15, 0x05}, + {0x16, 0x40}, + {0x17, 0x03}, + {0x18, 0x16}, + {0x19, 0xD7}, + {0x1A, 0x01}, + {0x1B, 0xDC}, + {0x1C, 0x00}, + {0x1D, 0x04}, + {0x1E, 0x00}, + {0x1F, 0x00}, + {0x20, 0x03}, + {0x21, 0x16}, + {0x22, 0x18}, + {0x23, 0x08}, + {0x24, 0xDC}, + {0x25, 0x00}, + {0x26, 0x04}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x01}, + {0x2A, 0x16}, + {0x2B, 0x18}, + {0x2D, 0x08}, + {0x4C, 0x99}, + {0x4D, 0x00}, + {0x4E, 0x00}, + {0x4F, 0x00}, + {0x50, 0x01}, + {0x51, 0x0A}, + {0x52, 0x00}, + {0x5A, 0xE4}, + {0x5E, 0x77}, + {0x5F, 0x77}, + {0x60, 0x34}, + {0x61, 0x02}, + {0x62, 0x81}, + + /* Page 6 */ + {0xFE, 0x07}, + {0x07, 0x4F}, + + /* Page 0 */ + {0xFE, 0x01}, + /* Display Resolution Panel Option */ + {0x05, 0x15}, + /* DDVDH Charge Pump Control Normal Mode */ + {0x0E, 0x8B}, + /* DDVDH Charge Pump Control ldle Mode */ + {0x0F, 0x8B}, + /* DDVDH/VCL Regulator Enable */ + {0x10, 0x11}, + /* VCL Charge Pump Control Normal Mode */ + {0x11, 0xA2}, + /* VCL Charge Pump Control Idle Mode */ + {0x12, 0xA0}, + /* VGH Charge Pump Control ldle Mode */ + {0x14, 0xA1}, + /* VGL Charge Pump Control Normal Mode */ + {0x15, 0x82}, + /* VGHR Control */ + {0x18, 0x47}, + /* VGLR Control */ + {0x19, 0x36}, + /* VREFPN5 REGULATOR ENABLE */ + {0x1A, 0x10}, + /* VREFPN5 */ + {0x1C, 0x57}, + /* SWITCH EQ Control */ + {0x1D, 0x02}, + /* VGMP Control */ + {0x21, 0xF8}, + /* VGSP Control */ + {0x22, 0x90}, + /* VGMP / VGSP control */ + {0x23, 0x00}, + /* Low Frame Rate Control Normal Mode */ + {0x25, 0x03}, + {0x26, 0x4a}, + /* Low Frame Rate Control Idle Mode */ + {0x2A, 0x03}, + {0x2B, 0x4A}, + {0x2D, 0x12}, + {0x2F, 0x12}, + + {0x30, 0x45}, + + /* Source Control */ + {0x37, 0x0C}, + /* Switch Timing Control */ + {0x3A, 0x00}, + {0x3B, 0x20}, + {0x3D, 0x0B}, + {0x3F, 0x38}, + {0x40, 0x0B}, + {0x41, 0x0B}, + + /* Switch Output Selection */ + {0x42, 0x33}, + {0x43, 0x66}, + {0x44, 0x11}, + {0x45, 0x44}, + {0x46, 0x22}, + {0x47, 0x55}, + {0x4C, 0x33}, + {0x4D, 0x66}, + {0x4E, 0x11}, + {0x4f, 0x44}, + {0x50, 0x22}, + {0x51, 0x55}, + + /* Source Data Output Selection */ + {0x56, 0x11}, + {0x58, 0x44}, + {0x59, 0x22}, + {0x5A, 0x55}, + {0x5B, 0x33}, + {0x5C, 0x66}, + {0x61, 0x11}, + {0x62, 0x44}, + {0x63, 0x22}, + {0x64, 0x55}, + {0x65, 0x33}, + {0x66, 0x66}, + + {0x6D, 0x90}, + {0x6E, 0x40}, + + /* Source Sequence 2 */ + {0x70, 0xA5}, + + /* OVDD control */ + {0x72, 0x04}, + + /* OVSS control */ + {0x73, 0x15}, + + /* Page 9 */ + {0xFE, 0x0A}, + {0x29, 0x10}, + + /* Page 4 */ + {0xFE, 0x05}, + /* ELVSS -2.4V(RT4723). 0x15: RT4723. 0x01: RT4723B. 0x17: STAM1332. */ + {0x05, 0x15}, + + {0xFE, 0x00}, + /* enable TE. */ + {0x35, 0x00}, +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = 12000000, + .hactive.typ = 400, + .hfront_porch.typ = 20, + .hback_porch.typ = 20, + .hsync_len.typ = 40, + .vactive.typ = 400, + .vfront_porch.typ = 20, + .vback_porch.typ = 4, + .vsync_len.typ = 12, +}; + +static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format) +{ + switch (format) { + case MIPI_DSI_FMT_RGB565: + return 0x75; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + return 0x76; + case MIPI_DSI_FMT_RGB888: + return 0x77; + default: + return 0x77; /* for backward compatibility */ + } +}; + +static int usmp_panel_push_cmd_list(struct mipi_dsi_device *device, + const cmd_set_table *cmd_set, + size_t count) +{ + size_t i; + const cmd_set_table *cmd; + int ret = 0; + + for (i = 0; i < count; i++) { + cmd = cmd_set++; + ret = mipi_dsi_generic_write(device, cmd, CMD_TABLE_LEN); + if (ret < 0) + return ret; + } + + return ret; +}; + +static int rm67162_enable(struct udevice *dev) +{ + struct rm67162_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + u8 color_format = color_format_from_dsi_format(priv->format); + u16 brightness; + u8 dsi_mode; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + ret = usmp_panel_push_cmd_list(dsi, &mcs_rm67162_400x400[0], + sizeof(mcs_rm67162_400x400) / CMD_TABLE_LEN); + if (ret < 0) { + printf("Failed to send MCS (%d)\n", ret); + return -EIO; + } + + /* Select User Command Set table (CMD1) */ + ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2); + if (ret < 0) + return -EIO; + + /* Software reset */ + ret = mipi_dsi_dcs_soft_reset(dsi); + if (ret < 0) { + printf("Failed to do Software Reset (%d)\n", ret); + return -EIO; + } + + /* Wait 16ms for panel out of reset */ + mdelay(16); + + /* Set DSI mode */ + dsi_mode = (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? 0x0B : 0x00; + ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, dsi_mode }, 2); + if (ret < 0) { + dev_err(dev, "Failed to set DSI mode (%d)\n", ret); + return -EIO; + } + + /* Set tear ON */ + ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + if (ret < 0) { + printf("Failed to set tear ON (%d)\n", ret); + return -EIO; + } + + /* Set tear scanline */ + ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380); + if (ret < 0) { + printf("Failed to set tear scanline (%d)\n", ret); + return -EIO; + } + + /* Set pixel format */ + ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format); + if (ret < 0) { + printf("Failed to set pixel format (%d)\n", ret); + return -EIO; + } + + /* Exit sleep mode */ + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode (%d)\n", ret); + return -EIO; + } + + mdelay(121); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + printf("Failed to set display ON (%d)\n", ret); + return -EIO; + } + + //mdelay(50); + /* Set display brightness */ + brightness = 255; /* Max brightness */ + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 2); + if (ret < 0) { + printf("Failed to set display brightness (%d)\n", ret); + return -EIO; + } + + return 0; +} + +static int rm67162_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + return rm67162_enable(dev); +} + +static int rm67162_panel_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct rm67162_panel_priv *priv = dev_get_priv(dev); + + memcpy(timings, &default_timing, sizeof(*timings)); + + /* fill characteristics of DSI data link */ + if (device) { + device->lanes = priv->lanes; + device->format = priv->format; + device->mode_flags = priv->mode_flags; + } + + return 0; +} + +static int rm67162_panel_probe(struct udevice *dev) +{ + struct rm67162_panel_priv *priv = dev_get_priv(dev); + int ret; + u32 video_mode; + + priv->format = MIPI_DSI_FMT_RGB888; + priv->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO; + + ret = dev_read_u32(dev, "video-mode", &video_mode); + if (!ret) { + switch (video_mode) { + case 0: + /* burst mode */ + priv->mode_flags |= MIPI_DSI_MODE_VIDEO_BURST; + break; + case 1: + /* non-burst mode with sync event */ + break; + case 2: + /* non-burst mode with sync pulse */ + priv->mode_flags |= MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + break; + default: + dev_warn(dev, "invalid video mode %d\n", video_mode); + break; + } + } + + ret = dev_read_u32(dev, "dsi-lanes", &priv->lanes); + if (ret) { + printf("Failed to get dsi-lanes property (%d)\n", ret); + return ret; + } + + if (dev_read_bool(dev, "reset,otherway")) { + return 0; + } + + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + printf("Warning: cannot get reset GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + /* reset panel */ + ret = dm_gpio_set_value(&priv->reset, true); + if (ret) + printf("reset gpio fails to set true\n"); + mdelay(1); + ret = dm_gpio_set_value(&priv->reset, false); + if (ret) + printf("reset gpio fails to set true\n"); + mdelay(12); + + return 0; +} + +static int rm67162_panel_disable(struct udevice *dev) +{ + struct rm67162_panel_priv *priv = dev_get_priv(dev); + + if (&priv->reset != NULL) + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + +static const struct panel_ops rm67162_panel_ops = { + .enable_backlight = rm67162_panel_enable_backlight, + .get_display_timing = rm67162_panel_get_display_timing, +}; + +static const struct udevice_id rm67162_panel_ids[] = { + { .compatible = "usmp,rm67162" }, + { } +}; + +U_BOOT_DRIVER(rm67162_panel) = { + .name = "rm67162_panel", + .id = UCLASS_PANEL, + .of_match = rm67162_panel_ids, + .ops = &rm67162_panel_ops, + .probe = rm67162_panel_probe, + .remove = rm67162_panel_disable, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct rm67162_panel_priv), +}; diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 4427da6e5f..940ce25c20 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -36,6 +36,7 @@ struct wdog_regs { #define WDGCS_RCS BIT(10) #define WDGCS_ULK BIT(11) +#define WDOG_CS_PRES BIT(12) #define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14) @@ -89,7 +90,11 @@ void hw_watchdog_init(void) writel(0, &wdog->win); /* setting 1-kHz clock source, enable counter running, and clear interrupt */ +#if defined(CONFIG_ARCH_IMX9) + writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG | WDOG_CS_PRES), &wdog->cs); +#else writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); +#endif /* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) @@ -117,11 +122,16 @@ void reset_cpu(void) while (!(readl(&wdog->cs) & WDGCS_ULK)) ; - hw_watchdog_set_timeout(5); /* 5ms timeout */ + hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */ + writel(0, &wdog->win); /* enable counter running */ +#if defined(CONFIG_ARCH_IMX9) + writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), &wdog->cs); +#else writel((cmd32| WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); +#endif /* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index c9ecee588a..53f3a5838f 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -824,15 +824,7 @@ static int new_dir_table(fat_itr *itr) int dir_oldclust = itr->clust; unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; - if (mydata->fatsize == 32) { - dir_newclust = find_empty_cluster(mydata); - } else { - dir_newclust = itr->clust + 1; - if (dir_newclust > 1) { - printf("error: fail to get empty clust for directory entry\n"); - return -1; - } - } + dir_newclust = find_empty_cluster(mydata); /* * Flush before updating FAT to ensure valid directory structure @@ -844,10 +836,13 @@ static int new_dir_table(fat_itr *itr) if (flush_dir(itr)) return -EIO; - if (mydata->fatsize == 32) { - set_fatent_value(mydata, dir_oldclust, dir_newclust); + set_fatent_value(mydata, dir_oldclust, dir_newclust); + if (mydata->fatsize == 32) set_fatent_value(mydata, dir_newclust, 0xffffff8); - } + else if (mydata->fatsize == 16) + set_fatent_value(mydata, dir_newclust, 0xfff8); + else if (mydata->fatsize == 12) + set_fatent_value(mydata, dir_newclust, 0xff8); if (flush_dirty_fat_buffer(mydata) < 0) return -EIO; diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index a45a6ffe7c..1d05bcae99 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2019-2021 Toradex + * Copyright 2019-2022 Toradex */ #ifndef __APALIS_IMX8_H @@ -9,67 +9,57 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 - /* Networking */ #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x84000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x94400000\0" \ - "scriptaddr=0x87000000\0" + "fdt_addr_r=0x9d400000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_comp_addr_r=0xf0000000\0" \ + "kernel_comp_size=0x08000000\0" \ + "ramdisk_addr_r=0x9d500000\0" \ + "scriptaddr=0x9d480000\0" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ +/* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) \ + func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ + M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ - "console=ttyLP1 earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ - "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "console=ttyLP1\0" \ + "fdt_board=eval\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; tftp ${fdt_addr} " \ - "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon\0" \ + "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -/* Link Definitions */ - #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 - #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 @@ -88,4 +78,18 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USBD_HS +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + #endif /* __APALIS_IMX8_H */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 57192649ec..178a219e7c 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -59,18 +59,9 @@ "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ - "${soc}-${fdt_module}-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" - #define BOARD_EXTRA_ENV_SETTINGS \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttyS0\0" \ "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ @@ -79,7 +70,6 @@ "fdt_board=eval\0" \ "fdt_fixup=;\0" \ "fdt_module=" FDT_MODULE "\0" \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index bbdcab29d8..9a611b163a 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -90,16 +90,6 @@ "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 #define FDT_FILE "imx6q-apalis-eval.dtb" #define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" @@ -109,13 +99,13 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ "fdt_file=" FDT_FILE "\0" \ "fdtfile=" FDT_FILE "\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index eab4f22be3..33f2a3be2a 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -47,7 +47,8 @@ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ #define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE + UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 91f0f953a1..654b246b80 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -50,15 +50,6 @@ "ramdisk_addr_r=0x82200000\0" \ "scriptaddr=0x87000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${fdtfile} && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -98,9 +89,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" \ "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index ee070408d4..0f4e415678 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -8,102 +8,53 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#include <linux/stringify.h> - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 #define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "ramdisk_addr_r=0x83800000\0" \ - "scriptaddr=0x80800000\0" - -#ifdef CONFIG_AHAB_BOOT -#define AHAB_ENV "sec_boot=yes\0" -#else -#define AHAB_ENV "sec_boot=no\0" -#endif + "fdt_addr_r=0x9d400000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_comp_addr_r=0xb0000000\0" \ + "kernel_comp_size=0x08000000\0" \ + "ramdisk_addr_r=0x9d500000\0" \ + "scriptaddr=0x9d480000\0" /* Boot M4 */ #define M4_BOOT_ENV \ "m4_0_image=m4_0.bin\0" \ - "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${m4_0_image}\0" \ - "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ - -#define MFG_NAND_PARTITION "" + "loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" +/* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ + func(USB, usb, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs ${consoleargs} " \ - "rdinit=/linuxrc g_mass_storage.stall=0 " \ - "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ - "g_mass_storage.idProduct=0x37FF " \ - "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ - "${vidargs} clk_ignore_unused\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ - "${fdt_addr};\0" \ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - AHAB_ENV \ BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ - "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ - "fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "image=Image\0" \ + "console=ttyLP3\0" \ + "fdt_board=eval-v3\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs ${consoleargs} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "netargs=setenv bootargs ${consoleargs} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ - "${vidargs}\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \ - "${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon\0" \ + "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ "if test \"$confirm\" = \"y\"; then " \ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ - "${blkcnt}; fi\0" \ - "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" - -/* Link Definitions */ + "${blkcnt}; fi\0" #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ - -/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 @@ -122,7 +73,8 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ -#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 -#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ +/* USB Config */ +#define CONFIG_USBD_HS +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif /* __COLIBRI_IMX8X_H */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 1dbc77dde1..ff3f3636ed 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -79,27 +79,17 @@ "ramdisk_addr_r=0x12200000\0" \ "scriptaddr=0x17000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ "fdt_file=" FDT_FILE "\0" \ "fdtfile=" FDT_FILE "\0" \ "fdt_fixup=;\0" \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBOOT_UPDATE \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 92e24ea8c6..276667bb94 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -89,15 +89,6 @@ "ramdisk_addr_r=0x82100000\0" \ "scriptaddr=0x87000000\0" -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -136,10 +127,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ MODULE_EXTRA_ENV_SETTINGS \ UBOOT_UPDATE \ "boot_file=zImage\0" \ + "boot_script_dhcp=boot.scr\0" \ "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=\0" \ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index c377187b80..3752581a27 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -27,6 +27,7 @@ /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ #define BOARD_EXTRA_ENV_SETTINGS \ + "boot_script_dhcp=boot.scr\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ UBOOT_UPDATE diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 324e607839..ca8ddf26f8 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -45,7 +45,8 @@ "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \ #define BOARD_EXTRA_ENV_SETTINGS \ - UBOOT_UPDATE + UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 62f85185b7..68a2f3f3a3 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -46,15 +46,6 @@ "update_uboot=nand erase.part u-boot && " \ "nand write ${loadaddr} u-boot ${filesize}\0" \ -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ @@ -79,9 +70,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ UBI_BOOTCMD \ UBOOT_UPDATE \ + "boot_script_dhcp=boot.scr\0" \ "console=ttyLP0\0" \ "defargs=user_debug=30\0" \ "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ diff --git a/include/configs/imx8mm_ab2.h b/include/configs/imx8mm_ab2.h new file mode 100644 index 0000000000..2c78005afe --- /dev/null +++ b/include/configs/imx8mm_ab2.h @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8MM_AB2_H +#define __IMX8MM_AB2_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#if defined(CONFIG_IMX8M_LPDDR4) && defined(CONFIG_TARGET_IMX8MM_AB2) +#define CONFIG_POWER_PCA9450 +#else +#define CONFIG_POWER_BD71837 +#endif + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define IMX_FEC_BASE 0x30BE0000 +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#define JH_ROOT_DTB "imx8mm-ab2-root.dtb" + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_root_dtb=" JH_ROOT_DTB "\0" \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \ + "setenv jh_clk clk_ignore_unused mem=1212MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 " + +#define M4_BOOT_ENV \ + "m4_boot=no\0" \ + "m4_image=nxh3670.itb\0" \ + "m4_loadaddr=0x80000000\0" \ + "m4_nxh_app_loadaddr=0x81000000\0" \ + "m4_nxh_rfmac_loadaddr=0x81012000\0" \ + "m4_nxh_cf_loadaddr=0x81016000\0" \ + "m4_nxh_data_loadaddr=0x8101E000\0" \ + "m4_sf_loadaddr=0x08100000\0" \ + "m4_fdt_file=imx8mm-ab2-m4.dtb\0" \ + "m4_nxh_bin=main@1\0" \ + "m4_nxh_app=app@1\0" \ + "m4_nxh_rfmac=rfmac@1\0" \ + "m4_nxh_cf=cf@1\0" \ + "m4_nxh_data=data@1\0" \ + "loadm4nxhfw=imxtract ${loadaddr} ${m4_nxh_bin} ${m4_loadaddr}; " \ + "imxtract ${loadaddr} ${m4_nxh_app} ${m4_nxh_app_loadaddr}; " \ + "imxtract ${loadaddr} ${m4_nxh_rfmac} ${m4_nxh_rfmac_loadaddr}; " \ + "imxtract ${loadaddr} ${m4_nxh_cf} ${m4_nxh_cf_loadaddr}; " \ + "imxtract ${loadaddr} ${m4_nxh_data} ${m4_nxh_data_loadaddr}\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${m4_loadaddr} 0x100000 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=run loadm4image; run loadm4nxhfw; dcache flush; bootaux ${m4_loadaddr}\0" \ + "m4netboot=${get_cmd} ${loaddadr} ${m4_image}; " \ + "run loadm4nxhfw; dcache flush; bootaux ${m4_loadaddr}; \0" \ + "m4boot_sf=sf probe 0:0; dcache flush; bootaux ${m4_sf_loadaddr}\0" + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "splashimage=0x50000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr_r} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr_r}" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + BOOTENV \ + JAILHOUSE_ENV \ + M4_BOOT_ENV \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bsp_script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x50000000\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${m4_boot} = yes || test ${m4_boot} = try; then "\ + "echo Booting M4 aux core...; " \ + "run m4boot; " \ + "fi; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${m4_boot} = yes || test ${m4_boot} = try; then " \ + "echo Booting M4 aux core...;" \ + "run m4netboot;" \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" +#endif + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ + +#ifdef CONFIG_TARGET_IMX8MM_DDR4_AB2 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_FSL_FSPI +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USBD_HS +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 257ac79a1e..3d992ffa13 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -123,6 +123,7 @@ CONFIG_MFG_ENV_SETTINGS \ BOOTENV \ JAILHOUSE_ENV \ + "prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted;\0" \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bsp_script=boot.scr\0" \ @@ -139,7 +140,7 @@ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -156,7 +157,7 @@ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi;\0" \ - "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ diff --git a/include/configs/imx8mn_ab2.h b/include/configs/imx8mn_ab2.h new file mode 100644 index 0000000000..fc8b92b087 --- /dev/null +++ b/include/configs/imx8mn_ab2.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8MN_AB2_H +#define __IMX8MN_AB2_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + + +#define CONFIG_SPL_MAX_SIZE (208 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x96fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x954000 +#define CONFIG_MALLOC_F_ADDR 0x970000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define IMX_FEC_BASE 0x30BE0000 +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#ifdef CONFIG_TARGET_IMX8MN_DDR4_AB2 +#define JH_ROOT_DTB "imx8mn-ddr4-ab2-root.dtb" +#else +#define JH_ROOT_DTB "imx8mn-ab2-root.dtb" +#endif + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_root_dtb=" JH_ROOT_DTB "\0" \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \ + "setenv jh_clk clk_ignore_unused mem=1212MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 " + +#define M7_BOOT_ENV \ + "m7_boot=no\0" \ + "m7_image=nxh3670.itb\0" \ + "m7_loadaddr=0x80000000\0" \ + "m7_nxh_app_loadaddr=0x81000000\0" \ + "m7_nxh_rfmac_loadaddr=0x81012000\0" \ + "m7_nxh_cf_loadaddr=0x81016000\0" \ + "m7_nxh_data_loadaddr=0x8101E000\0" \ + "m7_fdt_file=imx8mn-ab2-m7.dtb\0" \ + "m7_nxh_bin=main@1\0" \ + "m7_nxh_app=app@1\0" \ + "m7_nxh_rfmac=rfmac@1\0" \ + "m7_nxh_cf=cf@1\0" \ + "m7_nxh_data=data@1\0" \ + "loadm7nxhfw=imxtract ${loadaddr} ${m7_nxh_bin} ${m7_loadaddr}; " \ + "imxtract ${loadaddr} ${m7_nxh_app} ${m7_nxh_app_loadaddr}; " \ + "imxtract ${loadaddr} ${m7_nxh_rfmac} ${m7_nxh_rfmac_loadaddr}; " \ + "imxtract ${loadaddr} ${m7_nxh_cf} ${m7_nxh_cf_loadaddr}; " \ + "imxtract ${loadaddr} ${m7_nxh_data} ${m7_nxh_data_loadaddr}\0" \ + "loadm7image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m7_image}\0" \ + "update_m7_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm7image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${m7_loadaddr} 0x100000 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m7boot=run loadm7image; run loadm7nxhfw; dcache flush; bootaux ${m7_loadaddr}\0" \ + "m7netboot=${get_cmd} ${loaddadr} ${m7_image}; " \ + "run loadm7nxhfw; dcache flush; bootaux ${m7_loadaddr}; \0" \ + "m7boot_sf=sf probe 0:0; dcache flush; bootaux ${m7_sf_loadaddr}\0" + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + BOOTENV \ + M7_BOOT_ENV \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bsp_script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x50000000\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${m7_boot} = yes || test ${m7_boot} = try; then "\ + "echo Booting M7 aux core...; " \ + "run m7boot; " \ + "fi; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${m7_boot} = yes || test ${m7_boot} = try; then " \ + "echo Booting M7 aux core...;" \ + "run m7netboot;" \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 + +#ifdef CONFIG_TARGET_IMX8MN_DDR3L_AB2 +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +#else +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USBD_HS +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 41e272a09e..1bdf68ab83 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -102,6 +102,7 @@ CONFIG_MFG_ENV_SETTINGS \ JAILHOUSE_ENV \ BOOTENV \ + "prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted;\0" \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bsp_script=boot.scr\0" \ @@ -118,7 +119,7 @@ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -135,7 +136,7 @@ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi;\0" \ - "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index af499376bb..a26c651dcf 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -117,6 +117,7 @@ CONFIG_MFG_ENV_SETTINGS \ JAILHOUSE_ENV \ BOOTENV \ + "prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bsp_script=boot.scr\0" \ @@ -134,7 +135,7 @@ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -151,7 +152,7 @@ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi;\0" \ - "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index b43dce8751..96f72fdbe4 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -84,6 +84,7 @@ CONFIG_MFG_ENV_SETTINGS \ BOOTENV \ JAILHOUSE_ENV \ + "prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted;\0" \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bsp_script=boot.scr\0" \ @@ -100,7 +101,7 @@ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -117,7 +118,7 @@ "else " \ "echo wait for boot; " \ "fi;\0" \ - "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ diff --git a/include/configs/imx8ulp_watch.h b/include/configs/imx8ulp_watch.h new file mode 100644 index 0000000000..154eef096b --- /dev/null +++ b/include/configs/imx8ulp_watch.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX8ULP_WATCH_H +#define __IMX8ULP_WATCH_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x22050000 +#define CONFIG_SPL_BSS_START_ADDR 0x22048000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x22040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ + +#define CONFIG_MALLOC_F_ADDR 0x22040000 + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#endif + +#define COUNTER_FREQUENCY 1000000 /* 1MHz */ + +#define CONFIG_SERIAL_TAG + +/* ENET Config */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define IMX_FEC_BASE 0x29950000 +#endif + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) + +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=setenv jh_clk clk_ignore_unused mem=896MB; run loadimage; run mmcboot\0 " \ + "jh_netboot=setenv jh_clk clk_ignore_unused mem=896MB; run netboot\0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=2\0" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + BOOTENV \ + JAILHOUSE_ENV \ + AHAB_ENV \ + "scriptaddr=0x83500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "splashimage=0x90000000\0" \ + "console=ttyLP1,115200 earlycon\0" \ + "fdtoverlay_addr_r=0x83040000\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_RBASE +/* USB Configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8ulp_evk_android.h" +#endif + +#endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h new file mode 100644 index 0000000000..11caf14fd9 --- /dev/null +++ b/include/configs/imx93_evk.h @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX93_EVK_H +#define __IMX93_EVK_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x20519dd0 +#define CONFIG_SPL_BSS_START_ADDR 0x2051a000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x83200000 /* Need disable simple malloc where still uses malloc_f area */ +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) + +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +#define JAILHOUSE_ENV \ + "jh_mmcboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \ + "setenv jh_clk clk_ignore_unused mem=1248MB kvm-arm.mode=nvhe; " \ + "if run loadimage; then run mmcboot;" \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \ + "setenv jh_clk clk_ignore_unused mem=1248MB kvm-arm.mode=nvhe; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + JAILHOUSE_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + BOOTENV \ + AHAB_ENV \ + "scriptaddr=0x83500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "splashimage=0x90000000\0" \ + "console=ttyLP0,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC +#define PHYS_SDRAM_SIZE 0x70000000 /* 1/8 DDR is used by ECC */ +#else +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 2 + +#define DWC_NET_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#endif diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h new file mode 100644 index 0000000000..ed17090c54 --- /dev/null +++ b/include/configs/imx93_qsb.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX93_QSB_H +#define __IMX93_QSB_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x20519dd0 +#define CONFIG_SPL_BSS_START_ADDR 0x2051a000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x83200000 /* Need disable simple malloc where still uses malloc_f area */ +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) + +#include <config_distro_bootcmd.h> +#else +#define BOOTENV +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + BOOTENV \ + AHAB_ENV \ + "scriptaddr=0x83500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "splashimage=0x90000000\0" \ + "console=ttyLP0,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC +#define PHYS_SDRAM_SIZE 0x70000000 /* 1/8 DDR is used by ECC */ +#else +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" + +#define DWC_NET_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#endif diff --git a/include/configs/imx_env.h b/include/configs/imx_env.h index 7eed730d64..2ca95826f0 100644 --- a/include/configs/imx_env.h +++ b/include/configs/imx_env.h @@ -28,6 +28,30 @@ #define MFG_NAND_FIT_PARTITION "" #endif +#if defined(CONFIG_IMX8MP) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ + 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) +#endif +#if defined(CONFIG_IMX8MM) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ + 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) + +#endif +#if defined(CONFIG_IMX8MN) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ + 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) + +#endif +#if defined(CONFIG_IMX8MQ) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ + 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) + +#endif + #define CONFIG_MFG_ENV_SETTINGS_DEFAULT \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 31b578ae33..e426bedb40 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor + * Copyright 2022 NXP */ #ifndef __LS1043ARDB_H__ @@ -226,7 +227,9 @@ #define QSGMII_PORT3_PHY_ADDR 0x6 #define QSGMII_PORT4_PHY_ADDR 0x7 -#define FM1_10GEC1_PHY_ADDR 0x1 +/* The AQR PHY model and MDIO address differ between board revisions */ +#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */ +#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 3dd334ceec..0d77657978 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -53,7 +53,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "bootcmd_mfg=fastboot 0\0" \ "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ @@ -61,12 +60,6 @@ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \ - "tftp ${fdt_addr} verdin/${fdtfile}; " \ - "booti ${loadaddr} - ${fdt_addr}\0" \ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index d2d652db75..88299ad950 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -79,7 +79,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "bootcmd_mfg=fastboot 0\0" \ "boot_file=Image\0" \ "boot_scripts=" BOOT_SCRIPT "\0" \ "boot_script_dhcp=" BOOT_SCRIPT "\0" \ @@ -87,12 +86,6 @@ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \ - "tftp ${fdt_addr} verdin/${fdtfile}; " \ - "booti ${loadaddr} - ${fdt_addr}\0" \ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ "consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ diff --git a/include/crypto/sha2.h b/include/crypto/sha2.h new file mode 100644 index 0000000000..1d787e16d9 --- /dev/null +++ b/include/crypto/sha2.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common values for SHA-2 algorithms + * + * Copyright 2022 NXP + */ + +#ifndef _CRYPTO_SHA2_H +#define _CRYPTO_SHA2_H + +#include <linux/types.h> + +#define SHA256_DIGEST_SIZE 32 +#define SHA256_BLOCK_SIZE 64 + +#define SHA256_H0 0x6a09e667UL +#define SHA256_H1 0xbb67ae85UL +#define SHA256_H2 0x3c6ef372UL +#define SHA256_H3 0xa54ff53aUL +#define SHA256_H4 0x510e527fUL +#define SHA256_H5 0x9b05688cUL +#define SHA256_H6 0x1f83d9abUL +#define SHA256_H7 0x5be0cd19UL + +struct sha256_state { + uint32_t state[SHA256_DIGEST_SIZE / 4]; + uint64_t count; + uint8_t buf[SHA256_BLOCK_SIZE]; +}; + +/* + * Stand-alone implementation of the SHA256 algorithm. + */ + +static inline void sha256_init(struct sha256_state *sctx) +{ + sctx->state[0] = SHA256_H0; + sctx->state[1] = SHA256_H1; + sctx->state[2] = SHA256_H2; + sctx->state[3] = SHA256_H3; + sctx->state[4] = SHA256_H4; + sctx->state[5] = SHA256_H5; + sctx->state[6] = SHA256_H6; + sctx->state[7] = SHA256_H7; + sctx->count = 0; +} + +void sha256_ce(const unsigned char *data, unsigned int ilen, unsigned char *output); + +#endif /* _CRYPTO_SHA2_H */ diff --git a/include/crypto/sha256_base.h b/include/crypto/sha256_base.h new file mode 100644 index 0000000000..f36a7929b3 --- /dev/null +++ b/include/crypto/sha256_base.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha256_base.h - core logic for SHA-256 implementations + * + * Copyright (C) 2015 Linaro Ltd <ard.biesheuvel@linaro.org> + * Copyright 2022 NXP + */ + +#ifndef _CRYPTO_SHA256_BASE_H +#define _CRYPTO_SHA256_BASE_H + +#include <asm/unaligned.h> +#include <linux/string.h> +#include <compiler.h> +#include <crypto/sha2.h> + +typedef void (sha256_block_fn)(struct sha256_state *sst, u8 const *src, + int blocks); + +static inline void sha256_base_do_update(struct sha256_state *sctx, + const u8 *data, + unsigned int len, + sha256_block_fn *block_fn) +{ + unsigned int partial = sctx->count % SHA256_BLOCK_SIZE; + + sctx->count += len; + + if ((partial + len) >= SHA256_BLOCK_SIZE) { + int blocks; + + if (partial) { + int p = SHA256_BLOCK_SIZE - partial; + + memcpy(sctx->buf + partial, data, p); + data += p; + len -= p; + + block_fn(sctx, sctx->buf, 1); + } + + blocks = len / SHA256_BLOCK_SIZE; + len %= SHA256_BLOCK_SIZE; + + if (blocks) { + block_fn(sctx, data, blocks); + data += blocks * SHA256_BLOCK_SIZE; + } + partial = 0; + } + if (len) + memcpy(sctx->buf + partial, data, len); +} + +static inline void sha256_base_do_finalize(struct sha256_state *sctx, + sha256_block_fn *block_fn) +{ + const int bit_offset = SHA256_BLOCK_SIZE - sizeof(__be64); + __be64 *bits = (__be64 *)(sctx->buf + bit_offset); + unsigned int partial = sctx->count % SHA256_BLOCK_SIZE; + + sctx->buf[partial++] = 0x80; + if (partial > bit_offset) { + memset(sctx->buf + partial, 0x0, SHA256_BLOCK_SIZE - partial); + partial = 0; + + block_fn(sctx, sctx->buf, 1); + } + + memset(sctx->buf + partial, 0x0, bit_offset - partial); + *bits = cpu_to_be64(sctx->count << 3); + block_fn(sctx, sctx->buf, 1); +} + +static inline void sha256_base_finish(struct sha256_state *sctx, u8 *out) +{ + unsigned int digest_size = SHA256_DIGEST_SIZE; + __be32 *digest = (__be32 *)out; + int i; + + for (i = 0; digest_size > 0; i++, digest_size -= sizeof(__be32)) + put_unaligned_be32(sctx->state[i], digest++); + + memset(sctx, 0x0, sizeof(*sctx)); +} + +#endif /* _CRYPTO_SHA256_BASE_H */ diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h new file mode 100644 index 0000000000..4ea6864b41 --- /dev/null +++ b/include/dt-bindings/clock/imx93-clock.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H +#define __DT_BINDINGS_CLOCK_IMX93_CLK_H + +#define IMX93_CLK_DUMMY 0 +#define IMX93_CLK_24M 1 +#define IMX93_CLK_EXT1 2 +#define IMX93_CLK_SYS_PLL_PFD0 3 +#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 +#define IMX93_CLK_SYS_PLL_PFD1 5 +#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 +#define IMX93_CLK_SYS_PLL_PFD2 7 +#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 +#define IMX93_CLK_AUDIO_PLL 9 +#define IMX93_CLK_VIDEO_PLL 10 +#define IMX93_CLK_A55_PERIPH 11 +#define IMX93_CLK_A55_MTR_BUS 12 +#define IMX93_CLK_A55 13 +#define IMX93_CLK_M33 14 +#define IMX93_CLK_BUS_WAKEUP 15 +#define IMX93_CLK_BUS_AON 16 +#define IMX93_CLK_WAKEUP_AXI 17 +#define IMX93_CLK_SWO_TRACE 18 +#define IMX93_CLK_M33_SYSTICK 19 +#define IMX93_CLK_FLEXIO1 20 +#define IMX93_CLK_FLEXIO2 21 +#define IMX93_CLK_LPIT1 22 +#define IMX93_CLK_LPIT2 23 +#define IMX93_CLK_LPTMR1 24 +#define IMX93_CLK_LPTMR2 25 +#define IMX93_CLK_TPM1 26 +#define IMX93_CLK_TPM2 27 +#define IMX93_CLK_TPM3 28 +#define IMX93_CLK_TPM4 29 +#define IMX93_CLK_TPM5 30 +#define IMX93_CLK_TPM6 31 +#define IMX93_CLK_FLEXSPI1 32 +#define IMX93_CLK_CAN1 33 +#define IMX93_CLK_CAN2 34 +#define IMX93_CLK_LPUART1 35 +#define IMX93_CLK_LPUART2 36 +#define IMX93_CLK_LPUART3 37 +#define IMX93_CLK_LPUART4 38 +#define IMX93_CLK_LPUART5 39 +#define IMX93_CLK_LPUART6 40 +#define IMX93_CLK_LPUART7 41 +#define IMX93_CLK_LPUART8 42 +#define IMX93_CLK_LPI2C1 43 +#define IMX93_CLK_LPI2C2 44 +#define IMX93_CLK_LPI2C3 45 +#define IMX93_CLK_LPI2C4 46 +#define IMX93_CLK_LPI2C5 47 +#define IMX93_CLK_LPI2C6 48 +#define IMX93_CLK_LPI2C7 49 +#define IMX93_CLK_LPI2C8 50 +#define IMX93_CLK_LPSPI1 51 +#define IMX93_CLK_LPSPI2 52 +#define IMX93_CLK_LPSPI3 53 +#define IMX93_CLK_LPSPI4 54 +#define IMX93_CLK_LPSPI5 55 +#define IMX93_CLK_LPSPI6 56 +#define IMX93_CLK_LPSPI7 57 +#define IMX93_CLK_LPSPI8 58 +#define IMX93_CLK_I3C1 59 +#define IMX93_CLK_I3C2 60 +#define IMX93_CLK_USDHC1 61 +#define IMX93_CLK_USDHC2 62 +#define IMX93_CLK_USDHC3 63 +#define IMX93_CLK_SAI1 64 +#define IMX93_CLK_SAI2 65 +#define IMX93_CLK_SAI3 66 +#define IMX93_CLK_CCM_CKO1 67 +#define IMX93_CLK_CCM_CKO2 68 +#define IMX93_CLK_CCM_CKO3 69 +#define IMX93_CLK_CCM_CKO4 70 +#define IMX93_CLK_HSIO 71 +#define IMX93_CLK_HSIO_USB_TEST_60M 72 +#define IMX93_CLK_HSIO_ACSCAN_80M 73 +#define IMX93_CLK_HSIO_ACSCAN_480M 74 +#define IMX93_CLK_ML_APB 75 +#define IMX93_CLK_ML 76 +#define IMX93_CLK_MEDIA_AXI 77 +#define IMX93_CLK_MEDIA_APB 78 +#define IMX93_CLK_MEDIA_LDB 79 +#define IMX93_CLK_MEDIA_DISP_PIX 80 +#define IMX93_CLK_CAM_PIX 81 +#define IMX93_CLK_MIPI_TEST_BYTE 82 +#define IMX93_CLK_MIPI_PHY_CFG 83 +#define IMX93_CLK_ADC 84 +#define IMX93_CLK_PDM 85 +#define IMX93_CLK_TSTMR1 86 +#define IMX93_CLK_TSTMR2 87 +#define IMX93_CLK_MQS1 88 +#define IMX93_CLK_MQS2 89 +#define IMX93_CLK_AUDIO_XCVR 90 +#define IMX93_CLK_SPDIF 91 +#define IMX93_CLK_ENET 92 +#define IMX93_CLK_ENET_TIMER1 93 +#define IMX93_CLK_ENET_TIMER2 94 +#define IMX93_CLK_ENET_REF 95 +#define IMX93_CLK_ENET_REF_PHY 96 +#define IMX93_CLK_I3C1_SLOW 97 +#define IMX93_CLK_I3C2_SLOW 98 +#define IMX93_CLK_USB_PHY_BURUNIN 99 +#define IMX93_CLK_PAL_CAME_SCAN 100 +#define IMX93_CLK_A55_GATE 101 +#define IMX93_CLK_CM33_GATE 102 +#define IMX93_CLK_ADC1_GATE 103 +#define IMX93_CLK_WDOG1_GATE 104 +#define IMX93_CLK_WDOG2_GATE 105 +#define IMX93_CLK_WDOG3_GATE 106 +#define IMX93_CLK_WDOG4_GATE 107 +#define IMX93_CLK_WDOG5_GATE 108 +#define IMX93_CLK_SEMA1_GATE 109 +#define IMX93_CLK_SEMA2_GATE 110 +#define IMX93_CLK_MU_A_GATE 111 +#define IMX93_CLK_MU_B_GATE 112 +#define IMX93_CLK_EDMA1_GATE 113 +#define IMX93_CLK_EDMA2_GATE 114 +#define IMX93_CLK_FLEXSPI1_GATE 115 +#define IMX93_CLK_GPIO1_GATE 116 +#define IMX93_CLK_GPIO2_GATE 117 +#define IMX93_CLK_GPIO3_GATE 118 +#define IMX93_CLK_GPIO4_GATE 119 +#define IMX93_CLK_FLEXIO1_GATE 120 +#define IMX93_CLK_FLEXIO2_GATE 121 +#define IMX93_CLK_LPIT1_GATE 122 +#define IMX93_CLK_LPIT2_GATE 123 +#define IMX93_CLK_LPTMR1_GATE 124 +#define IMX93_CLK_LPTMR2_GATE 125 +#define IMX93_CLK_TPM1_GATE 126 +#define IMX93_CLK_TPM2_GATE 127 +#define IMX93_CLK_TPM3_GATE 128 +#define IMX93_CLK_TPM4_GATE 129 +#define IMX93_CLK_TPM5_GATE 130 +#define IMX93_CLK_TPM6_GATE 131 +#define IMX93_CLK_CAN1_GATE 132 +#define IMX93_CLK_CAN2_GATE 133 +#define IMX93_CLK_LPUART1_GATE 134 +#define IMX93_CLK_LPUART2_GATE 135 +#define IMX93_CLK_LPUART3_GATE 136 +#define IMX93_CLK_LPUART4_GATE 137 +#define IMX93_CLK_LPUART5_GATE 138 +#define IMX93_CLK_LPUART6_GATE 139 +#define IMX93_CLK_LPUART7_GATE 140 +#define IMX93_CLK_LPUART8_GATE 141 +#define IMX93_CLK_LPI2C1_GATE 142 +#define IMX93_CLK_LPI2C2_GATE 143 +#define IMX93_CLK_LPI2C3_GATE 144 +#define IMX93_CLK_LPI2C4_GATE 145 +#define IMX93_CLK_LPI2C5_GATE 146 +#define IMX93_CLK_LPI2C6_GATE 147 +#define IMX93_CLK_LPI2C7_GATE 148 +#define IMX93_CLK_LPI2C8_GATE 149 +#define IMX93_CLK_LPSPI1_GATE 150 +#define IMX93_CLK_LPSPI2_GATE 151 +#define IMX93_CLK_LPSPI3_GATE 152 +#define IMX93_CLK_LPSPI4_GATE 153 +#define IMX93_CLK_LPSPI5_GATE 154 +#define IMX93_CLK_LPSPI6_GATE 155 +#define IMX93_CLK_LPSPI7_GATE 156 +#define IMX93_CLK_LPSPI8_GATE 157 +#define IMX93_CLK_I3C1_GATE 158 +#define IMX93_CLK_I3C2_GATE 159 +#define IMX93_CLK_USDHC1_GATE 160 +#define IMX93_CLK_USDHC2_GATE 161 +#define IMX93_CLK_USDHC3_GATE 162 +#define IMX93_CLK_SAI1_GATE 163 +#define IMX93_CLK_SAI2_GATE 164 +#define IMX93_CLK_SAI3_GATE 165 +#define IMX93_CLK_MIPI_CSI_GATE 166 +#define IMX93_CLK_MIPI_DSI_GATE 167 +#define IMX93_CLK_LVDS_GATE 168 +#define IMX93_CLK_LCDIF_GATE 169 +#define IMX93_CLK_PXP_GATE 170 +#define IMX93_CLK_ISI_GATE 171 +#define IMX93_CLK_NIC_MEDIA_GATE 172 +#define IMX93_CLK_USB_CONTROLLER_GATE 173 +#define IMX93_CLK_USB_TEST_60M_GATE 174 +#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 +#define IMX93_CLK_PDM_GATE 176 +#define IMX93_CLK_MQS1_GATE 177 +#define IMX93_CLK_MQS2_GATE 178 +#define IMX93_CLK_AUD_XCVR_GATE 179 +#define IMX93_CLK_SPDIF_GATE 180 +#define IMX93_CLK_HSIO_32K_GATE 181 +#define IMX93_CLK_ENET1_GATE 182 +#define IMX93_CLK_ENET_QOS_GATE 183 +#define IMX93_CLK_SYS_CNT_GATE 184 +#define IMX93_CLK_TSTMR1_GATE 185 +#define IMX93_CLK_TSTMR2_GATE 186 +#define IMX93_CLK_TMC_GATE 187 +#define IMX93_CLK_PMRO_GATE 188 +#define IMX93_CLK_32K 189 +#define IMX93_CLK_SAI1_IPG 190 +#define IMX93_CLK_SAI2_IPG 191 +#define IMX93_CLK_SAI3_IPG 192 +#define IMX93_CLK_END 193 +#endif diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h new file mode 100644 index 0000000000..6e9e0ccb90 --- /dev/null +++ b/include/dt-bindings/power/imx93-power.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_IMX93_POWER_H__ +#define __DT_BINDINGS_IMX93_POWER_H__ + +#define IMX93_POWER_DOMAIN_MLMIX 0 +#define IMX93_POWER_DOMAIN_MEDIAMIX 1 + +#define IMX93_MEDIABLK_PD_MIPI_DSI 0 +#define IMX93_MEDIABLK_PD_MIPI_CSI 1 +#define IMX93_MEDIABLK_PD_PXP 2 +#define IMX93_MEDIABLK_PD_LCDIF 3 +#define IMX93_MEDIABLK_PD_ISI 4 + +#endif diff --git a/include/efi_api.h b/include/efi_api.h index 2a31b85076..83c01085fd 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -226,10 +226,6 @@ enum efi_reset_type { EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \ 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) -#define EFI_MEMORY_ONLY_RESET_CONTROL_GUID \ - EFI_GUID(0xe20939be, 0x32d4, 0x41be, 0xa1, 0x50, \ - 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29) - struct efi_capsule_header { efi_guid_t capsule_guid; u32 header_size; @@ -1977,14 +1973,6 @@ struct efi_signature_list { EFI_GUID(0x86c77a67, 0x0b97, 0x4633, 0xa1, 0x87, \ 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7) -#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \ - EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \ - 0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47) - -#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \ - EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \ - 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f) - #define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001 #define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002 #define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004 diff --git a/include/efi_loader.h b/include/efi_loader.h index cd1f2543b2..c52ea59ec7 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -312,8 +312,6 @@ extern const efi_guid_t efi_guid_firmware_management_protocol; extern const efi_guid_t efi_esrt_guid; /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; -/* GUID of memory only reset control */ -extern const efi_guid_t efi_memory_only_reset_control_guid; extern char __efi_runtime_start[], __efi_runtime_stop[]; extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; @@ -982,6 +980,42 @@ efi_status_t efi_capsule_authenticate(const void *capsule, #define EFI_CAPSULE_DIR u"\\EFI\\UpdateCapsule\\" /** + * struct efi_fw_image - Information on firmware images updatable through + * capsule update + * + * This structure gives information about the firmware images on the platform + * which can be updated through the capsule update mechanism + * + * @image_type_id: Image GUID. Same value is to be used in the capsule + * @fw_name: Name of the firmware image + * @image_index: Image Index, same as value passed to SetImage FMP + * function + */ +struct efi_fw_image { + efi_guid_t image_type_id; + u16 *fw_name; + u8 image_index; +}; + +/** + * struct efi_capsule_update_info - Information needed for capsule updates + * + * This structure provides information needed for performing firmware + * updates. The structure needs to be initialised per platform, for all + * platforms which enable capsule updates + * + * @dfu_string: String used to populate dfu_alt_info + * @images: Pointer to an array of updatable images + */ +struct efi_capsule_update_info { + const char *dfu_string; + struct efi_fw_image *images; +}; + +extern struct efi_capsule_update_info update_info; +extern u8 num_image_type_guids; + +/** * Install the ESRT system table. * * Return: status code diff --git a/include/fb_fsl.h b/include/fb_fsl.h index 7c2d6fbc89..080ea0e44b 100644 --- a/include/fb_fsl.h +++ b/include/fb_fsl.h @@ -51,6 +51,7 @@ #endif #define FASTBOOT_PARTITION_METADATA "metadata" +#define ERASE_UBOOT_ENV "erase_uboot_env" #ifdef CONFIG_ANDROID_AB_SUPPORT #define FASTBOOT_PARTITION_BOOT_A "boot_a" diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h index 18e5cc15d6..93c996b764 100644 --- a/include/fsl_lpuart.h +++ b/include/fsl_lpuart.h @@ -5,7 +5,7 @@ */ #if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \ - defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) + defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) || defined(CONFIG_ARCH_IMX9) struct lpuart_fsl_reg32 { u32 verid; u32 param; diff --git a/include/imx_sip.h b/include/imx_sip.h index 4c549c94e9..da844fe6be 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -15,6 +15,7 @@ #define IMX_SIP_SRC 0xC2000005 #define IMX_SIP_SRC_MCU_START 0x00 #define IMX_SIP_SRC_MCU_STARTED 0x01 +#define IMX_SIP_SRC_MCU_STOP 0x02 #define IMX_SIP_FIPS_CONFIG 0xC200000D #define IMX_SIP_FIPS_CONFIG_SET 0x1 diff --git a/include/net.h b/include/net.h index b02e4f630c..444c59771f 100644 --- a/include/net.h +++ b/include/net.h @@ -397,6 +397,8 @@ struct ip_hdr { #define IP_HDR_SIZE (sizeof(struct ip_hdr)) +#define IP_MIN_FRAG_DATAGRAM_SIZE (IP_HDR_SIZE + 8) + /* * Internet Protocol (IP) + UDP header. */ diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index bcda4762d7..22b6a33a80 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -40,6 +40,12 @@ enum scmi_status_code { SCMI_PROTOCOL_ERROR = -10, }; +enum scmi_common_message_id { + SCMI_PROTOCOL_VERSION = 0x000, + SCMI_PROTOCOL_ATTRIBUTES = 0x001, + SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x002 +}; + /* * SCMI Clock Protocol */ @@ -323,4 +329,88 @@ struct scmi_power_get_state_out { u32 state; }; +/* + * SCMI Sensor protocol + */ + +enum scmi_sensor_message_id { + SCMI_SENSOR_DESCRIPTION_GET = 0x3, + SCMI_SENSOR_TRIP_POINT_NOTIFY = 0x4, + SCMI_SENSOR_TRIP_POINT_CONFIG = 0x5, + SCMI_SENSOR_READING_GET = 0x6, + SCMI_SENSOR_AXIS_DESCRIPTION_GET = 0x7, + SCMI_SENSOR_LIST_UPDATE_INTERVALS = 0x8, + SCMI_SENSOR_CONFIG_GET = 0x9, + SCMI_SENSOR_CONFIG_SET = 0xA, + SCMI_SENSOR_CONTINUOUS_UPDATE_NOTIFY = 0xB, +}; + +struct scmi_protocol_attributes_p2a_sensor { + int32_t status; + int16_t num_sensors; + uint8_t max_reqs; + uint8_t res; + uint32_t sensor_reg_low; + uint32_t sensor_reg_high; + uint32_t sensor_reg_len; +}; + +#define SCMI_MAX_STR_SIZE 16 + +struct scmi_msg_resp_attrs { + s32 min_range_low; + s32 min_range_high; + s32 max_range_low; + s32 max_range_high; +}; + +struct scmi_sensor_desc { + u32 id; + u32 attr_low; + u32 attr_high; + u8 name[SCMI_MAX_STR_SIZE]; + u32 power; + u32 resolution; + struct scmi_msg_resp_attrs scalar_attrs; +}; + +struct scmi_sensor_description_get_a2p { + uint32_t desc_index; +}; + +struct scmi_sensor_descrition_get_p2a { + int32_t status; + uint32_t num_sensor_flags; + struct scmi_sensor_desc desc[1]; +}; + +struct scmi_sensor_config_get_a2p { + uint32_t sensor_id; +}; + +struct scmi_sensor_config_get_p2a { + int32_t status; + uint32_t sensor_config; +}; + +/* + * Sensor Reading Get + */ +struct scmi_sensor_reading_get_a2p { + uint32_t sensor_id; + uint32_t flags; +}; + +struct scmi_sensor_val { + uint32_t value_low; + uint32_t value_high; + uint32_t timestap_low; + uint32_t timestap_high; +}; + +struct scmi_sensor_reading_get_p2a { + int32_t status; + struct scmi_sensor_val val; +}; + #endif /* _SCMI_PROTOCOLS_H */ diff --git a/include/video_bridge.h b/include/video_bridge.h index 3b429eac57..8b71b04a11 100644 --- a/include/video_bridge.h +++ b/include/video_bridge.h @@ -45,6 +45,17 @@ struct video_bridge_ops { int (*check_attached)(struct udevice *dev); /** + * check_timing() - check if the timing need update after the bridge device attached + * + * This method is optional - if not provided then return 0 + * + * @dev: Device to check + * @active: The timing to be checked and updated + * Return: 0 if OK, -ve on error + */ + int (*check_timing)(struct udevice *dev, struct display_timing *timing); + + /** * set_backlight() - Set the backlight brightness * * @dev: device to adjust @@ -99,6 +110,15 @@ int video_bridge_set_active(struct udevice *dev, bool active); int video_bridge_check_attached(struct udevice *dev); /** + * check_timing() - check if the timing need update after the bridge device attached + * + * @dev: Device to check + * @active: The timing to be checked and updated + * Return: 0 if OK, -ve on error + */ +int video_bridge_check_timing(struct udevice *dev, struct display_timing *timing); + +/** * video_bridge_read_edid() - Read information from EDID * * @dev: Device to read from diff --git a/lib/Kconfig b/lib/Kconfig index acd3d51bc9..a4c1175701 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -876,7 +876,7 @@ config LMB_USE_MAX_REGIONS config LMB_MAX_REGIONS int "Number of memory and reserved regions in lmb lib" depends on LMB && LMB_USE_MAX_REGIONS - default 8 + default 16 help Define the number of supported regions, memory and reserved, in the library logical memory blocks. diff --git a/lib/avb/fsl/fsl_bootctrl.c b/lib/avb/fsl/fsl_bootctrl.c index 797503a857..9b15bc9bac 100755 --- a/lib/avb/fsl/fsl_bootctrl.c +++ b/lib/avb/fsl/fsl_bootctrl.c @@ -927,10 +927,9 @@ AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, AvbOps* ops = ab_ops->ops; AvbSlotVerifyData* slot_data = NULL; AvbSlotVerifyData* data = NULL; - AvbABFlowResult ret; + AvbABFlowResult ret = 0; struct bootloader_control ab_data, ab_data_orig; AvbIOResult io_ret; - bool saw_and_allowed_verification_error = false; AvbSlotVerifyResult verify_result; bool set_slot_unbootable = false; int target_slot, n; @@ -999,8 +998,7 @@ AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " "is set.\n", NULL); - saw_and_allowed_verification_error = - true; + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; } else { set_slot_unbootable = true; } @@ -1079,13 +1077,6 @@ AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, avb_assert(slot_data != NULL); data = slot_data; slot_data = NULL; - if (saw_and_allowed_verification_error) { - avb_assert( - flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); - ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; - } else { - ret = AVB_AB_FLOW_RESULT_OK; - } out: io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); @@ -1251,11 +1242,10 @@ AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, AvbOps* ops = ab_ops->ops; AvbSlotVerifyData* slot_data[2] = {NULL, NULL}; AvbSlotVerifyData* data = NULL; - AvbABFlowResult ret; + AvbABFlowResult ret = 0; struct bootloader_control ab_data, ab_data_orig; size_t slot_index_to_boot, n; AvbIOResult io_ret; - bool saw_and_allowed_verification_error = false; size_t target_slot; AvbSlotVerifyResult verify_result; bool set_slot_unbootable = false; @@ -1324,9 +1314,8 @@ AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " "is set.\n", NULL); - saw_and_allowed_verification_error = - true; slot_index_to_boot = target_slot; + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; n = 2; } else { set_slot_unbootable = true; @@ -1414,13 +1403,6 @@ AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, avb_assert(slot_data[slot_index_to_boot] != NULL); data = slot_data[slot_index_to_boot]; slot_data[slot_index_to_boot] = NULL; - if (saw_and_allowed_verification_error) { - avb_assert( - flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); - ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; - } else { - ret = AVB_AB_FLOW_RESULT_OK; - } /* ... and decrement tries remaining, if applicable. */ if (!ab_data.slot_info[slot_index_to_boot].successful_boot && diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c index 54c677bcad..82c5c745d4 100644 --- a/lib/crypto/pkcs7_verify.c +++ b/lib/crypto/pkcs7_verify.c @@ -529,6 +529,7 @@ static int pkcs7_verify_one(struct pkcs7_message *pkcs7, if (sinfo->signing_time < sinfo->signer->valid_from || sinfo->signing_time > sinfo->signer->valid_to) { pr_warn("Message signed outside of X.509 validity window\n"); + return -EKEYREJECTED; } } diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e5e35fe51f..09fb8cbe75 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -174,6 +174,7 @@ config EFI_CAPSULE_FIRMWARE_FIT depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT select UPDATE_FIT select DFU + select SET_DFU_ALT_INFO select EFI_CAPSULE_FIRMWARE help Select this option if you want to enable firmware management protocol @@ -185,6 +186,7 @@ config EFI_CAPSULE_FIRMWARE_RAW depends on SANDBOX || (!SANDBOX && !EFI_CAPSULE_FIRMWARE_FIT) select DFU_WRITE_ALT select DFU + select SET_DFU_ALT_INFO select EFI_CAPSULE_FIRMWARE help Select this option if you want to enable firmware management protocol diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index f00440163d..f03f4c9044 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -128,6 +128,7 @@ void set_capsule_result(int index, struct efi_capsule_header *capsule, /** * efi_fmp_find - search for Firmware Management Protocol drivers * @image_type: Image type guid + * @image_index: Image Index * @instance: Instance number * @handles: Handles of FMP drivers * @no_handles: Number of handles @@ -141,8 +142,8 @@ void set_capsule_result(int index, struct efi_capsule_header *capsule, * * NULL - on failure */ static struct efi_firmware_management_protocol * -efi_fmp_find(efi_guid_t *image_type, u64 instance, efi_handle_t *handles, - efi_uintn_t no_handles) +efi_fmp_find(efi_guid_t *image_type, u8 image_index, u64 instance, + efi_handle_t *handles, efi_uintn_t no_handles) { efi_handle_t *handle; struct efi_firmware_management_protocol *fmp; @@ -203,6 +204,7 @@ efi_fmp_find(efi_guid_t *image_type, u64 instance, efi_handle_t *handles, log_debug("+++ desc[%d] index: %d, name: %ls\n", j, desc->image_index, desc->image_id_name); if (!guidcmp(&desc->image_type_id, image_type) && + (desc->image_index == image_index) && (!instance || !desc->hardware_instance || desc->hardware_instance == instance)) @@ -449,8 +451,8 @@ static efi_status_t efi_capsule_update_firmware( } /* find a device for update firmware */ - /* TODO: should we pass index as well, or nothing but type? */ fmp = efi_fmp_find(&image->update_image_type_id, + image->update_image_index, image->update_hardware_instance, handles, no_handles); if (!fmp) { diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index a5ff32f121..27953fe769 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -35,6 +35,11 @@ struct fmp_payload_header { u32 lowest_supported_version; }; +__weak void set_dfu_alt_info(char *interface, char *devstr) +{ + env_set("dfu_alt_info", update_info.dfu_string); +} + /* Place holder; not supported */ static efi_status_t EFIAPI efi_firmware_get_image_unsupported( @@ -97,91 +102,57 @@ efi_status_t EFIAPI efi_firmware_set_package_info_unsupported( } /** - * efi_get_dfu_info - return information about the current firmware image - * @this: Protocol instance + * efi_fill_image_desc_array - populate image descriptor array * @image_info_size: Size of @image_info * @image_info: Image information * @descriptor_version: Pointer to version number - * @descriptor_count: Pointer to number of descriptors + * @descriptor_count: Image count * @descriptor_size: Pointer to descriptor size - * package_version: Package version - * package_version_name: Package version's name - * image_type: Image type GUID + * @package_version: Package version + * @package_version_name: Package version's name * - * Return information bout the current firmware image in @image_info. + * Return information about the current firmware image in @image_info. * @image_info will consist of a number of descriptors. - * Each descriptor will be created based on "dfu_alt_info" variable. + * Each descriptor will be created based on efi_fw_image array. * * Return status code */ -static efi_status_t efi_get_dfu_info( +static efi_status_t efi_fill_image_desc_array( efi_uintn_t *image_info_size, struct efi_firmware_image_descriptor *image_info, u32 *descriptor_version, u8 *descriptor_count, efi_uintn_t *descriptor_size, u32 *package_version, - u16 **package_version_name, - const efi_guid_t *image_type) + u16 **package_version_name) { - struct dfu_entity *dfu; - size_t names_len, total_size; - int dfu_num, i; - u16 *name, *next; - int ret; - - ret = dfu_init_env_entities(NULL, NULL); - if (ret) - return EFI_SUCCESS; - - names_len = 0; - dfu_num = 0; - list_for_each_entry(dfu, &dfu_list, list) { - names_len += (utf8_utf16_strlen(dfu->name) + 1) * 2; - dfu_num++; - } - if (!dfu_num) { - log_warning("No entities in dfu_alt_info\n"); - *image_info_size = 0; - dfu_free_entities(); + size_t total_size; + struct efi_fw_image *fw_array; + int i; - return EFI_SUCCESS; - } + fw_array = update_info.images; + *descriptor_count = num_image_type_guids; + + total_size = sizeof(*image_info) * num_image_type_guids; - total_size = sizeof(*image_info) * dfu_num + names_len; - /* - * we will assume that sizeof(*image_info) * dfu_name - * is, at least, a multiple of 2. So the start address for - * image_id_name would be aligned with 2 bytes. - */ if (*image_info_size < total_size) { *image_info_size = total_size; - dfu_free_entities(); return EFI_BUFFER_TOO_SMALL; } *image_info_size = total_size; *descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION; - *descriptor_count = dfu_num; *descriptor_size = sizeof(*image_info); *package_version = 0xffffffff; /* not supported */ *package_version_name = NULL; /* not supported */ - /* DFU alt number should correspond to image_index */ - i = 0; - /* Name area starts just after descriptors */ - name = (u16 *)((u8 *)image_info + sizeof(*image_info) * dfu_num); - next = name; - list_for_each_entry(dfu, &dfu_list, list) { - image_info[i].image_index = dfu->alt + 1; - image_info[i].image_type_id = *image_type; - image_info[i].image_id = dfu->alt; - - /* copy the DFU entity name */ - utf8_utf16_strcpy(&next, dfu->name); - image_info[i].image_id_name = name; - name = ++next; + for (i = 0; i < num_image_type_guids; i++) { + image_info[i].image_index = fw_array[i].image_index; + image_info[i].image_type_id = fw_array[i].image_type_id; + image_info[i].image_id = fw_array[i].image_index; + + image_info[i].image_id_name = fw_array[i].fw_name; image_info[i].version = 0; /* not supported */ image_info[i].version_name = NULL; /* not supported */ @@ -202,12 +173,8 @@ static efi_status_t efi_get_dfu_info( image_info[i].last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS; image_info[i].hardware_instance = 1; image_info[i].dependencies = NULL; - - i++; } - dfu_free_entities(); - return EFI_SUCCESS; } @@ -220,8 +187,6 @@ static efi_status_t efi_get_dfu_info( * - versioning of firmware image * - package information */ -const efi_guid_t efi_firmware_image_type_uboot_fit = - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID; /** * efi_firmware_fit_get_image_info - return information about the current @@ -267,11 +232,10 @@ efi_status_t EFIAPI efi_firmware_fit_get_image_info( !descriptor_size || !package_version || !package_version_name)) return EFI_EXIT(EFI_INVALID_PARAMETER); - ret = efi_get_dfu_info(image_info_size, image_info, - descriptor_version, descriptor_count, - descriptor_size, - package_version, package_version_name, - &efi_firmware_image_type_uboot_fit); + ret = efi_fill_image_desc_array(image_info_size, image_info, + descriptor_version, descriptor_count, + descriptor_size, package_version, + package_version_name); return EFI_EXIT(ret); } @@ -329,8 +293,6 @@ const struct efi_firmware_management_protocol efi_fmp_fit = { * This FIRMWARE_MANAGEMENT_PROTOCOL driver provides a firmware update * method with raw data. */ -const efi_guid_t efi_firmware_image_type_uboot_raw = - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID; /** * efi_firmware_raw_get_image_info - return information about the current @@ -376,11 +338,10 @@ efi_status_t EFIAPI efi_firmware_raw_get_image_info( !descriptor_size || !package_version || !package_version_name)) return EFI_EXIT(EFI_INVALID_PARAMETER); - ret = efi_get_dfu_info(image_info_size, image_info, - descriptor_version, descriptor_count, - descriptor_size, - package_version, package_version_name, - &efi_firmware_image_type_uboot_raw); + ret = efi_fill_image_desc_array(image_info_size, image_info, + descriptor_version, descriptor_count, + descriptor_size, package_version, + package_version_name); return EFI_EXIT(ret); } diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index b7b9aea6d3..9611398885 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -27,7 +27,6 @@ const efi_guid_t efi_guid_loaded_image_device_path = const efi_guid_t efi_simple_file_system_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID; -const efi_guid_t efi_memory_only_reset_control_guid = EFI_MEMORY_ONLY_RESET_CONTROL_GUID; static int machines[] = { #if defined(__aarch64__) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 366c219f53..eee54e4878 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -8,16 +8,12 @@ #define LOG_CATEGORY LOGC_EFI #include <common.h> -#include <mapmem.h> #include <efi_loader.h> #include <efi_variable.h> #include <log.h> -#include <asm/global_data.h> #define OBJ_LIST_NOT_INITIALIZED 1 -DECLARE_GLOBAL_DATA_PTR; - efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED; /* @@ -180,68 +176,6 @@ static efi_status_t efi_init_os_indications(void) /** - * efi_init_memory_only_reset_control() - indicate supported features for - * OS requests - * - * Set the MemoryOverwriteRequestControl variable. - * - * Return: status code - */ -static efi_status_t efi_init_memory_only_reset_control(void) -{ - u8 memory_only_reset_control = 0; - efi_status_t ret; - efi_uintn_t data_size = 0; - - data_size = sizeof(memory_only_reset_control); - ret = efi_get_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - NULL, &data_size, - &memory_only_reset_control, NULL); - if (ret == EFI_SUCCESS) { - if (memory_only_reset_control & 0x01) { - struct bd_info *bd = gd->bd; - int i; - void *start, *buf; - ulong count; - - memory_only_reset_control = memory_only_reset_control & (~(0x01)); - ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS | - EFI_VARIABLE_NON_VOLATILE, - sizeof(memory_only_reset_control), - &memory_only_reset_control, 0); - - for (i = CONFIG_NR_DRAM_BANKS - 1; i > 0; --i) { - count = bd->bi_dram[i].size; - if (!count) - continue; - start = map_sysmem(bd->bi_dram[i].start, count); - buf = start; - while (count > 0) { - *((u8 *)buf) = 0; - buf += 1; - count--; - } - unmap_sysmem(start); - } - } - return ret; - } - - ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS | - EFI_VARIABLE_NON_VOLATILE, - sizeof(memory_only_reset_control), - &memory_only_reset_control, 0); - return ret; -} - -/** * efi_init_obj_list() - Initialize and populate EFI object list * * Return: status code @@ -292,11 +226,6 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; - /* Platform Reset Attack features */ - ret = efi_init_memory_only_reset_control(); - if (ret != EFI_SUCCESS) - goto out; - /* Initialize system table */ ret = efi_initialize_system_table(); if (ret != EFI_SUCCESS) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index b255d3acc0..a90d51624e 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -55,7 +55,7 @@ static lbaint_t write_sparse_chunk_raw(struct sparse_storage *info, void *data, char *response) { - lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 100; + lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 4096; uint32_t *aligned_buf = NULL; if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_mem.c b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c index 56d8348d3c..890dbe48bc 100644 --- a/lib/trusty/ql-tipc/arch/arm/trusty_mem.c +++ b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c @@ -97,7 +97,7 @@ static void arm64_write_ATS1ExW(uint64_t vaddr) break; case 0x3: default: - trusty_fatal("Unsupported execution state: EL%u\n", _current_el ); + trusty_fatal("Unsupported execution state: EL%lu\n", _current_el ); break; } diff --git a/lib/trusty/ql-tipc/keymaster.c b/lib/trusty/ql-tipc/keymaster.c index d3957b853b..282cb53cdb 100644 --- a/lib/trusty/ql-tipc/keymaster.c +++ b/lib/trusty/ql-tipc/keymaster.c @@ -247,7 +247,7 @@ static int km_get_version(int32_t *version) rc = km_send_request(KM_GET_VERSION, NULL, 0); if (rc < 0) { - trusty_error("failed to send km version request", rc); + trusty_error("failed (%d) to send km version request", rc); return rc; } @@ -524,7 +524,7 @@ int trusty_get_mppubk(uint8_t *mppubk, uint32_t *size) rc = km_send_request(KM_GET_MPPUBK, NULL, 0); if (rc < 0) { - trusty_error("failed to send km mppubk request\n", rc); + trusty_error("%s: failed (%d) to send km mppubk request\n", __func__, rc); return rc; } @@ -586,6 +586,7 @@ int trusty_set_attestation_id(void) { uint8_t *req = NULL, *tmp = NULL; uint32_t req_size = 0; + char *serial = NULL; int rc; req = trusty_calloc(1024, 1); // 1024 bytes buffer should be enough. @@ -620,10 +621,14 @@ int trusty_set_attestation_id(void) } /* serial number, bail out when fail because it's a MUST. */ - char *serial = get_serial(); - if (serial) - km_attestation_id_data_serialize((uint8_t *)serial, 16, &tmp, &req_size); - else { + serial = get_serial(); + if (serial != NULL) { + rc = km_attestation_id_data_serialize((uint8_t *)serial, 16, &tmp, &req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to set id serial.\n", __func__, rc); + goto end; + } + } else { trusty_error("%s: failed to get serial number.\n", __func__); goto end; } @@ -685,6 +690,11 @@ int trusty_set_boot_patch_level(uint32_t boot_patch_level) int rc; req = trusty_calloc(4, 1); // 4 bytes should be enough. + if (!req) { + trusty_error("trusty_calloc memory failed!\n"); + return -1; + } + memcpy(req, &boot_patch_level, sizeof(uint32_t)); req_size = sizeof(uint32_t); diff --git a/lib/trusty/ql-tipc/rpmb_proxy.c b/lib/trusty/ql-tipc/rpmb_proxy.c index 3c9d8ee36d..74ce4b32e8 100644 --- a/lib/trusty/ql-tipc/rpmb_proxy.c +++ b/lib/trusty/ql-tipc/rpmb_proxy.c @@ -252,7 +252,7 @@ static int proxy_handle_rpmb(struct trusty_ipc_chan *chan, if (req->write_size) { if ((req->write_size % MMC_BLOCK_SIZE) != 0) { - trusty_error("%: invalid write size %u\n", __func__, + trusty_error("%s: invalid write size %u\n", __func__, req->write_size); msg->result = STORAGE_ERR_NOT_VALID; goto err_response; diff --git a/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c index 934286cb69..cf15bf77b0 100644 --- a/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c +++ b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c @@ -74,7 +74,7 @@ int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data, if (rel_write_size) { if (rel_write_size % MMC_BLOCK_SIZE) { trusty_error( - "rel_write_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + "rel_write_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", rel_write_size); ret = TRUSTY_ERR_INVALID_ARGS; goto end; @@ -90,7 +90,7 @@ int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data, } if (write_size) { if (write_size % MMC_BLOCK_SIZE) { - trusty_error("write_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + trusty_error("write_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", write_size); ret = TRUSTY_ERR_INVALID_ARGS; goto end; @@ -105,7 +105,7 @@ int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data, } if (read_size) { if (read_size % MMC_BLOCK_SIZE) { - trusty_error("read_size is not a multiple of MMC_BLOCK_SIZE: %d\n", + trusty_error("read_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", read_size); ret = TRUSTY_ERR_INVALID_ARGS; goto end; @@ -907,6 +907,9 @@ static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp) int offset8, start, len, done = 0; u16 ip_off = ntohs(ip->ip_off); + if (ip->ip_len < IP_MIN_FRAG_DATAGRAM_SIZE) + return NULL; + /* payload starts after IP header, this fragment is in there */ payload = (struct hole *)(pkt_buff + IP_HDR_SIZE); offset8 = (ip_off & IP_OFFS); diff --git a/scripts/dtc/pylibfdt/Makefile b/scripts/dtc/pylibfdt/Makefile index 493995e303..a7579f0c5f 100644 --- a/scripts/dtc/pylibfdt/Makefile +++ b/scripts/dtc/pylibfdt/Makefile @@ -17,7 +17,7 @@ quiet_cmd_pymod = PYMOD $@ cmd_pymod = unset CROSS_COMPILE; unset CFLAGS; \ CC="$(HOSTCC)" LDSHARED="$(HOSTCC) -shared " \ LDFLAGS="$(HOSTLDFLAGS)" \ - VERSION="u-boot-$(UBOOTVERSION)" \ + VERSION="$(UBOOTVERSION)" \ CPPFLAGS="$(HOSTCFLAGS) -I$(LIBFDT_srcdir)" OBJDIR=$(obj) \ SOURCES="$(PYLIBFDT_srcs)" \ SWIG_OPTS="-I$(LIBFDT_srcdir) -I$(LIBFDT_srcdir)/.." \ diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index 9076087a12..d757415c88 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -72,7 +72,7 @@ def efi_capsule_data(request, u_boot_config): # Create capsule files # two regions: one for u-boot.bin and the other for u-boot.env - check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir, + check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir, shell=True) check_call('sed -e \"s?BINFILE1?u-boot.bin.new?\" -e \"s?BINFILE2?u-boot.env.new?\" %s/test/py/tests/test_efi_capsule/uboot_bin_env.its > %s/uboot_bin_env.its' % (u_boot_config.source_dir, data_dir), @@ -80,21 +80,29 @@ def efi_capsule_data(request, u_boot_config): check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its uboot_bin_env.itb' % (data_dir, u_boot_config.build_dir), shell=True) - check_call('cd %s; %s/tools/mkeficapsule --index 1 --fit uboot_bin_env.itb Test01' % + check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test01' % (data_dir, u_boot_config.build_dir), shell=True) - check_call('cd %s; %s/tools/mkeficapsule --index 1 --raw u-boot.bin.new Test02' % + check_call('cd %s; %s/tools/mkeficapsule --index 2 --guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test02' % (data_dir, u_boot_config.build_dir), shell=True) - check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid E2BB9C06-70E9-4B14-97A3-5A7913176E3F u-boot.bin.new Test03' % + check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 u-boot.bin.new Test03' % (data_dir, u_boot_config.build_dir), shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test04' % + (data_dir, u_boot_config.build_dir), + shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' % + (data_dir, u_boot_config.build_dir), + shell=True) + if capsule_auth_enabled: # firmware signed with proper key check_call('cd %s; ' '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' '--private-key SIGNER.key --certificate SIGNER.crt ' - '--raw u-boot.bin.new Test11' + '--guid 09D7DF52-0720-4710-91D1-08469B7FE9C8 ' + 'u-boot.bin.new Test11' % (data_dir, u_boot_config.build_dir), shell=True) # firmware signed with *mal* key @@ -102,7 +110,8 @@ def efi_capsule_data(request, u_boot_config): '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' '--private-key SIGNER2.key ' '--certificate SIGNER2.crt ' - '--raw u-boot.bin.new Test12' + '--guid 09D7DF52-0720-4710-91D1-08469B7FE9C8 ' + 'u-boot.bin.new Test12' % (data_dir, u_boot_config.build_dir), shell=True) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py new file mode 100644 index 0000000000..5bef84958b --- /dev/null +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2020, Linaro Limited +# Author: AKASHI Takahiro <takahiro.akashi@linaro.org> +# +# U-Boot UEFI: Firmware Update Test + +""" +This test verifies capsule-on-disk firmware update for FIT images +""" + +from subprocess import check_call, check_output, CalledProcessError +import pytest +from capsule_defs import * + + +@pytest.mark.boardspec('sandbox64') +@pytest.mark.boardspec('sandbox_flattree') +@pytest.mark.buildconfigspec('efi_capsule_firmware_fit') +@pytest.mark.buildconfigspec('efi_capsule_on_disk') +@pytest.mark.buildconfigspec('dfu') +@pytest.mark.buildconfigspec('dfu_sf') +@pytest.mark.buildconfigspec('cmd_efidebug') +@pytest.mark.buildconfigspec('cmd_fat') +@pytest.mark.buildconfigspec('cmd_memory') +@pytest.mark.buildconfigspec('cmd_nvedit_efi') +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.slow +class TestEfiCapsuleFirmwareFit(object): + def test_efi_capsule_fw1( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ + Test Case 1 - Update U-Boot and U-Boot environment on SPI Flash + but with an incorrect GUID value in the capsule + No update should happen + 0x100000-0x150000: U-Boot binary (but dummy) + 0x150000-0x200000: U-Boot environment (but dummy) + """ + # other tests might have run and the + # system might not be in a clean state. + # Restart before starting the tests. + u_boot_console.restart_uboot() + + disk_img = efi_capsule_data + with u_boot_console.log.section('Test Case 1-a, before reboot'): + output = u_boot_console.run_command_list([ + 'host bind 0 %s' % disk_img, + 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', + 'efidebug boot order 1', + 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', + 'env save']) + + # initialize contents + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, + 'sf write 4000000 100000 10', + 'sf read 5000000 100000 10', + 'md.b 5000000 10']) + assert 'Old' in ''.join(output) + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, + 'sf write 4000000 150000 10', + 'sf read 5000000 150000 10', + 'md.b 5000000 10']) + assert 'Old' in ''.join(output) + + # place a capsule file + output = u_boot_console.run_command_list([ + 'fatload host 0:1 4000000 %s/Test05' % CAPSULE_DATA_DIR, + 'fatwrite host 0:1 4000000 %s/Test05 $filesize' % CAPSULE_INSTALL_DIR, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test05' in ''.join(output) + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + capsule_auth = u_boot_config.buildconfig.get( + 'config_efi_capsule_authenticate') + + # reboot + u_boot_console.restart_uboot(expect_reset = capsule_early) + + with u_boot_console.log.section('Test Case 1-b, after reboot'): + if not capsule_early: + # make sure that dfu_alt_info exists even persistent variables + # are not available. + output = u_boot_console.run_command_list([ + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', + 'host bind 0 %s' % disk_img, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test05' in ''.join(output) + + # need to run uefi command to initiate capsule handling + output = u_boot_console.run_command( + 'env print -e Capsule0000', wait_for_reboot = True) + + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'sf read 4000000 100000 10', + 'md.b 4000000 10']) + assert 'u-boot:Old' in ''.join(output) + + output = u_boot_console.run_command_list([ + 'sf read 4000000 150000 10', + 'md.b 4000000 10']) + assert 'u-boot-env:Old' in ''.join(output) + + def test_efi_capsule_fw2( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ + Test Case 2 - Update U-Boot and U-Boot environment on SPI Flash + 0x100000-0x150000: U-Boot binary (but dummy) + 0x150000-0x200000: U-Boot environment (but dummy) + """ + disk_img = efi_capsule_data + with u_boot_console.log.section('Test Case 2-a, before reboot'): + output = u_boot_console.run_command_list([ + 'host bind 0 %s' % disk_img, + 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', + 'efidebug boot order 1', + 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', + 'env save']) + + # initialize contents + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, + 'sf write 4000000 100000 10', + 'sf read 5000000 100000 10', + 'md.b 5000000 10']) + assert 'Old' in ''.join(output) + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, + 'sf write 4000000 150000 10', + 'sf read 5000000 150000 10', + 'md.b 5000000 10']) + assert 'Old' in ''.join(output) + + # place a capsule file + output = u_boot_console.run_command_list([ + 'fatload host 0:1 4000000 %s/Test04' % CAPSULE_DATA_DIR, + 'fatwrite host 0:1 4000000 %s/Test04 $filesize' % CAPSULE_INSTALL_DIR, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test04' in ''.join(output) + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + capsule_auth = u_boot_config.buildconfig.get( + 'config_efi_capsule_authenticate') + + # reboot + u_boot_console.restart_uboot(expect_reset = capsule_early) + + with u_boot_console.log.section('Test Case 2-b, after reboot'): + if not capsule_early: + # make sure that dfu_alt_info exists even persistent variables + # are not available. + output = u_boot_console.run_command_list([ + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', + 'host bind 0 %s' % disk_img, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test04' in ''.join(output) + + # need to run uefi command to initiate capsule handling + output = u_boot_console.run_command( + 'env print -e Capsule0000', wait_for_reboot = True) + + output = u_boot_console.run_command_list([ + 'host bind 0 %s' % disk_img, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test04' not in ''.join(output) + + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'sf read 4000000 100000 10', + 'md.b 4000000 10']) + if capsule_auth: + assert 'u-boot:Old' in ''.join(output) + else: + assert 'u-boot:New' in ''.join(output) + + output = u_boot_console.run_command_list([ + 'sf read 4000000 150000 10', + 'md.b 4000000 10']) + if capsule_auth: + assert 'u-boot-env:Old' in ''.join(output) + else: + assert 'u-boot-env:New' in ''.join(output) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py index 1dcf1c70f4..ae99f080ff 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py @@ -5,7 +5,7 @@ # U-Boot UEFI: Firmware Update Test """ -This test verifies capsule-on-disk firmware update +This test verifies capsule-on-disk firmware update for raw images """ from subprocess import check_call, check_output, CalledProcessError @@ -14,7 +14,6 @@ from capsule_defs import * @pytest.mark.boardspec('sandbox') -@pytest.mark.buildconfigspec('efi_capsule_firmware_fit') @pytest.mark.buildconfigspec('efi_capsule_firmware_raw') @pytest.mark.buildconfigspec('efi_capsule_on_disk') @pytest.mark.buildconfigspec('dfu') @@ -25,23 +24,29 @@ from capsule_defs import * @pytest.mark.buildconfigspec('cmd_nvedit_efi') @pytest.mark.buildconfigspec('cmd_sf') @pytest.mark.slow -class TestEfiCapsuleFirmwareFit(object): +class TestEfiCapsuleFirmwareRaw(object): def test_efi_capsule_fw1( self, u_boot_config, u_boot_console, efi_capsule_data): """ Test Case 1 - Update U-Boot and U-Boot environment on SPI Flash - but with OsIndications unset + but with an incorrect GUID value in the capsule No update should happen 0x100000-0x150000: U-Boot binary (but dummy) 0x150000-0x200000: U-Boot environment (but dummy) """ + + # other tests might have run and the + # system might not be in a clean state. + # Restart before starting the tests. + u_boot_console.restart_uboot() + disk_img = efi_capsule_data with u_boot_console.log.section('Test Case 1-a, before reboot'): output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', 'efidebug boot order 1', - 'env set -e OsIndications', + 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'env save']) @@ -63,16 +68,17 @@ class TestEfiCapsuleFirmwareFit(object): # place a capsule file output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR, + 'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR, + 'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) + assert 'Test03' in ''.join(output) # reboot u_boot_console.restart_uboot() capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 1-b, after reboot'): if not capsule_early: # make sure that dfu_alt_info exists even persistent variables @@ -81,16 +87,11 @@ class TestEfiCapsuleFirmwareFit(object): 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'host bind 0 %s' % disk_img, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) + assert 'Test03' in ''.join(output) # need to run uefi command to initiate capsule handling output = u_boot_console.run_command( - 'env print -e Capsule0000') - - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) + 'env print -e Capsule0000', wait_for_reboot = True) output = u_boot_console.run_command_list([ 'sf probe 0:0', @@ -107,6 +108,8 @@ class TestEfiCapsuleFirmwareFit(object): self, u_boot_config, u_boot_console, efi_capsule_data): """ Test Case 2 - Update U-Boot and U-Boot environment on SPI Flash + but with OsIndications unset + No update should happen 0x100000-0x150000: U-Boot binary (but dummy) 0x150000-0x200000: U-Boot environment (but dummy) """ @@ -116,7 +119,7 @@ class TestEfiCapsuleFirmwareFit(object): 'host bind 0 %s' % disk_img, 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', + 'env set -e OsIndications', 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'env save']) @@ -136,21 +139,24 @@ class TestEfiCapsuleFirmwareFit(object): 'md.b 5000000 10']) assert 'Old' in ''.join(output) - # place a capsule file + # place the capsule files output = u_boot_console.run_command_list([ 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR, 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) assert 'Test01' in ''.join(output) - capsule_early = u_boot_config.buildconfig.get( - 'config_efi_capsule_on_disk_early') - capsule_auth = u_boot_config.buildconfig.get( - 'config_efi_capsule_authenticate') + output = u_boot_console.run_command_list([ + 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, + 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test02' in ''.join(output) # reboot - u_boot_console.restart_uboot(expect_reset = capsule_early) + u_boot_console.restart_uboot() + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 2-b, after reboot'): if not capsule_early: # make sure that dfu_alt_info exists even persistent variables @@ -160,32 +166,28 @@ class TestEfiCapsuleFirmwareFit(object): 'host bind 0 %s' % disk_img, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) assert 'Test01' in ''.join(output) + assert 'Test02' in ''.join(output) # need to run uefi command to initiate capsule handling output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + 'env print -e Capsule0000') output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' not in ''.join(output) + assert 'Test01' in ''.join(output) + assert 'Test02' in ''.join(output) output = u_boot_console.run_command_list([ 'sf probe 0:0', 'sf read 4000000 100000 10', 'md.b 4000000 10']) - if capsule_auth: - assert 'u-boot:Old' in ''.join(output) - else: - assert 'u-boot:New' in ''.join(output) + assert 'u-boot:Old' in ''.join(output) output = u_boot_console.run_command_list([ 'sf read 4000000 150000 10', 'md.b 4000000 10']) - if capsule_auth: - assert 'u-boot-env:Old' in ''.join(output) - else: - assert 'u-boot-env:New' in ''.join(output) + assert 'u-boot-env:Old' in ''.join(output) def test_efi_capsule_fw3( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -203,7 +205,7 @@ class TestEfiCapsuleFirmwareFit(object): 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'env save']) - # initialize content + # initialize contents output = u_boot_console.run_command_list([ 'sf probe 0:0', 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, @@ -212,7 +214,21 @@ class TestEfiCapsuleFirmwareFit(object): 'md.b 5000000 10']) assert 'Old' in ''.join(output) - # place a capsule file + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, + 'sf write 4000000 150000 10', + 'sf read 5000000 100000 10', + 'md.b 5000000 10']) + assert 'Old' in ''.join(output) + + # place the capsule files + output = u_boot_console.run_command_list([ + 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR, + 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR, + 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test01' in ''.join(output) + output = u_boot_console.run_command_list([ 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR, @@ -235,6 +251,7 @@ class TestEfiCapsuleFirmwareFit(object): 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'host bind 0 %s' % disk_img, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test01' in ''.join(output) assert 'Test02' in ''.join(output) # need to run uefi command to initiate capsule handling @@ -246,15 +263,16 @@ class TestEfiCapsuleFirmwareFit(object): 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', 'efidebug capsule esrt']) - # ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID is in the ESRT. - assert 'AE13FF2D-9AD4-4E25-9AC8-6D80B3B22147' in ''.join(output) + # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. + assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) - # ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID is in the ESRT. - assert 'E2BB9C06-70E9-4B14-97A3-5A7913176E3F' in ''.join(output) + # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. + assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) output = u_boot_console.run_command_list([ 'host bind 0 %s' % disk_img, 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) + assert 'Test01' not in ''.join(output) assert 'Test02' not in ''.join(output) output = u_boot_console.run_command_list([ @@ -266,78 +284,11 @@ class TestEfiCapsuleFirmwareFit(object): else: assert 'u-boot:New' in ''.join(output) - def test_efi_capsule_fw4( - self, u_boot_config, u_boot_console, efi_capsule_data): - """ - Test Case 4 - Test "--guid" option of mkeficapsule - The test scenario is the same as Case 3. - """ - disk_img = efi_capsule_data - with u_boot_console.log.section('Test Case 4-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content output = u_boot_console.run_command_list([ 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test03' in ''.join(output) - - capsule_early = u_boot_config.buildconfig.get( - 'config_efi_capsule_on_disk_early') - capsule_auth = u_boot_config.buildconfig.get( - 'config_efi_capsule_authenticate') - - # reboot - u_boot_console.restart_uboot(expect_reset = capsule_early) - - with u_boot_console.log.section('Test Case 4-b, after reboot'): - if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test03' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) - - # make sure the dfu_alt_info exists because it is required for making ESRT. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'efidebug capsule esrt']) - - # ensure that EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID is in the ESRT. - assert 'E2BB9C06-70E9-4B14-97A3-5A7913176E3F' in ''.join(output) - - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test03' not in ''.join(output) - - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', + 'sf read 4000000 150000 10', 'md.b 4000000 10']) if capsule_auth: - assert 'u-boot:Old' in ''.join(output) + assert 'u-boot-env:Old' in ''.join(output) else: - assert 'u-boot:New' in ''.join(output) + assert 'u-boot-env:New' in ''.join(output) diff --git a/tools/.gitignore b/tools/.gitignore index a88453f64d..5b7b13330d 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -28,6 +28,7 @@ /mxsboot /ncb /prelink-riscv +/printinitialenv /proftool /relocate-rela /spl_size_limit diff --git a/tools/Makefile b/tools/Makefile index 60231c728c..10dce12f62 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -264,6 +264,10 @@ clean-dirs := lib common always := $(hostprogs-y) +# Host tool to dump the currently configured default environment, +# build it on demand, i.e. not add it to 'always'. +hostprogs-y += printinitialenv + # Generated LCD/video logo LOGO_H = $(objtree)/include/bmp_logo.h LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h diff --git a/tools/eficapsule.h b/tools/eficapsule.h index 69c9c58c2f..d63b831443 100644 --- a/tools/eficapsule.h +++ b/tools/eficapsule.h @@ -37,14 +37,6 @@ typedef struct { EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \ 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) -#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \ - EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \ - 0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47) - -#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \ - EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \ - 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f) - #define EFI_CERT_TYPE_PKCS7_GUID \ EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \ 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7) diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index c118335b93..5f74d23b9e 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -27,17 +27,11 @@ static const char *tool_name = "mkeficapsule"; efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID; -efi_guid_t efi_guid_image_type_uboot_fit = - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID; -efi_guid_t efi_guid_image_type_uboot_raw = - EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID; efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID; -static const char *opts_short = "frg:i:I:v:p:c:m:dh"; +static const char *opts_short = "g:i:I:v:p:c:m:dh"; static struct option options[] = { - {"fit", no_argument, NULL, 'f'}, - {"raw", no_argument, NULL, 'r'}, {"guid", required_argument, NULL, 'g'}, {"index", required_argument, NULL, 'i'}, {"instance", required_argument, NULL, 'I'}, @@ -54,8 +48,6 @@ static void print_usage(void) fprintf(stderr, "Usage: %s [options] <image blob> <output file>\n" "Options:\n" - "\t-f, --fit FIT image type\n" - "\t-r, --raw raw image type\n" "\t-g, --guid <guid string> guid for image blob type\n" "\t-i, --index <index> update image index\n" "\t-I, --instance <instance> update hardware instance\n" @@ -606,22 +598,6 @@ int main(int argc, char **argv) break; switch (c) { - case 'f': - if (guid) { - fprintf(stderr, - "Image type already specified\n"); - exit(EXIT_FAILURE); - } - guid = &efi_guid_image_type_uboot_fit; - break; - case 'r': - if (guid) { - fprintf(stderr, - "Image type already specified\n"); - exit(EXIT_FAILURE); - } - guid = &efi_guid_image_type_uboot_raw; - break; case 'g': if (guid) { fprintf(stderr, diff --git a/tools/printinitialenv.c b/tools/printinitialenv.c new file mode 100644 index 0000000000..c58b234d67 --- /dev/null +++ b/tools/printinitialenv.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 + * Max Krummenacher, Toradex + * + * Snippets taken from tools/env/fw_env.c + * + * This prints the list of default environment variables as currently + * configured. + * + */ + +#include <stdio.h> + +/* Pull in the current config to define the default environment */ +#include <linux/kconfig.h> + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* get only #defines from config.h */ +#include <config.h> +#undef __ASSEMBLY__ +#else +#include <config.h> +#endif + +#define DEFAULT_ENV_INSTANCE_STATIC +#include <generated/environment.h> +#include <env_default.h> + +int main(void) +{ + char *env, *nxt; + + for (env = default_environment; *env; env = nxt + 1) { + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &default_environment[sizeof(default_environment)]) { + fprintf(stderr, "## Error: environment not terminated\n"); + return -1; + } + } + printf("%s\n", env); + } + return 0; +} |