diff options
| -rw-r--r-- | arch/arm/dts/imx7ulp-evk-emmc.dts | 10 | ||||
| -rw-r--r-- | arch/arm/dts/imx7ulp-evk-qspi.dts | 16 |
2 files changed, 17 insertions, 9 deletions
diff --git a/arch/arm/dts/imx7ulp-evk-emmc.dts b/arch/arm/dts/imx7ulp-evk-emmc.dts index a795228175..9407d198c3 100644 --- a/arch/arm/dts/imx7ulp-evk-emmc.dts +++ b/arch/arm/dts/imx7ulp-evk-emmc.dts @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -8,10 +9,17 @@ #include "imx7ulp-evk-qspi.dts" +/* To support eMMC HS200/HS400, need to do the following reowrk: + * 1,remove TF sd slot, replace eMMC chip + * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89 + * 3,add R107, make eMMC boot work + */ &usdhc0 { - pinctrl-names = "default", "sleep"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0_8bit>; pinctrl-1 = <&pinctrl_usdhc0_8bit>; + pinctrl-2 = <&pinctrl_usdhc0_8bit>; + pinctrl-3 = <&pinctrl_usdhc0_8bit>; non-removable; bus-width = <8>; status = "okay"; diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts index 404120c7ea..eb28ad1c0e 100644 --- a/arch/arm/dts/imx7ulp-evk-qspi.dts +++ b/arch/arm/dts/imx7ulp-evk-qspi.dts @@ -31,14 +31,14 @@ imx7ulp-evk { pinctrl_qspi1_1: qspi1grp_1 { fsl,pins = < - ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x43 /* SS1 */ - ULP1_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ - ULP1_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ - ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x43 /* DQS */ - ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x43 /* D3 */ - ULP1_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ - ULP1_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ - ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x43 /* D0 */ + IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x43 /* SS1 */ + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + IMX7ULP_PAD_PTB9__QSPIA_DQS 0x43 /* DQS */ + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ >; }; }; |