diff options
94 files changed, 2127 insertions, 802 deletions
diff --git a/.gitignore b/.gitignore index f980ae6f703..2e1c8bf2bf2 100644 --- a/.gitignore +++ b/.gitignore @@ -7,6 +7,7 @@ # .* *.a +*.asn1.[ch] *.bin *.cfgout *.dtb @@ -20,6 +20,8 @@ Allen Martin <amartin@nvidia.com> Andreas Bießmann <andreas.devel@googlemail.com> Andreas Bießmann <andreas@biessmann.org> Aneesh V <aneesh@ti.com> +Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> +Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> Dirk Behme <dirk.behme@googlemail.com> Fabio Estevam <fabio.estevam@nxp.com> Jagan Teki <402jagan@gmail.com> @@ -27,6 +29,7 @@ Jagan Teki <jaganna@gmail.com> Jagan Teki <jaganna@xilinx.com> Jagan Teki <jagannadh.teki@gmail.com> Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> +Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> Markus Klotzbuecher <mk@denx.de> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> Prabhakar Kushwaha <prabhakar@freescale.com> diff --git a/Documentation/.gitignore b/Documentation/.gitignore deleted file mode 100644 index 0d20b6487c6..00000000000 --- a/Documentation/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.pyc diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt deleted file mode 100644 index cfc376bc977..00000000000 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ /dev/null @@ -1,66 +0,0 @@ -The following properties are common to the Ethernet controllers: - -NOTE: All 'phy*' properties documented below are Ethernet specific. For the -generic PHY 'phys' property, see -Documentation/devicetree/bindings/phy/phy-bindings.txt. - -- local-mac-address: array of 6 bytes, specifies the MAC address that was - assigned to the network device; -- mac-address: array of 6 bytes, specifies the MAC address that was last used by - the boot program; should be used in cases where the MAC address assigned to - the device by the boot program is different from the "local-mac-address" - property; -- nvmem-cells: phandle, reference to an nvmem node for the MAC address; -- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; -- max-speed: number, specifies maximum speed in Mbit/s supported by the device; -- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than - the maximum frame size (there's contradiction in the Devicetree - Specification). -- phy-mode: string, operation mode of the PHY interface. This is now a de-facto - standard property; supported values are: - * "internal" - * "mii" - * "gmii" - * "sgmii" - * "qsgmii" - * "tbi" - * "rev-mii" - * "rmii" - * "rgmii" (RX and TX delays are added by the MAC when required) - * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the - MAC should not add the RX or TX delays in this case) - * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC - should not add an RX delay in this case) - * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC - should not add an TX delay in this case) - * "rtbi" - * "smii" - * "xgmii" - * "trgmii" - * "2000base-x", - * "2500base-x", - * "rxaui" - * "xaui" - * "10gbase-kr" (10GBASE-KR, XFI, SFI) -- phy-connection-type: the same as "phy-mode" property but described in the - Devicetree Specification; -- phy-handle: phandle, specifies a reference to a node representing a PHY - device; this property is described in the Devicetree Specification and so - preferred; -- phy: the same as "phy-handle" property, not recommended for new bindings. -- phy-device: the same as "phy-handle" property, not recommended for new - bindings. -- rx-fifo-depth: the size of the controller's receive fifo in bytes. This - is used for components that can have configurable receive fifo sizes, - and is useful for determining certain configuration settings such as - flow control thresholds. -- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This - is used for components that can have configurable fifo sizes. -- managed: string, specifies the PHY management type. Supported values are: - "auto", "in-band-status". "auto" is the default, it usess MDIO for - management if fixed-link is not specified. - -Child nodes of the Ethernet controller are typically the individual PHY devices -connected via the MDIO bus (sometimes the MDIO bus controller is separate). -They are described in the phy.txt file in this same directory. -For non-MDIO PHY management see fixed-link.txt. diff --git a/MAINTAINERS b/MAINTAINERS index 8d588b7d641..438fb225ab0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -883,6 +883,8 @@ M: Marek Vasut <marex@denx.de> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git F: drivers/usb/ +F: common/usb.c +F: common/usb_kbd.c USB xHCI M: Bin Meng <bmeng.cn@gmail.com> @@ -3,7 +3,7 @@ VERSION = 2020 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = NAME = # *DOCUMENTATION* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea1..36c9c2fecd0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -17,7 +17,7 @@ config POSITION_INDEPENDENT be loaded to and run from that address. This option lifts that restriction, thus allowing the code to be loaded to and executed from almost any address. This logic relies on the relocation - information that is embedded into the binary to support U-Boot + information that is embedded in the binary to support U-Boot relocating itself to the top-of-RAM later during execution. config INIT_SP_RELATIVE @@ -26,7 +26,7 @@ config INIT_SP_RELATIVE U-Boot typically uses a hard-coded value for the stack pointer before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses - into U-Boot, so that can be loaded and executed at arbitrary + into U-Boot, so that it can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. If this option is enabled, the early stack pointer is set to @@ -57,7 +57,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE hex help The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the - TEXT_OFFSET value written in to the Linux kernel image header. + TEXT_OFFSET value written to the Linux kernel image header. endif endif @@ -121,7 +121,7 @@ config SYS_ARM_MMU select SYS_ARM_CACHE_CP15 help Select if you want MMU-based virtualised addressing space - support by paged memory management. + support via paged memory management. config SYS_ARM_MPU bool 'Use the ARM v7 PMSA Compliant MPU' @@ -136,8 +136,8 @@ config SYS_ARM_MPU # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in # the Linux kernel. Do not set these options unless they apply! Also note that -# the following can be machine specific errata. These do have ability to -# provide rudimentary version and machine specific checks, but expect no +# the following can be machine-specific errata. These do have ability to +# provide rudimentary version and machine-specific checks, but expect no # product checks: # CONFIG_ARM_ERRATA_430973 # CONFIG_ARM_ERRATA_454179 @@ -332,7 +332,7 @@ config SYS_CACHELINE_SIZE config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help - Some architectures require a call to arch_cpu_init() + Some architectures require a call to arch_cpu_init(). Say Y here to enable it config SYS_ARCH_TIMER @@ -342,7 +342,7 @@ config SYS_ARCH_TIMER help The ARM Generic Timer (aka arch-timer) provides an architected interface to a timer source on an SoC. - It is mandantory for ARMv8 implementation and widely available + It is mandatory for ARMv8 implementation and widely available on ARMv7 systems. config ARM_SMCCC @@ -385,7 +385,7 @@ config TPL_SYS_THUMB_BUILD default y if SYS_THUMB_BUILD depends on TPL && !ARM64 help - Use this flag to build SPL using the Thumb instruction set for + Use this flag to build TPL using the Thumb instruction set for ARM architectures. Thumb instruction set provides better code density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. @@ -394,7 +394,7 @@ config TPL_SYS_THUMB_BUILD config SYS_L2CACHE_OFF bool "L2cache off" help - If SoC does not support L2CACHE or one do not want to enable + If SoC does not support L2CACHE or one does not want to enable L2CACHE, choose this option. config ENABLE_ARM_SOC_BOOT0_HOOK @@ -414,7 +414,7 @@ config USE_ARCH_MEMCPY depends on !ARM64 help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMCPY @@ -423,7 +423,7 @@ config SPL_USE_ARCH_MEMCPY depends on !ARM64 && SPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMCPY @@ -432,7 +432,7 @@ config TPL_USE_ARCH_MEMCPY depends on !ARM64 && TPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config USE_ARCH_MEMSET @@ -441,7 +441,7 @@ config USE_ARCH_MEMSET depends on !ARM64 help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMSET @@ -450,7 +450,7 @@ config SPL_USE_ARCH_MEMSET depends on !ARM64 && SPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMSET @@ -459,7 +459,7 @@ config TPL_USE_ARCH_MEMSET depends on !ARM64 && TPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SET_STACK_SIZE @@ -467,14 +467,14 @@ config SET_STACK_SIZE default y if ARCH_VERSAL || ARCH_ZYNQMP help This will enable an option to set max stack size that can be - used by u-boot. + used by U-Boot. config STACK_SIZE - hex "Define max stack size that can be used by u-boot" + hex "Define max stack size that can be used by U-Boot" depends on SET_STACK_SIZE default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP help - Defines Max stack size that can be used by u-boot so that the + Define Max stack size that can be used by U-Boot so that the initrd_high will be calculated as base stack pointer minus this stack size. @@ -689,7 +689,7 @@ config TARGET_BCMNS2 help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking - applications + applications. config ARCH_EXYNOS bool "Samsung EXYNOS" @@ -1101,8 +1101,8 @@ config TARGET_LS2080A_EMU select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH help - Support for Freescale LS2080A_EMU platform - The LS2080A Development System (EMULATOR) is a pre silicon + Support for Freescale LS2080A_EMU platform. + The LS2080A Development System (EMULATOR) is a pre-silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1114,7 +1114,7 @@ config TARGET_LS2080A_SIMU select ARMV8_MULTIENTRY select BOARD_LATE_INIT help - Support for Freescale LS2080A_SIMU platform + Support for Freescale LS2080A_SIMU platform. The LS2080A Development System (QDS) is a pre silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1130,7 +1130,7 @@ config TARGET_LS1088AQDS select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help - Support for NXP LS1088AQDS platform + Support for NXP LS1088AQDS platform. The LS1088A Development System (QDS) is a high-performance development platform that supports the QorIQ LS1088A Layerscape Architecture processor. @@ -1149,7 +1149,7 @@ config TARGET_LS2080AQDS select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL help - Support for Freescale LS2080AQDS platform + Support for Freescale LS2080AQDS platform. The LS2080A Development System (QDS) is a high-performance development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1649,7 +1649,7 @@ config TFABOOT default n help Enabling this will make a U-Boot binary that is capable of being - booted via TF-A. + booted via TF-A (Trusted Firmware for Cortex-A). config TI_SECURE_DEVICE bool "HS Device Type Support" diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 2c5d99e9acd..5b689004e89 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -75,7 +75,7 @@ static void __secure __mdelay(u32 ms) isb(); } -static void __secure clamp_release(u32 __maybe_unused *clamp) +static void __secure clamp_release(void __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ defined(CONFIG_MACH_SUN8I_H3) || \ @@ -90,7 +90,7 @@ static void __secure clamp_release(u32 __maybe_unused *clamp) #endif } -static void __secure clamp_set(u32 __maybe_unused *clamp) +static void __secure clamp_set(void __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ defined(CONFIG_MACH_SUN8I_H3) || \ @@ -99,22 +99,28 @@ static void __secure clamp_set(u32 __maybe_unused *clamp) #endif } -static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, +static void __secure sunxi_power_switch(void *clamp, void *pwroff_ptr, bool on, int cpu) { + u32 pwroff; + + memcpy(&pwroff, pwroff_ptr, sizeof(u32)); + if (on) { /* Release power clamp */ clamp_release(clamp); /* Clear power gating */ - clrbits_le32(pwroff, BIT(cpu)); + clrbits_le32(&pwroff, BIT(cpu)); } else { /* Set power gating */ - setbits_le32(pwroff, BIT(cpu)); + setbits_le32(&pwroff, BIT(cpu)); /* Activate power clamp */ clamp_set(clamp); } + + memcpy(pwroff_ptr, &pwroff, sizeof(u32)); } #ifdef CONFIG_MACH_SUN8I_R40 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3dc9c4d41c8..0127a91a820 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -68,7 +68,8 @@ dtb-$(CONFIG_ARCH_OWL) += \ bubblegum_96.dtb dtb-$(CONFIG_ROCKCHIP_PX30) += \ - px30-evb.dtb + px30-evb.dtb \ + px30-firefly.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb @@ -522,7 +523,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts index e1738b6dde3..a63fc2da22b 100644 --- a/arch/arm/dts/am335x-brsmarc1.dts +++ b/arch/arm/dts/am335x-brsmarc1.dts @@ -266,12 +266,14 @@ }; &cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; phy-handle = <ðphy0>; phy-mode = "rmii"; ti,ledcr = <0x0480>; }; &cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; phy-handle = <ðphy1>; phy-mode = "rmii"; ti,ledcr = <0x0480>; diff --git a/arch/arm/dts/am335x-brxre1.dts b/arch/arm/dts/am335x-brxre1.dts index a0d046d07a1..33d8ab78d8e 100644 --- a/arch/arm/dts/am335x-brxre1.dts +++ b/arch/arm/dts/am335x-brxre1.dts @@ -221,11 +221,13 @@ }; &cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; phy-handle = <ðphy0>; phy-mode = "mii"; }; &cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; phy-handle = <ðphy1>; phy-mode = "mii"; }; diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi index 135b6193a9d..5ac32a0ffaa 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.1.0 - * This file was generated on 09/06/2019 + * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.2.0 + * This file was generated on 10/09/2019 */ #define DDRSS_PLL_FHS_CNT 10 @@ -283,7 +283,7 @@ #define DDRSS_CTL_271_DATA 0x1FFF1000 #define DDRSS_CTL_272_DATA 0x01FF0000 #define DDRSS_CTL_273_DATA 0x000101FF -#define DDRSS_CTL_274_DATA 0xFFFF0B00 +#define DDRSS_CTL_274_DATA 0x0FFF0B00 #define DDRSS_CTL_275_DATA 0x01010001 #define DDRSS_CTL_276_DATA 0x01010101 #define DDRSS_CTL_277_DATA 0x01180101 diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi new file mode 100644 index 00000000000..bb782b4e2df --- /dev/null +++ b/arch/arm/dts/px30-firefly-u-boot.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart5 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&xin24m { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&pmucru { + u-boot,dm-pre-reloc; +}; + +&saradc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/px30-firefly.dts b/arch/arm/dts/px30-firefly.dts new file mode 100644 index 00000000000..c0a8e3009ad --- /dev/null +++ b/arch/arm/dts/px30-firefly.dts @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "px30.dtsi" + +/ { + model = "Firefly Core-PX30-JD4"; + compatible = "rockchip,px30-firefly", "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + esc-key { + label = "esc"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1310000>; + }; + + home-key { + label = "home"; + linux,code = <KEY_HOME>; + press-threshold-microvolt = <624000>; + }; + + menu-key { + label = "menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + label = "volume up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + power-supply = <&vcc3v3_lcd>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "sitronix,st7703"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v0>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_rmii>; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0>; + clock-output-names = "xin32k"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name = "vcc2v8_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name = "vcc1v5_dvp"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vccio_flash>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <800>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index ffbd657e314..6d5b3ec06e0 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -51,8 +51,14 @@ &emmc { u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + u-boot,spl-fifo-mode; }; &sdmmc { u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + u-boot,spl-fifo-mode; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts new file mode 100644 index 00000000000..f2f7b7a9257 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 Jagan Teki <jteki@openedev.com> + * Copyright (C) 2018 Diego Rondini <diego.rondini@kynetics.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "OrangePi Zero Plus2 H3"; + compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 58a36895e6d..767d1ff98d7 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -202,7 +202,7 @@ #ifndef __ASSEMBLY__ #include <linux/compiler.h> -struct __packed sunxi_prcm_reg { +struct sunxi_prcm_reg { u32 cpus_cfg; /* 0x000 */ u8 res0[0x8]; /* 0x004 */ u32 apb0_ratio; /* 0x00c */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index fee6d56c4d1..4ce2799b72a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -113,3 +113,14 @@ config DDRMC_VF610_CALIBRATION config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" depends on IMX8MN + +config IMX_DCD_ADDR + hex "DCD Blocks location on the image" + default 0x00910000 if !ARCH_MX7ULP + default 0x2f010000 if ARCH_MX7ULP + help + Indicates where the Device Configuration Data, a binary table used by + the ROM code to configure the device at early boot stage, is located. + This information is shared with the user via mkimage -l just so the + image can be signed. + diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ef816a24ffa..1e5df9ae44a 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -424,6 +424,7 @@ config TARGET_NITROGEN6X imply USB_ETHER_MCS7830 imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER + select MX6QDL config TARGET_OPOS6ULDEV bool "Armadeus OPOS6ULDev board" diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 99edcd9a247..a78ffbb674e 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -82,6 +82,7 @@ void board_init_f(ulong dummy) ctrl_mmr_unlock(); #ifdef CONFIG_CPU_V7R + disable_linefill_optimization(); setup_k3_mpu_regions(); #endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index bf631b74f84..50f5b81dfe5 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -244,3 +244,28 @@ void board_prep_linux(bootm_headers_t *images) CONFIG_SYS_CACHELINE_SIZE)); } #endif + +#ifdef CONFIG_CPU_V7R +void disable_linefill_optimization(void) +{ + u32 actlr; + + /* + * On K3 devices there are 2 conditions where R5F can deadlock: + * 1.When software is performing series of store operations to + * cacheable write back/write allocate memory region and later + * on software execute barrier operation (DSB or DMB). R5F may + * hang at the barrier instruction. + * 2.When software is performing a mix of load and store operations + * within a tight loop and store operations are all writing to + * cacheable write back/write allocates memory regions, R5F may + * hang at one of the load instruction. + * + * To avoid the above two conditions disable linefill optimization + * inside Cortex R5F. + */ + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); + actlr |= (1 << 13); /* Set DLFO bit */ + asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 8f9a023921b..35d1609cdcd 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -16,3 +16,4 @@ void setup_k3_mpu_regions(void); int early_console_init(void); +void disable_linefill_optimization(void); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index d0bf86abeb2..47587392661 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -87,6 +87,7 @@ void board_init_f(ulong dummy) ctrl_mmr_unlock(); #ifdef CONFIG_CPU_V7R + disable_linefill_optimization(); setup_k3_mpu_regions(); #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d8d68ba4472..b689a420bdb 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -306,7 +306,7 @@ config SPL_ROCKCHIP_COMMON_BOARD no TPL for the board. config TPL_ROCKCHIP_COMMON_BOARD - bool "" + bool "Rockchip TPL common board file" depends on TPL help Rockchip SoCs have similar boot process, prefer to use TPL for DRAM diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh index 89ef04312cf..4118472d9f2 100755 --- a/arch/arm/mach-rockchip/fit_spl_optee.sh +++ b/arch/arm/mach-rockchip/fit_spl_optee.sh @@ -17,6 +17,12 @@ if [ ! -f $TEE ]; then fi dtname=$1 +text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \ + |tr -d '\r'` +dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \ + include/autoconf.mk|tr -d '\r'` +tee_base=`echo "obase=16;$(($dram_base+0x8400000))"|bc` +tee_base='0x'$tee_base cat << __HEADER_EOF /* @@ -39,7 +45,7 @@ cat << __HEADER_EOF os = "U-Boot"; arch = "arm"; compression = "none"; - load = <0x61000000>; + load = <$text_base>; }; optee { description = "OP-TEE"; @@ -48,8 +54,8 @@ cat << __HEADER_EOF arch = "arm"; os = "tee"; compression = "none"; - load = <0x68400000>; - entry = <0x68400000>; + load = <$tee_base>; + entry = <$tee_base>; }; fdt { description = "$(basename $dtname .dtb)"; diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 3c045a5e179..c79317d6c51 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 """ # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index c9bc0841949..ae28f6e2066 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -46,9 +46,8 @@ config TARGET_STM32MP1 select STM32_SERIAL select SYS_ARCH_TIMER imply BOOTCOUNT_LIMIT - imply BOOTSTAGE imply CMD_BOOTCOUNT - imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE imply PRE_CONSOLE_BUFFER imply SILENT_CONSOLE diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 33653b59495..5018167fcf1 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -57,6 +57,8 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm + #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) @@ -67,6 +69,56 @@ DECLARE_GLOBAL_DATA_PTR; #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) +/* Prevent compiler error if gpio number 08 or 09 is used */ +#define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf))) + +#define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \ + .scl = { \ + .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\ + pad_ctrl), \ + .gpio_mode = NEW_PAD_CTRL( \ + cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\ + pad_ctrl), \ + .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \ + }, \ + .sda = { \ + .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\ + pad_ctrl), \ + .gpio_mode = NEW_PAD_CTRL( \ + cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\ + pad_ctrl), \ + .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \ + } \ +} + +#define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl) \ + _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl, _IO) + +#if defined(CONFIG_MX6QDL) +#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl) \ + I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl), \ + I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl) +#define I2C_PADS_INFO_ENTRY_SPACING 2 + +#define IOMUX_PAD_CTRL(name, pad_ctrl) \ + NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \ + NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl) +#else +#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl) \ + I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \ + sda_pad, sda_bank, sda_gp, pad_ctrl) +#define I2C_PADS_INFO_ENTRY_SPACING 1 + +#define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl) +#endif + int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); @@ -75,140 +127,105 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL), }; static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C1, SGTL5000 */ -static struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } + IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL), }; -/* I2C2 Camera, MIPI */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } +static struct i2c_pads_info i2c_pads[] = { + /* I2C1, SGTL5000 */ + I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL), + /* I2C2 Camera, MIPI */ + I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, + I2C_PAD_CTRL), + /* I2C3, J15 - RGB connector */ + I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL), }; -/* I2C3, J15 - RGB connector */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; +#define I2C_BUS_CNT 3 static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */ }; static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL), + IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */ }; static iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL), + IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL), + IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL), }; static iomux_v3_cfg_t const misc_pads[] = { - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), + IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP), + IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP), + IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP), /* OTG Power enable */ - MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), + IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM), }; /* wl1271 pads on nitrogen6x */ static iomux_v3_cfg_t const wl12xx_pads[] = { - (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) - | MUX_PAD_CTRL(WEAK_PULLDOWN), - (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) - | MUX_PAD_CTRL(OUTPUT_40OHM), - (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) - | MUX_PAD_CTRL(OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), + IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), }; #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) @@ -217,17 +234,17 @@ static iomux_v3_cfg_t const wl12xx_pads[] = { /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL), /* Back */ - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL), /* Home */ - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL), /* Volume Down */ - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL), /* Volume Up */ - MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -239,7 +256,7 @@ static void setup_iomux_enet(void) gpio_direction_output(IMX_GPIO_NR(6, 27), 1); gpio_direction_output(IMX_GPIO_NR(6, 28), 1); gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + SETUP_IOMUX_PADS(enet_pads1); gpio_direction_output(IMX_GPIO_NR(6, 24), 1); /* Need delay 10ms according to KSZ9021 spec */ @@ -247,24 +264,24 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + SETUP_IOMUX_PADS(enet_pads2); udelay(100); /* Wait 100 us before using mii interface */ } static iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL), }; static void setup_iomux_uart(void) { - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + SETUP_IOMUX_PADS(uart1_pads); + SETUP_IOMUX_PADS(uart2_pads); } #ifdef CONFIG_USB_EHCI_MX6 int board_ehci_hcd_init(int port) { - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + SETUP_IOMUX_PADS(usb_pads); /* Reset USB hub */ gpio_direction_output(IMX_GPIO_NR(7, 12), 0); @@ -314,12 +331,10 @@ int board_mmc_init(bd_t *bis) for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + SETUP_IOMUX_PADS(usdhc3_pads); break; case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + SETUP_IOMUX_PADS(usdhc4_pads); break; default: printf("Warning: you configured more USDHC controllers" @@ -345,16 +360,15 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) static iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), + IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), }; static void setup_spi(void) { - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, - ARRAY_SIZE(ecspi1_pads)); + SETUP_IOMUX_PADS(ecspi1_pads); } #endif @@ -424,52 +438,51 @@ free_bus: static void setup_buttons(void) { - imx_iomux_v3_setup_multiple_pads(button_pads, - ARRAY_SIZE(button_pads)); + SETUP_IOMUX_PADS(button_pads); } #if defined(CONFIG_VIDEO_IPUV3) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DI0_PIN4__GPIO4_IO20, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, + IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL), + IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL), }; static void do_enable_hdmi(struct display_info_t const *dev) @@ -507,9 +520,7 @@ static void enable_lvds_jeida(struct display_info_t const *dev) static void enable_rgb(struct display_info_t const *dev) { - imx_iomux_v3_setup_multiple_pads( - rgb_pads, - ARRAY_SIZE(rgb_pads)); + SETUP_IOMUX_PADS(rgb_pads); gpio_direction_output(RGB_BACKLIGHT_GP, 1); } @@ -810,8 +821,7 @@ static void setup_display(void) writel(reg, &iomux->gpr[3]); /* backlights off until needed */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); + SETUP_IOMUX_PADS(backlight_pads); gpio_direction_input(LVDS_BACKLIGHT_GP); gpio_direction_input(RGB_BACKLIGHT_GP); } @@ -819,24 +829,24 @@ static void setup_display(void) static iomux_v3_cfg_t const init_pads[] = { /* SGTL5000 sys_mclk */ - NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), + IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM), /* J5 - Camera MCLK */ - NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM), + IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM), /* wl1271 pads on nitrogen6x */ /* WL12XX_WL_IRQ_GP */ - NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), + IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), /* WL12XX_WL_ENABLE_GP */ - NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), /* WL12XX_BT_ENABLE_GP */ - NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), /* USB otg power */ - NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM), - NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), - NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), - NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM), - NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM), + IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), + IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), + IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM), + IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM), }; #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) @@ -871,8 +881,8 @@ int board_early_init_f(void) set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); gpio_direction_input(WL12XX_WL_IRQ_GP); - imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); - imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); + SETUP_IOMUX_PADS(wl12xx_pads); + SETUP_IOMUX_PADS(init_pads); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) @@ -893,12 +903,20 @@ int overwrite_console(void) int board_init(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct i2c_pads_info *p = i2c_pads; + int i; + int stride = 1; +#if defined(CONFIG_MX6QDL) + stride = 2; + if (!is_mx6dq() && !is_mx6dqp()) + p += 1; +#endif clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, IOMUXC_GPR1_OTG_ID_GPIO1); - imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); + SETUP_IOMUX_PADS(misc_pads); /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; @@ -906,11 +924,11 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + SETUP_IOMUX_PADS(usdhc2_pads); + for (i = 0; i < I2C_BUS_CNT; i++) { + setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p); + p += stride; + } #ifdef CONFIG_SATA setup_sata(); diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS index 42324a3f737..16f10326612 100644 --- a/board/davinci/da8xxevm/MAINTAINERS +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -8,7 +8,7 @@ F: configs/da850evm_nand_defconfig F: configs/da850evm_direct_nor_defconfig OMAPL138_LCDK BOARD -M: Peter Howard <phoward@gme.net.au> +M: Lokesh Vutla <lokeshvutla@ti.com> S: Maintained F: include/configs/omap1l38_lcdk.h F: configs/omapl138_lcdk_defconfig diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 03ebe4e7b5c..6dca22960bf 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -136,7 +136,7 @@ struct udevice *pfuze_common_init(void) int ret; unsigned int reg, dev_id, rev_id; - ret = pmic_get("pfuze100", &dev); + ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return NULL; diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README index c1d400bcf92..4f671b069cb 100644 --- a/board/freescale/imx8mq_evk/README +++ b/board/freescale/imx8mq_evk/README @@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware ====================================== Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf -branch: imx_4.14.62_1.0.0_beta +branch: imx_4.19.35_1.0.0 $ make PLAT=imx8mq bl31 $ cp build/imx8mq/release/bl31.bin $(srctree) diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 5b6584720be..ba69c966869 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -156,29 +156,49 @@ void board_boot_order(u32 *spl_boot_list) { struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned int reg = readl(&psrc->sbmr1) >> 11; - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1-SOM - * 0x2 SD2-Baseboard - */ - - reg &= 0x3; /* Only care about bottom 2 bits */ - switch (reg) { - case 0: - spl_boot_list[0] = BOOT_DEVICE_MMC1; + u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK; + unsigned int bmode = readl(&src_base->sbmr2); + + /* If bmode is serial or USB phy is active, return serial */ + if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) { + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (boot_mode >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: + spl_boot_list[0] = BOOT_DEVICE_NAND; break; - case 1: - spl_boot_list[0] = BOOT_DEVICE_MMC2; + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1-SOM + * 0x2 SD2-Baseboard + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + switch (reg) { + case 0: + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case 1: + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + } + break; + default: + /* By default use USB downloader */ + spl_boot_list[0] = BOOT_DEVICE_BOARD; break; } - /* If we cannot find a valid MMC/SD card, try NAND */ - spl_boot_list[1] = BOOT_DEVICE_NAND; - /* As a last resort, use serial downloader */ - spl_boot_list[2] = BOOT_DEVICE_BOARD; + spl_boot_list[1] = BOOT_DEVICE_BOARD; } static void ccgr_init(void) diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index a2adf89b5d5..4a89bb0e7b7 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -405,6 +405,11 @@ M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/orangepi_zero_plus2_defconfig +ORANGEPI ZERO PLUS 2 H3 BOARD +M: Diego Rondini <diego.rondini@kynetics.com> +S: Maintained +F: configs/orangepi_zero_plus2_h3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara@arm.com> S: Maintained diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 10c595d5844..a5cd8587dad 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -83,7 +83,7 @@ iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* Colibri MMC */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -304,7 +304,7 @@ int board_ehci_hcd_init(int port) } #endif -#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 5354308b345..012c2f608eb 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_DNS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" @@ -85,6 +86,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_TI=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 1cd54f00540..70f9cc722bf 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y +CONFIG_BOOTP_DNS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" @@ -88,6 +89,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_TI=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index ba752713568..15dc7a77e55 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_DNS2=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" @@ -86,6 +87,7 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_TI=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 1fa4054f5dd..fe0ee3db9a7 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -4,20 +4,25 @@ CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x04000000 +CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL_SIZE_LIMIT=0x4b000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/fit_spl_optee.sh" CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_OPTEE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3e19135a0d2..3db40a9a1ac 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -7,7 +7,8 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK_R_ADDR=0x4000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -23,6 +24,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index fa4ac75b09f..e24f1cf8c80 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -20,7 +20,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_CONSOLE_MUX is not set -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -32,7 +32,7 @@ CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_CMD_BOOTD is not set -CONFIG_DEBUG_UART2_CHANNEL=1 +CONFIG_DEBUG_UART_CHANNEL=1 # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -53,7 +53,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_DEFAULT_DEVICE_TREE="px30-evb" +CONFIG_DEFAULT_DEVICE_TREE="px30-firefly" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 683fc225c01..33ddd6d1c46 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -186,7 +186,7 @@ CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y -CONFIG_SYSRESET_MCP83XX=y +CONFIG_SYSRESET_MPC83XX=y CONFIG_TIMER=y CONFIG_MPC83XX_TIMER=y CONFIG_TPM_ATMEL_TWI=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 1505459259d..a2af8ae7b2e 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_MX5=y CONFIG_SYS_TEXT_BASE=0x97800000 CONFIG_TARGET_MX51EVK=y CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_OFFSET=0xC0000 CONFIG_NR_DRAM_BANKS=1 # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig new file mode 100644 index 00000000000..3000a97e731 --- /dev/null +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=672 +# CONFIG_DRAM_ODT_EN is not set +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 358c2cd0799..713a7e6c571 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -132,10 +132,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_BPP8=y CONFIG_VIDEO_BPP16=y CONFIG_VIDEO_BPP32=y -CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index a065d3e0887..f9161fd7d1d 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -116,10 +116,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_BPP8=y CONFIG_VIDEO_BPP16=y CONFIG_VIDEO_BPP32=y -CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 632f11f59b8..a5ea528ae35 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -115,10 +115,10 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_BPP8=y CONFIG_VIDEO_BPP16=y CONFIG_VIDEO_BPP32=y -CONFIG_BACKLIGHT_GPIO=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/doc/README.rockchip b/doc/README.rockchip index dae4ebc8e47..9b699b9ae5d 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -50,7 +50,7 @@ Two RK3036 boards are supported: Two RK3308 boards are supported: - EVB RK3308 - use evb-rk3308 configuration - - ROC-CC-RK3308 - use roc-rk3308-cc configuration + - ROC-CC-RK3308 - use roc-cc-rk3308 configuration Two RK3328 board are supported: @@ -106,7 +106,7 @@ For example: - Compile U-Boot => cd /path/to/u-boot => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf - => make roc-rk3308-cc_defconfig + => make roc-cc-rk3308_defconfig => make CROSS_COMPILE=aarch64-linux-gnu- all => ./tools/mkimage -n rk3308 -T rksd -d /path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img => cat spl/u-boot-spl.bin >> idbloader.img @@ -340,6 +340,12 @@ You can create the image via the following operations: cat firefly-rk3288/u-boot-dtb.bin >> out && \ sudo dd if=out of=/dev/sdc seek=64 +Or: + ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \ + firefly-rk3288/spl/u-boot-spl-dtb.bin:firefly-rk3288/u-boot-dtb.bin \ + out && \ + sudo dd if=out of=/dev/sdc seek=64 + If you have an HDMI cable attached you should see a video console. For evb_rk3036 board: @@ -347,6 +353,11 @@ For evb_rk3036 board: cat evb-rk3036/u-boot-dtb.bin >> out && \ sudo dd if=out of=/dev/sdc seek=64 +Or: + ./evb-rk3036/tools/mkimage -n rk3036 -T rksd -d \ + evb-rk3036/spl/u-boot-spl.bin:evb-rk3036/u-boot-dtb.bin out && \ + sudo dd if=out of=/dev/sdc seek=64 + Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the debug uart must be disabled diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt index 3fc360523bc..cfc376bc977 100644 --- a/doc/device-tree-bindings/net/ethernet.txt +++ b/doc/device-tree-bindings/net/ethernet.txt @@ -1,25 +1,66 @@ The following properties are common to the Ethernet controllers: +NOTE: All 'phy*' properties documented below are Ethernet specific. For the +generic PHY 'phys' property, see +Documentation/devicetree/bindings/phy/phy-bindings.txt. + - local-mac-address: array of 6 bytes, specifies the MAC address that was assigned to the network device; - mac-address: array of 6 bytes, specifies the MAC address that was last used by the boot program; should be used in cases where the MAC address assigned to the device by the boot program is different from the "local-mac-address" property; +- nvmem-cells: phandle, reference to an nvmem node for the MAC address; +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; - max-speed: number, specifies maximum speed in Mbit/s supported by the device; - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than - the maximum frame size (there's contradiction in ePAPR). -- phy-mode: string, operation mode of the PHY interface; supported values are - "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id", - "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto - standard property; -- phy-connection-type: the same as "phy-mode" property but described in ePAPR; + the maximum frame size (there's contradiction in the Devicetree + Specification). +- phy-mode: string, operation mode of the PHY interface. This is now a de-facto + standard property; supported values are: + * "internal" + * "mii" + * "gmii" + * "sgmii" + * "qsgmii" + * "tbi" + * "rev-mii" + * "rmii" + * "rgmii" (RX and TX delays are added by the MAC when required) + * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the + MAC should not add the RX or TX delays in this case) + * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC + should not add an RX delay in this case) + * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC + should not add an TX delay in this case) + * "rtbi" + * "smii" + * "xgmii" + * "trgmii" + * "2000base-x", + * "2500base-x", + * "rxaui" + * "xaui" + * "10gbase-kr" (10GBASE-KR, XFI, SFI) +- phy-connection-type: the same as "phy-mode" property but described in the + Devicetree Specification; - phy-handle: phandle, specifies a reference to a node representing a PHY - device; this property is described in ePAPR and so preferred; + device; this property is described in the Devicetree Specification and so + preferred; - phy: the same as "phy-handle" property, not recommended for new bindings. - phy-device: the same as "phy-handle" property, not recommended for new bindings. +- rx-fifo-depth: the size of the controller's receive fifo in bytes. This + is used for components that can have configurable receive fifo sizes, + and is useful for determining certain configuration settings such as + flow control thresholds. +- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This + is used for components that can have configurable fifo sizes. +- managed: string, specifies the PHY management type. Supported values are: + "auto", "in-band-status". "auto" is the default, it usess MDIO for + management if fixed-link is not specified. Child nodes of the Ethernet controller are typically the individual PHY devices connected via the MDIO bus (sometimes the MDIO bus controller is separate). They are described in the phy.txt file in this same directory. +For non-MDIO PHY management see fixed-link.txt. diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index eee06517fa5..3591225a6ed 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -167,6 +167,68 @@ For RSA the following are mandatory: - rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer - rsa,n0-inverse: -1 / modulus[0] mod 2^32 +These parameters can be added to a binary device tree using parameter -K of the +mkimage command:: + + tools/mkimage -f fit.its -K control.dtb -k keys -r image.fit + +Here is an example of a generated device tree node:: + + signature { + key-dev { + required = "conf"; + algo = "sha256,rsa2048"; + rsa,r-squared = <0xb76d1acf 0xa1763ca5 0xeb2f126 + 0x742edc80 0xd3f42177 0x9741d9d9 + 0x35bb476e 0xff41c718 0xd3801430 + 0xf22537cb 0xa7e79960 0xae32a043 + 0x7da1427a 0x341d6492 0x3c2762f5 + 0xaac04726 0x5b262d96 0xf984e86d + 0xb99443c7 0x17080c33 0x940f6892 + 0xd57a95d1 0x6ea7b691 0xc5038fa8 + 0x6bb48a6e 0x73f1b1ea 0x37160841 + 0xe05715ce 0xa7c45bbd 0x690d82d5 + 0x99c2454c 0x6ff117b3 0xd830683b + 0x3f81c9cf 0x1ca38a91 0x0c3392e4 + 0xd817c625 0x7b8e9a24 0x175b89ea + 0xad79f3dc 0x4d50d7b4 0x9d4e90f8 + 0xad9e2939 0xc165d6a4 0x0ada7e1b + 0xfb1bf495 0xfc3131c2 0xb8c6e604 + 0xc2761124 0xf63de4a6 0x0e9565f9 + 0xc8e53761 0x7e7a37a5 0xe99dcdae + 0x9aff7e1e 0xbd44b13d 0x6b0e6aa4 + 0x038907e4 0x8e0d6850 0xef51bc20 + 0xf73c94af 0x88bea7b1 0xcbbb1b30 + 0xd024b7f3>; + rsa,modulus = <0xc0711d6cb 0x9e86db7f 0x45986dbe + 0x023f1e8c9 0xe1a4c4d0 0x8a0dfdc9 + 0x023ba0c48 0x06815f6a 0x5caa0654 + 0x07078c4b7 0x3d154853 0x40729023 + 0x0b007c8fe 0x5a3647e5 0x23b41e20 + 0x024720591 0x66915305 0x0e0b29b0 + 0x0de2ad30d 0x8589430f 0xb1590325 + 0x0fb9f5d5e 0x9eba752a 0xd88e6de9 + 0x056b3dcc6 0x9a6b8e61 0x6784f61f + 0x000f39c21 0x5eec6b33 0xd78e4f78 + 0x0921a305f 0xaa2cc27e 0x1ca917af + 0x06e1134f4 0xd48cac77 0x4e914d07 + 0x0f707aa5a 0x0d141f41 0x84677f1d + 0x0ad47a049 0x028aedb6 0xd5536fcf + 0x03fef1e4f 0x133a03d2 0xfd7a750a + 0x0f9159732 0xd207812e 0x6a807375 + 0x06434230d 0xc8e22dad 0x9f29b3d6 + 0x07c44ac2b 0xfa2aad88 0xe2429504 + 0x041febd41 0x85d0d142 0x7b194d65 + 0x06e5d55ea 0x41116961 0xf3181dde + 0x068bf5fbc 0x3dd82047 0x00ee647e + 0x0d7a44ab3>; + rsa,exponent = <0x00 0x10001>; + rsa,n0-inverse = <0xb3928b85>; + rsa,num-bits = <0x800>; + key-name-hint = "dev"; + }; + }; + Signed Configurations --------------------- diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index d6e915c9b9c..21af66e4e7f 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -24,7 +24,7 @@ void ddr_init(struct dram_timing_info *dram_timing) { unsigned int tmp, initial_drate, target_freq; - printf("DDRINFO: start DRAM init\n"); + debug("DDRINFO: start DRAM init\n"); /* Step1: Follow the power up procedure */ if (is_imx8mq()) { @@ -109,7 +109,7 @@ void ddr_init(struct dram_timing_info *dram_timing) tmp = reg32_read(DDRPHY_CalBusy(0)); } while ((tmp & 0x1)); - printf("DDRINFO:ddrphy calibration done\n"); + debug("DDRINFO:ddrphy calibration done\n"); /* Step15: Set SWCTL.sw_done to 0 */ reg32_write(DDRC_SWCTL(0), 0x00000000); @@ -161,7 +161,7 @@ void ddr_init(struct dram_timing_info *dram_timing) /* enable port 0 */ reg32_write(DDRC_PCTRL_0(0), 0x00000001); - printf("DDRINFO: ddrmix config done\n"); + debug("DDRINFO: ddrmix config done\n"); /* save the dram timing config into memory */ dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index c3f7b57665d..ef5cd4e7234 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -32,6 +32,10 @@ struct davinci_mmc_priv { uint input_clk; /* Input clock to MMC controller */ struct gpio_desc cd_gpio; /* Card Detect GPIO */ struct gpio_desc wp_gpio; /* Write Protect GPIO */ +}; + +struct davinci_mmc_plat +{ struct mmc_config cfg; struct mmc mmc; }; @@ -480,8 +484,9 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) static int davinci_mmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct davinci_mmc_plat *plat = dev_get_platdata(dev); struct davinci_mmc_priv *priv = dev_get_priv(dev); - struct mmc_config *cfg = &priv->cfg; + struct mmc_config *cfg = &plat->cfg; #ifdef CONFIG_SPL_BUILD int ret; #endif @@ -502,7 +507,7 @@ static int davinci_mmc_probe(struct udevice *dev) gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); #endif - upriv->mmc = &priv->mmc; + upriv->mmc = &plat->mmc; #ifdef CONFIG_SPL_BUILD /* @@ -513,7 +518,7 @@ static int davinci_mmc_probe(struct udevice *dev) * support in SPL, hence the hard-coded base register address. */ priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE; - ret = mmc_bind(dev, &priv->mmc, &priv->cfg); + ret = mmc_bind(dev, &plat->mmc, &plat->cfg); if (ret) return ret; #endif @@ -523,9 +528,9 @@ static int davinci_mmc_probe(struct udevice *dev) static int davinci_mmc_bind(struct udevice *dev) { - struct davinci_mmc_priv *priv = dev_get_priv(dev); + struct davinci_mmc_plat *plat = dev_get_platdata(dev); - return mmc_bind(dev, &priv->mmc, &priv->cfg); + return mmc_bind(dev, &plat->mmc, &plat->cfg); } static const struct udevice_id davinci_mmc_ids[] = { @@ -542,6 +547,7 @@ U_BOOT_DRIVER(davinci_mmc_drv) = { #endif .probe = davinci_mmc_probe, .ops = &davinci_mmc_ops, + .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat), .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv), }; #endif diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5a8c0842556..eb49a6c11c4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -546,6 +546,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, (long long)instr->len); + if (!instr->len) + return 0; + div_u64_rem(instr->len, mtd->erasesize, &rem); if (rem) return -EINVAL; @@ -1226,6 +1229,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); + if (!len) + return 0; + for (i = 0; i < len; ) { ssize_t written; loff_t addr = to + i; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index d3b84574ac4..973b6f86c94 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -108,6 +108,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index 615037f1a3f..11f937032f3 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -50,7 +50,7 @@ static int bcm_sf2_eth_init(struct eth_device *dev) eth->port_num = 0; debug("Connecting PHY 0...\n"); phydev = phy_connect(miiphy_get_dev_by_name(dev->name), - 0, dev, eth->phy_interface); + -1, dev, eth->phy_interface); if (phydev != NULL) { eth->port[0] = phydev; eth->port_num += 1; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index da5b696c9d8..46321116352 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1045,7 +1045,7 @@ static int eqos_start(struct udevice *dev) * don't need to reconnect/reconfigure again */ if (!eqos->phy) { - eqos->phy = phy_connect(eqos->mii, 0, dev, + eqos->phy = phy_connect(eqos->mii, -1, dev, eqos->config->interface(dev)); if (!eqos->phy) { pr_err("phy_connect() failed"); diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index e7e78e3c56d..0c59552bb86 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -41,27 +41,110 @@ #define SATA_PLL_SOFT_RESET (1<<18) /* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - +#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14) +#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 + +#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22) +#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 + +#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) +#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) + +/* PHY RX Registers */ +#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C +#define INTERFACE_MASK GENMASK(31, 27) +#define INTERFACE_SHIFT 27 +#define INTERFACE_MODE_USBSS BIT(4) +#define INTERFACE_MODE_SATA_1P5 BIT(3) +#define INTERFACE_MODE_SATA_3P0 BIT(2) +#define INTERFACE_MODE_PCIE BIT(0) + +#define LOSD_MASK GENMASK(17, 14) +#define LOSD_SHIFT 14 +#define MEM_PLLDIV GENMASK(6, 5) + +#define PIPE3_PHY_RX_TRIM 0x0000001C +#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30) +#define MEM_DLL_TRIM_SHIFT 30 + +#define PIPE3_PHY_RX_DLL 0x00000024 +#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30) +#define MEM_DLL_PHINT_RATE_SHIFT 30 + +#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028 +#define MEM_HS_RATE_MASK GENMASK(28, 27) +#define MEM_HS_RATE_SHIFT 27 +#define MEM_OVRD_HS_RATE BIT(26) +#define MEM_OVRD_HS_RATE_SHIFT 26 +#define MEM_CDR_FASTLOCK BIT(23) +#define MEM_CDR_FASTLOCK_SHIFT 23 +#define MEM_CDR_LBW_MASK GENMASK(22, 21) +#define MEM_CDR_LBW_SHIFT 21 +#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19) +#define MEM_CDR_STEPCNT_SHIFT 19 +#define MEM_CDR_STL_MASK GENMASK(18, 16) +#define MEM_CDR_STL_SHIFT 16 +#define MEM_CDR_THR_MASK GENMASK(15, 13) +#define MEM_CDR_THR_SHIFT 13 +#define MEM_CDR_THR_MODE BIT(12) +#define MEM_CDR_THR_MODE_SHIFT 12 +#define MEM_CDR_2NDO_SDM_MODE BIT(11) +#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11 + +#define PIPE3_PHY_RX_EQUALIZER 0x00000038 +#define MEM_EQLEV_MASK GENMASK(31, 16) +#define MEM_EQLEV_SHIFT 16 +#define MEM_EQFTC_MASK GENMASK(15, 11) +#define MEM_EQFTC_SHIFT 11 +#define MEM_EQCTL_MASK GENMASK(10, 7) +#define MEM_EQCTL_SHIFT 7 +#define MEM_OVRD_EQLEV BIT(2) +#define MEM_OVRD_EQLEV_SHIFT 2 +#define MEM_OVRD_EQFTC BIT(1) +#define MEM_OVRD_EQFTC_SHIFT 1 + +#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44 +#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) +#define MEM_CDR_LOS_SOURCE_SHIFT 9 #define PLL_IDLE_TIME 100 /* in milliseconds */ #define PLL_LOCK_TIME 100 /* in milliseconds */ +enum pipe3_mode { PIPE3_MODE_PCIE = 1, + PIPE3_MODE_SATA, + PIPE3_MODE_USBSS }; + +struct pipe3_settings { + u8 ana_interface; + u8 ana_losd; + u8 dig_fastlock; + u8 dig_lbw; + u8 dig_stepcnt; + u8 dig_stl; + u8 dig_thr; + u8 dig_thr_mode; + u8 dig_2ndo_sdm_mode; + u8 dig_hs_rate; + u8 dig_ovrd_hs_rate; + u8 dll_trim_sel; + u8 dll_phint_rate; + u8 eq_lev; + u8 eq_ftc; + u8 eq_ctl; + u8 eq_ovrd_lev; + u8 eq_ovrd_ftc; +}; + struct omap_pipe3 { void __iomem *pll_ctrl_base; + void __iomem *phy_rx; void __iomem *power_reg; void __iomem *pll_reset_reg; struct pipe3_dpll_map *dpll_map; + enum pipe3_mode mode; + struct pipe3_settings settings; }; - struct pipe3_dpll_params { u16 m; u8 n; @@ -75,6 +158,12 @@ struct pipe3_dpll_map { struct pipe3_dpll_params params; }; +struct pipe3_data { + enum pipe3_mode mode; + struct pipe3_dpll_map *dpll_map; + struct pipe3_settings settings; +}; + static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) { return readl(addr + offset); @@ -175,19 +264,75 @@ static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on) rate = rate/1000000; if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + writel(val, pipe3->power_reg); + + /* Power up TX before RX for SATA & USB */ + val |= PIPE3_PHY_TX_POWERON; + writel(val, pipe3->power_reg); + + val |= PIPE3_PHY_RX_POWERON; + writel(val, pipe3->power_reg); } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + writel(val, pipe3->power_reg); } +} - writel(val, pipe3->power_reg); +static void ti_pipe3_calibrate(struct omap_pipe3 *phy) +{ + u32 val; + struct pipe3_settings *s = &phy->settings; + + val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); + val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); + val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); + omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); + + val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); + val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | + MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK | + MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE); + val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | + s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | + s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | + s->dig_lbw << MEM_CDR_LBW_SHIFT | + s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | + s->dig_stl << MEM_CDR_STL_SHIFT | + s->dig_thr << MEM_CDR_THR_SHIFT | + s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | + s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; + omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); + + val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); + val &= ~MEM_DLL_TRIM_SEL_MASK; + val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; + omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); + + val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); + val &= ~MEM_DLL_PHINT_RATE_MASK; + val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; + omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); + + val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); + val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | + MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); + val |= s->eq_lev << MEM_EQLEV_SHIFT | + s->eq_ftc << MEM_EQFTC_SHIFT | + s->eq_ctl << MEM_EQCTL_SHIFT | + s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | + s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; + omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); + + if (phy->mode == PIPE3_MODE_SATA) { + val = omap_pipe3_readl(phy->phy_rx, + SATA_PHY_RX_IO_AND_A2D_OVERRIDES); + val &= ~MEM_CDR_LOS_SOURCE_MASK; + omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, + val); + } } static int pipe3_init(struct phy *phy) @@ -202,6 +347,8 @@ static int pipe3_init(struct phy *phy) ret = omap_pipe3_dpll_program(pipe3); if (ret) return ret; + + ti_pipe3_calibrate(pipe3); } else { /* else just bring it out of IDLE mode */ val = omap_pipe3_readl(pipe3->pll_ctrl_base, @@ -317,7 +464,22 @@ static int pipe3_phy_probe(struct udevice *dev) fdt_addr_t addr; fdt_size_t sz; struct omap_pipe3 *pipe3 = dev_get_priv(dev); + struct pipe3_data *data; + /* PHY_RX */ + addr = devfdt_get_addr_size_index(dev, 0, &sz); + if (addr == FDT_ADDR_T_NONE) { + pr_err("missing phy_rx address\n"); + return -EINVAL; + } + + pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE); + if (!pipe3->phy_rx) { + pr_err("unable to remap phy_rx\n"); + return -EINVAL; + } + + /* PLLCTRL */ addr = devfdt_get_addr_size_index(dev, 2, &sz); if (addr == FDT_ADDR_T_NONE) { pr_err("missing pll ctrl address\n"); @@ -334,25 +496,28 @@ static int pipe3_phy_probe(struct udevice *dev) if (!pipe3->power_reg) return -EINVAL; - if (device_is_compatible(dev, "ti,phy-pipe3-sata")) { + data = (struct pipe3_data *)dev_get_driver_data(dev); + pipe3->mode = data->mode; + pipe3->dpll_map = data->dpll_map; + pipe3->settings = data->settings; + + if (pipe3->mode == PIPE3_MODE_SATA) { pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset"); if (!pipe3->pll_reset_reg) return -EINVAL; } - pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev); - return 0; } static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ + {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ + {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ + {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ + {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ }; static struct pipe3_dpll_map dpll_map_usb[] = { @@ -365,9 +530,61 @@ static struct pipe3_dpll_map dpll_map_usb[] = { { }, /* Terminator */ }; +static struct pipe3_data data_usb = { + .mode = PIPE3_MODE_USBSS, + .dpll_map = dpll_map_usb, + .settings = { + /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */ + .ana_interface = INTERFACE_MODE_USBSS, + .ana_losd = 0xa, + .dig_fastlock = 1, + .dig_lbw = 3, + .dig_stepcnt = 0, + .dig_stl = 0x3, + .dig_thr = 1, + .dig_thr_mode = 1, + .dig_2ndo_sdm_mode = 0, + .dig_hs_rate = 0, + .dig_ovrd_hs_rate = 1, + .dll_trim_sel = 0x2, + .dll_phint_rate = 0x3, + .eq_lev = 0, + .eq_ftc = 0, + .eq_ctl = 0x9, + .eq_ovrd_lev = 0, + .eq_ovrd_ftc = 0, + }, +}; + +static struct pipe3_data data_sata = { + .mode = PIPE3_MODE_SATA, + .dpll_map = dpll_map_sata, + .settings = { + /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */ + .ana_interface = INTERFACE_MODE_SATA_3P0, + .ana_losd = 0x5, + .dig_fastlock = 1, + .dig_lbw = 3, + .dig_stepcnt = 0, + .dig_stl = 0x3, + .dig_thr = 1, + .dig_thr_mode = 1, + .dig_2ndo_sdm_mode = 0, + .dig_hs_rate = 0, /* Not in TRM preferred settings */ + .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */ + .dll_trim_sel = 0x1, + .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */ + .eq_lev = 0, + .eq_ftc = 0x1f, + .eq_ctl = 0, + .eq_ovrd_lev = 1, + .eq_ovrd_ftc = 1, + }, +}; + static const struct udevice_id pipe3_phy_ids[] = { - { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata }, - { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb}, + { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata }, + { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb}, { } }; diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index 81560e16cef..82c5185e2e5 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -349,7 +349,7 @@ void rtc_init(void) static int rx8010sj_probe(struct udevice *dev) { - rx8010sj_rtc_init(&dev); + rx8010sj_rtc_init(dev); return 0; } @@ -364,6 +364,7 @@ static const struct rtc_ops rx8010sj_rtc_ops = { static const struct udevice_id rx8010sj_rtc_ids[] = { { .compatible = "epson,rx8010sj-rtc" }, + { .compatible = "epson,rx8010" }, { } }; diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c index 844f1b72c7a..4f478ccfd72 100644 --- a/drivers/rtc/s35392a.c +++ b/drivers/rtc/s35392a.c @@ -350,6 +350,8 @@ static const struct rtc_ops s35392a_rtc_ops = { static const struct udevice_id s35392a_rtc_ids[] = { { .compatible = "sii,s35392a-rtc" }, + { .compatible = "sii,s35392a" }, + { .compatible = "s35392a" }, { } }; diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index c04535ac445..95eeb8307ad 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -27,6 +27,12 @@ /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +/* + * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However, + * the controller seems to hang when given 0x10000, so stick with this for now. + */ +#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff + struct rockchip_spi_params { /* RXFIFO overruns and TXFIFO underruns stop the master clock */ bool master_manages_fifo; @@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev, * represented in CTRLR1. */ if (data && data->master_manages_fifo) - max_chunk_size = 0x10000; + max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN; // rockchip_spi_configure(dev, mode, size) rkspi_enable_chip(regs, false); @@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0x10000); + int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1); diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 5e6293ae69b..f09e138bb8c 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -119,7 +119,7 @@ config SYSRESET_TPL_X86 help Reboot support for generic x86 processor reset in TPL. -config SYSRESET_MCP83XX +config SYSRESET_MPC83XX bool "Enable support MPC83xx SoC family reboot driver" help Reboot support for NXP MPC83xx SoCs. diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index fff4a184a02..51af68fad3b 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o -obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o +obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c index 1903f611038..0b6d9cf7274 100644 --- a/drivers/usb/cdns3/ep0.c +++ b/drivers/usb/cdns3/ep0.c @@ -10,6 +10,7 @@ * Peter Chen <peter.chen@nxp.com> */ +#include <cpu_func.h> #include <linux/usb/composite.h> #include <linux/iopoll.h> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0f9a6328161..77c555e7692 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, /* Set dwc3 usb2 phy config */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_PHYIF; - reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; switch (hsphy_mode) { case USBPHY_INTERFACE_MODE_UTMI: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); break; case USBPHY_INTERFACE_MODE_UTMIW: - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); break; default: break; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index bff53e072b9..1c08a2c5b6e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -162,18 +162,14 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) -#define DWC3_GUSB2PHYCFG_PHYIF BIT(3) - -/* Global USB2 PHY Configuration Mask */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) - -/* Global USB2 PHY Configuration Offset */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 - -#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) -#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ - DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 +#define UTMI_PHYIF_16_BIT 1 +#define UTMI_PHYIF_8_BIT 0 /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 4cde0acbf63..50ab3650ee9 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -38,7 +38,6 @@ config BACKLIGHT_GPIO config VIDEO_BPP8 bool "Support 8-bit-per-pixel displays" depends on DM_VIDEO - default n help Support drawing text and bitmaps onto a 8-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -48,7 +47,6 @@ config VIDEO_BPP8 config VIDEO_BPP16 bool "Support 16-bit-per-pixel displays" depends on DM_VIDEO - default n help Support drawing text and bitmaps onto a 16-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -58,7 +56,7 @@ config VIDEO_BPP16 config VIDEO_BPP32 bool "Support 32-bit-per-pixel displays" depends on DM_VIDEO - default n + default y if X86 help Support drawing text and bitmaps onto a 32-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -68,7 +66,6 @@ config VIDEO_BPP32 config VIDEO_ANSI bool "Support ANSI escape sequences in video console" depends on DM_VIDEO - default n help Enable ANSI escape sequence decoding for a more fully functional console. diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 2f25af73325..c3f7ef8addc 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -16,39 +16,36 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void * __maybe_unused line; - int __maybe_unused pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; - int __maybe_unused i; + void *line; + int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; + int i; line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length; switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } default: return -ENOSYS; } @@ -76,7 +73,7 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - int __maybe_unused i, row; + int i, row; void *line = vid_priv->fb + y * vid_priv->line_length + VID_TO_PIXEL(x_frac) * VNBYTES(vid_priv->bpix); @@ -85,45 +82,45 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; - uchar __maybe_unused bits = video_fontdata[idx]; + uchar bits = video_fontdata[idx]; switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst++ = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst++ = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst++ = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif default: return -ENOSYS; } diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 71a5c5efba3..b4852555989 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -22,33 +22,30 @@ static int console_set_row_1(struct udevice *dev, uint row, int clr) (row + 1) * VIDEO_FONT_HEIGHT * pbytes; for (j = 0; j < vid_priv->ysize; j++) { switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } default: return -ENOSYS; } @@ -99,39 +96,39 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst-- = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst-- = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst-- = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif default: return -ENOSYS; } @@ -153,33 +150,30 @@ static int console_set_row_2(struct udevice *dev, uint row, int clr) line = vid_priv->fb + vid_priv->ysize * vid_priv->line_length - (row + 1) * VIDEO_FONT_HEIGHT * vid_priv->line_length; switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - break; - } -#endif + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } default: return -ENOSYS; } @@ -226,42 +220,42 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) uchar bits = video_fontdata[idx]; switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst-- = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst-- = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? vid_priv->colour_fg - : vid_priv->colour_bg; - bits <<= 1; + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < VIDEO_FONT_WIDTH; i++) { + *dst-- = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + bits <<= 1; + } + break; } - break; - } -#endif default: return -ENOSYS; } @@ -281,33 +275,30 @@ static int console_set_row_3(struct udevice *dev, uint row, int clr) line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * pbytes; for (j = 0; j < vid_priv->ysize; j++) { switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } -#endif + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + *dst++ = clr; + break; + } default: return -ENOSYS; } @@ -356,39 +347,39 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { switch (vid_priv->bpix) { -#ifdef CONFIG_VIDEO_BPP8 - case VIDEO_BPP8: { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP8: + if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { + uint8_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst++ = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + uint16_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst++ = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg - : vid_priv->colour_bg; + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + uint32_t *dst = line; + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + *dst++ = (pfont[i] & mask) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + } + break; } - break; - } -#endif default: return -ENOSYS; } diff --git a/drivers/video/fonts/.gitignore b/drivers/video/fonts/.gitignore new file mode 100644 index 00000000000..86ec950f649 --- /dev/null +++ b/drivers/video/fonts/.gitignore @@ -0,0 +1 @@ +*.S diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index c690eceeaa7..75c7e25095d 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -116,7 +116,6 @@ static void vidconsole_newline(struct udevice *dev) video_sync(dev->parent, false); } -#if CONFIG_IS_ENABLED(VIDEO_BPP16) || CONFIG_IS_ENABLED(VIDEO_BPP32) static const struct vid_rgb colors[VID_COLOR_COUNT] = { { 0x00, 0x00, 0x00 }, /* black */ { 0xc0, 0x00, 0x00 }, /* red */ @@ -135,23 +134,22 @@ static const struct vid_rgb colors[VID_COLOR_COUNT] = { { 0x00, 0xff, 0xff }, /* bright cyan */ { 0xff, 0xff, 0xff }, /* white */ }; -#endif u32 vid_console_color(struct video_priv *priv, unsigned int idx) { switch (priv->bpix) { -#if CONFIG_IS_ENABLED(VIDEO_BPP16) case VIDEO_BPP16: - return ((colors[idx].r >> 3) << 11) | - ((colors[idx].g >> 2) << 5) | - ((colors[idx].b >> 3) << 0); -#endif -#if CONFIG_IS_ENABLED(VIDEO_BPP32) + if (CONFIG_IS_ENABLED(VIDEO_BPP16)) { + return ((colors[idx].r >> 3) << 11) | + ((colors[idx].g >> 2) << 5) | + ((colors[idx].b >> 3) << 0); + } case VIDEO_BPP32: - return (colors[idx].r << 16) | - (colors[idx].g << 8) | - (colors[idx].b << 0); -#endif + if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { + return (colors[idx].r << 16) | + (colors[idx].g << 8) | + (colors[idx].b << 0); + } default: /* * For unknown bit arrangements just support diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 5ea7568fa4c..12057c8a5be 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -92,26 +92,24 @@ int video_clear(struct udevice *dev) struct video_priv *priv = dev_get_uclass_priv(dev); switch (priv->bpix) { -#ifdef CONFIG_VIDEO_BPP16 - case VIDEO_BPP16: { - u16 *ppix = priv->fb; - u16 *end = priv->fb + priv->fb_size; - - while (ppix < end) - *ppix++ = priv->colour_bg; - break; - } -#endif -#ifdef CONFIG_VIDEO_BPP32 - case VIDEO_BPP32: { - u32 *ppix = priv->fb; - u32 *end = priv->fb + priv->fb_size; - - while (ppix < end) - *ppix++ = priv->colour_bg; - break; - } -#endif + case VIDEO_BPP16: + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { + u16 *ppix = priv->fb; + u16 *end = priv->fb + priv->fb_size; + + while (ppix < end) + *ppix++ = priv->colour_bg; + break; + } + case VIDEO_BPP32: + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { + u32 *ppix = priv->fb; + u32 *end = priv->fb + priv->fb_size; + + while (ppix < end) + *ppix++ = priv->colour_bg; + break; + } default: memset(priv->fb, priv->colour_bg, priv->fb_size); break; @@ -125,14 +123,14 @@ void video_set_default_colors(struct udevice *dev, bool invert) struct video_priv *priv = dev_get_uclass_priv(dev); int fore, back; -#ifdef CONFIG_SYS_WHITE_ON_BLACK - /* White is used when switching to bold, use light gray here */ - fore = VID_LIGHT_GRAY; - back = VID_BLACK; -#else - fore = VID_BLACK; - back = VID_WHITE; -#endif + if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) { + /* White is used when switching to bold, use light gray here */ + fore = VID_LIGHT_GRAY; + back = VID_BLACK; + } else { + fore = VID_BLACK; + back = VID_WHITE; + } if (invert) { int temp; diff --git a/include/common.h b/include/common.h index 8b37b587474..52c02185f40 100644 --- a/include/common.h +++ b/include/common.h @@ -15,7 +15,6 @@ #ifndef __ASSEMBLY__ /* put C only stuff in this section */ -typedef unsigned char uchar; typedef volatile unsigned long vu_long; typedef volatile unsigned short vu_short; typedef volatile unsigned char vu_char; diff --git a/include/compiler.h b/include/compiler.h index 29507f9840e..90372f239c0 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -46,7 +46,6 @@ # include <byteswap.h> #elif defined(__MACH__) || defined(__FreeBSD__) # include <machine/endian.h> -typedef unsigned long ulong; #endif #ifdef __FreeBSD__ # include <sys/endian.h> /* htole32 and friends */ @@ -66,6 +65,7 @@ typedef uint8_t __u8; typedef uint16_t __u16; typedef uint32_t __u32; typedef unsigned int uint; +typedef unsigned long ulong; #define uswap_16(x) \ ((((x) & 0xff00) >> 8) | \ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 844d2688d92..fbe431b9c9a 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -63,10 +63,8 @@ #define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_PHY_TI /* * Default to using SPI for environment, etc. diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index acbab05ae93..991fe0056c4 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -39,7 +39,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image.itb\0" \ - "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "console=ttymxc1,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fit=try\0" \ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 62037c7387a..ce73ca6b0ae 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -42,7 +42,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image.itb\0" \ - "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "console=ttymxc1,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fit=try\0" \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index b29989db8f9..5d9ef70830f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -103,7 +103,7 @@ CONFIG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ - "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "console=ttymxc0,115200\0" \ "fdt_addr=0x43000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 71ff7893810..10aa1bcd87c 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -182,6 +182,19 @@ /*----------------------------------------------------------------------- * environment organization */ + +/* + * Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432 + * + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 #define CONFIG_SYS_MMC_ENV_DEV 0 #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 704d9f3dcb8..55aace1c6e7 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -54,9 +54,9 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ - "mmcdev=2\0" \ + "mmcdev=3\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 2:2 uuid\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ "loadbootscript=" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4157d7614fc..bc8aa7adf5a 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -37,7 +37,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_ENV_SECT_SIZE SZ_128K #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index a67d3d7d1b7..bd9ac826f3d 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -42,7 +42,7 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01f00000\0" \ + "fdt_addr_r=0x02800000\0" \ "kernel_addr_r=0x00680000\0" \ "ramdisk_addr_r=0x04000000\0" diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index b14da3a6265..407e5d29311 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -11,6 +11,7 @@ #define CONFIG_IRAM_BASE 0xff090000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 +#define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 1086d2168ce..bfd477f31d2 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -8,6 +8,8 @@ #ifndef _UBOOT_CRC_H #define _UBOOT_CRC_H +#include <compiler.h> /* 'uint*' definitions */ + /** * crc8() - Calculate and return CRC-8 of the data * diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py index 9bdaef9373f..6ff38f1020b 100644 --- a/test/py/tests/test_env.py +++ b/test/py/tests/test_env.py @@ -49,7 +49,7 @@ class StateTestEnv(object): for l in response.splitlines(): if not '=' in l: continue - (var, value) = l.strip().split('=', 1) + (var, value) = l.split('=', 1) self.env[var] = value def get_existent_var(self): diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py index 0ee972298ca..038f03064a6 100644 --- a/test/py/tests/test_handoff.py +++ b/test/py/tests/test_handoff.py @@ -6,7 +6,7 @@ import pytest # Magic number to check that SPL handoff is working TEST_HANDOFF_MAGIC = 0x14f93c7b -@pytest.mark.boardspec('sandbox') +@pytest.mark.boardspec('sandbox_spl') @pytest.mark.buildconfigspec('spl') def test_handoff(u_boot_console): """Test that of-platdata can be generated and used in sandbox""" diff --git a/tools/.gitignore b/tools/.gitignore index d0176a7283f..82bdce27829 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -1,3 +1,4 @@ +/asn1_compiler /atmel_pmecc_params /bin2header /bmp_logo diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 30b5a190ab9..381739d28df 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -112,6 +112,7 @@ struct environment { unsigned char *flags; char *data; enum flag_scheme flag_scheme; + int dirty; }; static struct environment environment = { @@ -506,6 +507,9 @@ int fw_env_flush(struct env_opts *opts) if (!opts) opts = &default_opts; + if (!environment.dirty) + return 0; + /* * Update CRC */ @@ -551,7 +555,8 @@ int fw_env_write(char *name, char *value) deleting = (oldval && !(value && strlen(value))); creating = (!oldval && (value && strlen(value))); - overwriting = (oldval && (value && strlen(value))); + overwriting = (oldval && (value && strlen(value) && + strcmp(oldval, value))); /* check for permission */ if (deleting) { @@ -591,6 +596,7 @@ int fw_env_write(char *name, char *value) /* Nothing to do */ return 0; + environment.dirty = 1; if (deleting || overwriting) { if (*++nxt == '\0') { *env = '\0'; @@ -1440,6 +1446,7 @@ int fw_env_open(struct env_opts *opts) "Warning: Bad CRC, using default environment\n"); memcpy(environment.data, default_environment, sizeof(default_environment)); + environment.dirty = 1; } } else { flag0 = *environment.flags; @@ -1493,6 +1500,16 @@ int fw_env_open(struct env_opts *opts) crc1_ok = (crc1 == redundant->crc); flag1 = redundant->flags; + /* + * environment.data still points to ((struct + * env_image_redundant *)addr0)->data. If the two + * environments differ, or one has bad crc, force a + * write-out by marking the environment dirty. + */ + if (memcmp(environment.data, redundant->data, ENV_SIZE) || + !crc0_ok || !crc1_ok) + environment.dirty = 1; + if (crc0_ok && !crc1_ok) { dev_current = 0; } else if (!crc0_ok && crc1_ok) { @@ -1502,6 +1519,7 @@ int fw_env_open(struct env_opts *opts) "Warning: Bad CRC, using default environment\n"); memcpy(environment.data, default_environment, sizeof(default_environment)); + environment.dirty = 1; dev_current = 0; } else { switch (environment.flag_scheme) { diff --git a/tools/imagetool.h b/tools/imagetool.h index 2689a4004a7..e1c778b0dff 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -253,6 +253,7 @@ void pbl_load_uboot(int fd, struct image_tool_params *mparams); int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); int imx8image_copy_image(int fd, struct image_tool_params *mparams); int imx8mimage_copy_image(int fd, struct image_tool_params *mparams); +int rockchip_copy_image(int fd, struct image_tool_params *mparams); #define ___cat(a, b) a ## b #define __cat(a, b) ___cat(a, b) diff --git a/tools/imximage.c b/tools/imximage.c index d7c0b6e883f..d7edd3c52f4 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -11,9 +11,13 @@ #include "imagetool.h" #include <image.h> #include "imximage.h" +#include <generated/autoconf.h> #define UNDEFINED 0xFFFFFFFF +#if !defined(CONFIG_IMX_DCD_ADDR) +#define CONFIG_IMX_DCD_ADDR 0x00910000 +#endif /* * Supported commands for configuration file */ @@ -524,8 +528,8 @@ static void print_hdr_v2(struct imx_header *imx_hdr) printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n", (uint32_t)fhdr_v2->self, 0, (uint32_t)(fhdr_v2->csf - fhdr_v2->self)); - printf("DCD Blocks: 0x00910000 0x%08x 0x%08x\n", - offs, be16_to_cpu(dcdlen)); + printf("DCD Blocks: 0x%08x 0x%08x 0x%08x\n", + offs, CONFIG_IMX_DCD_ADDR, be16_to_cpu(dcdlen)); } } else { imx_header_v2_t *next_hdr_v2; diff --git a/tools/mkimage.c b/tools/mkimage.c index 42171883109..5f51d2cc89f 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -544,6 +544,14 @@ int main(int argc, char **argv) ret = imx8mimage_copy_image(ifd, ¶ms); if (ret) return ret; + } else if ((params.type == IH_TYPE_RKSD) || + (params.type == IH_TYPE_RKSPI)) { + /* Rockchip has special Image format */ + int ret; + + ret = rockchip_copy_image(ifd, ¶ms); + if (ret) + return ret; } else { copy_file(ifd, params.datafile, pad_len); } diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 0d908daee80..c2382dfe5a1 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -14,8 +14,6 @@ #include "mkimage.h" #include "rkcommon.h" -#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) - enum { RK_SIGNATURE = 0x0ff0aa55, }; @@ -80,6 +78,24 @@ static struct spl_info spl_infos[] = { { "rv1108", "RK11", 0x1800, false }, }; +/** + * struct spl_params - spl params parsed in check_params() + * + * @init_file: Init data file path + * @init_size: Aligned size of init data in bytes + * @boot_file: Boot data file path + * @boot_size: Aligned size of boot data in bytes + */ + +struct spl_params { + char *init_file; + uint32_t init_size; + char *boot_file; + uint32_t boot_size; +}; + +static struct spl_params spl_params = { 0 }; + static unsigned char rc4_key[16] = { 124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17 @@ -99,13 +115,26 @@ static struct spl_info *rkcommon_get_spl_info(char *imagename) return NULL; } +static int rkcommon_get_aligned_size(struct image_tool_params *params, + const char *fname) +{ + int size; + + size = imagetool_get_filesize(params, fname); + if (size < 0) + return -1; + + /* + * Pad to a 2KB alignment, as required for init/boot size by the ROM + * (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html) + */ + return ROUND(size, RK_SIZE_ALIGN); +} + int rkcommon_check_params(struct image_tool_params *params) { int i; - if (rkcommon_get_spl_info(params->imagename) != NULL) - return EXIT_SUCCESS; - /* * If this is a operation (list or extract), the don't require * imagename to be set. @@ -113,6 +142,40 @@ int rkcommon_check_params(struct image_tool_params *params) if (params->lflag || params->iflag) return EXIT_SUCCESS; + if (!rkcommon_get_spl_info(params->imagename)) + goto err_spl_info; + + spl_params.init_file = params->datafile; + + spl_params.boot_file = strchr(spl_params.init_file, ':'); + if (spl_params.boot_file) { + *spl_params.boot_file = '\0'; + spl_params.boot_file += 1; + } + + spl_params.init_size = + rkcommon_get_aligned_size(params, spl_params.init_file); + if (spl_params.init_size < 0) + return EXIT_FAILURE; + + /* Boot file is optional, and only for back-to-bootrom functionality. */ + if (spl_params.boot_file) { + spl_params.boot_size = + rkcommon_get_aligned_size(params, spl_params.boot_file); + if (spl_params.boot_size < 0) + return EXIT_FAILURE; + } + + if (spl_params.init_size > rkcommon_get_spl_size(params)) { + fprintf(stderr, + "Error: SPL image is too large (size %#x than %#x)\n", + spl_params.init_size, rkcommon_get_spl_size(params)); + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; + +err_spl_info: fprintf(stderr, "ERROR: imagename (%s) is not supported!\n", params->imagename ? params->imagename : "NULL"); @@ -155,8 +218,7 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params) return info->spl_rc4; } -static void rkcommon_set_header0(void *buf, uint file_size, - struct image_tool_params *params) +static void rkcommon_set_header0(void *buf, struct image_tool_params *params) { struct header0_info *hdr = buf; @@ -164,16 +226,8 @@ static void rkcommon_set_header0(void *buf, uint file_size, hdr->signature = RK_SIGNATURE; hdr->disable_rc4 = !rkcommon_need_rc4_spl(params); hdr->init_offset = RK_INIT_OFFSET; + hdr->init_size = spl_params.init_size / RK_BLK_SIZE; - hdr->init_size = DIV_ROUND_UP(file_size, RK_BLK_SIZE); - /* - * The init_size has to be a multiple of 4 blocks (i.e. of 2K) - * or the BootROM will not boot the image. - * - * Note: To verify that this is not a legacy constraint, we - * rechecked this against the RK3399 BootROM. - */ - hdr->init_size = ROUND(hdr->init_size, 4); /* * init_boot_size needs to be set, as it is read by the BootROM * to determine the size of the next-stage bootloader (e.g. U-Boot @@ -182,29 +236,36 @@ static void rkcommon_set_header0(void *buf, uint file_size, * see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html * for a more detailed explanation by Andy Yan */ - hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; + if (spl_params.boot_file) + hdr->init_boot_size = + hdr->init_size + spl_params.boot_size / RK_BLK_SIZE; + else + hdr->init_boot_size = + hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; rc4_encode(buf, RK_BLK_SIZE, rc4_key); } -int rkcommon_set_header(void *buf, uint file_size, - struct image_tool_params *params) +void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd, + struct image_tool_params *params) { struct header1_info *hdr = buf + RK_SPL_HDR_START; - if (file_size > rkcommon_get_spl_size(params)) - return -ENOSPC; - - rkcommon_set_header0(buf, file_size, params); + rkcommon_set_header0(buf, params); /* Set up the SPL name (i.e. copy spl_hdr over) */ memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); if (rkcommon_need_rc4_spl(params)) rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START, - params->file_size - RK_SPL_HDR_START); + spl_params.init_size); - return 0; + if (spl_params.boot_file) { + if (rkcommon_need_rc4_spl(params)) + rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START, + spl_params.init_size, + spl_params.boot_size); + } } static inline unsigned rkcommon_offset_to_spi(unsigned offset) @@ -296,7 +357,7 @@ void rkcommon_print_header(const void *buf) struct header0_info header0; struct spl_info *spl_info; uint8_t image_type; - int ret; + int ret, boot_size; ret = rkcommon_parse_header(buf, &header0, &spl_info); @@ -314,7 +375,11 @@ void rkcommon_print_header(const void *buf) printf("Image Type: Rockchip %s (%s) boot image\n", spl_info->spl_hdr, (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI"); - printf("Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE); + printf("Init Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE); + + boot_size = (header0.init_boot_size - header0.init_size) * RK_BLK_SIZE; + if (boot_size != RK_MAX_BOOT_SIZE) + printf("Boot Data Size: %d bytes\n", boot_size); } void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size) @@ -331,12 +396,8 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size) } int rkcommon_vrec_header(struct image_tool_params *params, - struct image_type_params *tparams, - unsigned int alignment) + struct image_type_params *tparams) { - unsigned int unpadded_size; - unsigned int padded_size; - /* * The SPL image looks as follows: * @@ -362,19 +423,118 @@ int rkcommon_vrec_header(struct image_tool_params *params, /* Allocate, clear and install the header */ tparams->hdr = malloc(tparams->header_size); - if (!tparams->hdr) - return -ENOMEM; + if (!tparams->hdr) { + fprintf(stderr, "%s: Can't alloc header: %s\n", + params->cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } memset(tparams->hdr, 0, tparams->header_size); /* - * If someone passed in 0 for the alignment, we'd better handle - * it correctly... + * We need to store the original file-size (i.e. before padding), as + * imagetool does not set this during its adjustment of file_size. */ - if (!alignment) - alignment = 1; + params->orig_file_size = tparams->header_size + + spl_params.init_size + spl_params.boot_size; + + params->file_size = ROUND(params->orig_file_size, RK_SIZE_ALIGN); + + /* Ignoring pad len, since we are using our own copy_image() */ + return 0; +} + +static int pad_file(struct image_tool_params *params, int ifd, int pad) +{ + uint8_t zeros[4096]; + + memset(zeros, 0, sizeof(zeros)); + + while (pad > 0) { + int todo = sizeof(zeros); + + if (todo > pad) + todo = pad; + if (write(ifd, (char *)&zeros, todo) != todo) { + fprintf(stderr, "%s: Write error on %s: %s\n", + params->cmdname, params->imagefile, + strerror(errno)); + return -1; + } + pad -= todo; + } + + return 0; +} + +static int copy_file(struct image_tool_params *params, int ifd, + const char *file, int padded_size) +{ + int dfd; + struct stat sbuf; + unsigned char *ptr; + int size; + + if (params->vflag) + fprintf(stderr, "Adding Image %s\n", file); + + dfd = open(file, O_RDONLY | O_BINARY); + if (dfd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + params->cmdname, file, strerror(errno)); + return -1; + } - unpadded_size = tparams->header_size + params->file_size; - padded_size = ROUND(unpadded_size, alignment); + if (fstat(dfd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat %s: %s\n", + params->cmdname, file, strerror(errno)); + goto err_close; + } + + if (params->vflag) + fprintf(stderr, "Size %u(pad to %u)\n", + (int)sbuf.st_size, padded_size); + + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s: Can't read %s: %s\n", + params->cmdname, file, strerror(errno)); + goto err_munmap; + } + + size = sbuf.st_size; + if (write(ifd, ptr, size) != size) { + fprintf(stderr, "%s: Write error on %s: %s\n", + params->cmdname, params->imagefile, strerror(errno)); + goto err_munmap; + } + + munmap((void *)ptr, sbuf.st_size); + close(dfd); + return pad_file(params, ifd, padded_size - size); + +err_munmap: + munmap((void *)ptr, sbuf.st_size); +err_close: + close(dfd); + return -1; +} + +int rockchip_copy_image(int ifd, struct image_tool_params *params) +{ + int ret; + + ret = copy_file(params, ifd, spl_params.init_file, + spl_params.init_size); + if (ret) + return ret; + + if (spl_params.boot_file) { + ret = copy_file(params, ifd, spl_params.boot_file, + spl_params.boot_size); + if (ret) + return ret; + } - return padded_size - unpadded_size; + return pad_file(params, ifd, + params->file_size - params->orig_file_size); } diff --git a/tools/rkcommon.h b/tools/rkcommon.h index 47f47a52aaf..93518824a51 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -9,13 +9,11 @@ enum { RK_BLK_SIZE = 512, - RK_INIT_SIZE_ALIGN = 2048, + RK_SIZE_ALIGN = 2048, RK_INIT_OFFSET = 4, RK_MAX_BOOT_SIZE = 512 << 10, RK_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE, RK_SPL_HDR_SIZE = 4, - RK_SPL_START = RK_SPL_HDR_START + RK_SPL_HDR_SIZE, - RK_IMAGE_HEADER_LEN = RK_SPL_START, }; /** @@ -49,11 +47,9 @@ int rkcommon_get_spl_size(struct image_tool_params *params); * This sets up a 2KB header which can be interpreted by the Rockchip boot ROM. * * @buf: Pointer to header place (must be at least 2KB in size) - * @file_size: Size of the file we want the boot ROM to load, in bytes - * @return 0 if OK, -ENOSPC if too large */ -int rkcommon_set_header(void *buf, uint file_size, - struct image_tool_params *params); +void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd, + struct image_tool_params *params); /** * rkcommon_verify_header() - verify the header for a Rockchip boot image @@ -102,14 +98,10 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size); * @params: Pointer to the tool params structure * @tparams: Pointer tot the image type structure (for setting * the header and header_size) - * @alignment: Alignment (a power of two) that the image should be - * padded to (e.g. 512 if we want to align with SD/MMC - * blocksizes or 2048 for the SPI format) * - * @return bytes of padding required/added (does not include the header_size) + * @return 0 (always) */ int rkcommon_vrec_header(struct image_tool_params *params, - struct image_type_params *tparams, - unsigned int alignment); + struct image_type_params *tparams); #endif diff --git a/tools/rkimage.c b/tools/rkimage.c index ae50de55c93..1c5540b1c3d 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -18,7 +18,7 @@ static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, memcpy(buf, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); if (rkcommon_need_rc4_spl(params)) - rkcommon_rc4_encode_spl(buf, 4, params->file_size); + rkcommon_rc4_encode_spl(buf, 0, params->file_size); } static int rkimage_check_image_type(uint8_t type) diff --git a/tools/rksd.c b/tools/rksd.c index 24411d863a0..7d46a1b07b3 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -12,27 +12,6 @@ #include "mkimage.h" #include "rkcommon.h" -static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, - struct image_tool_params *params) -{ - unsigned int size; - int ret; - - /* - * We need to calculate this using 'RK_SPL_HDR_START' and not using - * 'tparams->header_size', as the additional byte inserted when - * 'is_boot0' is true counts towards the payload (and not towards the - * header). - */ - size = params->file_size - RK_SPL_HDR_START; - ret = rkcommon_set_header(buf, size, params); - if (ret) { - /* TODO(sjg@chromium.org): This method should return an error */ - printf("Warning: SPL image is too large (size %#x) and will " - "not boot\n", size); - } -} - static int rksd_check_image_type(uint8_t type) { if (type == IH_TYPE_RKSD) @@ -41,16 +20,6 @@ static int rksd_check_image_type(uint8_t type) return EXIT_FAILURE; } -static int rksd_vrec_header(struct image_tool_params *params, - struct image_type_params *tparams) -{ - /* - * Pad to a 2KB alignment, as required for init_size by the ROM - * (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html) - */ - return rkcommon_vrec_header(params, tparams, RK_INIT_SIZE_ALIGN); -} - /* * rk_sd parameters */ @@ -62,9 +31,9 @@ U_BOOT_IMAGE_TYPE( rkcommon_check_params, rkcommon_verify_header, rkcommon_print_header, - rksd_set_header, + rkcommon_set_header, NULL, rksd_check_image_type, NULL, - rksd_vrec_header + rkcommon_vrec_header ); diff --git a/tools/rkspi.c b/tools/rkspi.c index faa18fcd183..f2530f7bde3 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -21,22 +21,20 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, { int sector; unsigned int size; - int ret; size = params->orig_file_size; - ret = rkcommon_set_header(buf, size, params); - debug("size %x\n", size); - if (ret) { - /* TODO(sjg@chromium.org): This method should return an error */ - printf("Warning: SPL image is too large (size %#x) and will " - "not boot\n", size); - } + + rkcommon_set_header(buf, sbuf, ifd, params); /* * Spread the image out so we only use the first 2KB of each 4KB * region. This is a feature of the SPI format required by the Rockchip * boot ROM. Its rationale is unknown. */ + if (params->vflag) + fprintf(stderr, "Spreading spi image from %u to %u\n", + size, params->file_size); + for (sector = size / RKSPI_SECT_LEN - 1; sector >= 0; sector--) { debug("sector %u\n", sector); memmove(buf + sector * RKSPI_SECT_LEN * 2, @@ -56,35 +54,23 @@ static int rkspi_check_image_type(uint8_t type) } /* - * The SPI payload needs to be padded out to make space for odd half-sector - * layout used in flash (i.e. only the first 2K of each 4K sector is used). + * The SPI payload needs to make space for odd half-sector layout used in flash + * (i.e. only the first 2K of each 4K sector is used). */ static int rkspi_vrec_header(struct image_tool_params *params, struct image_type_params *tparams) { - int padding = rkcommon_vrec_header(params, tparams, RK_INIT_SIZE_ALIGN); - /* - * The file size has not been adjusted at this point (our caller will - * eventually add the header/padding to the file_size), so we need to - * add up the header_size, file_size and padding ourselves. - */ - int padded_size = tparams->header_size + params->file_size + padding; - - /* - * We need to store the original file-size (i.e. before padding), as - * imagetool does not set this during its adjustment of file_size. - */ - params->orig_file_size = padded_size; + rkcommon_vrec_header(params, tparams); /* * Converting to the SPI format (i.e. splitting each 4K page into two * 2K subpages and then padding these 2K pages up to take a complete - * 4K sector again) will will double the image size. - * - * Thus we return the padded_size as an additional padding requirement - * (be sure to add this to the padding returned from the common code). + * 4K sector again) which will double the image size. */ - return padded_size + padding; + params->file_size = ROUND(params->file_size, RKSPI_SECT_LEN) << 1; + + /* Ignoring pad len, since we are using our own copy_image() */ + return 0; } /* |