diff options
Diffstat (limited to 'arch/arm/dts')
41 files changed, 4899 insertions, 17 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8d35a96f61..45a79f0201 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -959,13 +959,16 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb \ imx8ulp-evk-i3c.dtb \ imx8ulp-9x9-evk.dtb \ - imx8ulp-9x9-evk-i3c.dtb + imx8ulp-9x9-evk-i3c.dtb \ + imx8ulp-watch.dtb dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-ddr4-evk.dtb \ + imx8mm-ddr4-ab2.dtb \ imx8mm-ddr3l-val.dtb \ imx8mm-ddr4-val.dtb \ imx8mm-evk.dtb \ + imx8mm-ab2.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-n801x-s.dtb \ @@ -980,8 +983,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ phycore-imx8mm.dtb \ imx8mn-ddr3l-evk.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-ddr4-ab2.dtb \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ + imx8mn-ab2.dtb \ imx8mn-var-som-symphony.dtb \ imx8mn-venice.dtb \ imx8mn-venice-gw7902.dtb \ @@ -999,6 +1004,11 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb +dtb-$(CONFIG_ARCH_IMX9) += \ + imx93-11x11-evk.dtb \ + imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dts + dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts index 040e52912e..3fe19b9848 100644 --- a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts +++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts @@ -100,8 +100,8 @@ SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c - SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 956d724979..22b34c8feb 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -2,6 +2,32 @@ /* * Copyright 2019 Toradex AG */ +/ { + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-pre-proper; +}; &mu { u-boot,dm-pre-proper; @@ -75,6 +101,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -93,6 +135,12 @@ &gpio4 { u-boot,dm-pre-proper; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { @@ -123,6 +171,32 @@ u-boot,dm-pre-proper; }; +/* USB */ +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + dr_mode = "host"; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e..298e4b5907 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2019 Toradex + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -9,7 +9,6 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-apalis-u-boot.dtsi" / { model = "Toradex Apalis iMX8"; @@ -19,6 +18,34 @@ bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; stdout-path = &lpuart1; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-0 = <&pinctrl_gpio_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + }; }; &iomuxc { @@ -30,8 +57,6 @@ <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>, <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>, <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>, - <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>, - <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>, <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, @@ -587,10 +612,26 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; +}; + /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; @@ -598,8 +639,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; bus-width = <8>; cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ status = "okay"; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index 322429a98a..84417d0ea6 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -3,6 +3,34 @@ * Copyright 2019 Toradex AG */ +/ { + aliases { + usbgadget0 = &usbg1; + usbhost1 = &usbh3; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + chipidea,usb = <&usbotg1>; + dr_mode = "peripheral"; + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + cdns3,usb = <&usbotg3>; + dr_mode = "host"; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + &{/imx8qx-pm} { u-boot,dm-pre-proper; @@ -72,6 +100,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &pd_conn_sdch0 { u-boot,dm-pre-proper; }; @@ -84,6 +128,21 @@ u-boot,dm-pre-proper; }; +&gpio_expander_43 { + usb-bypass-n-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + line-name = "usb-bypass-n"; + output-high; + }; + usb-reset-n-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + line-name = "usb-reset-n"; + output-low; + }; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -120,6 +179,30 @@ u-boot,dm-pre-proper; }; +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + #phy-cells = <0>; + reg = <0x0 0x5B160000 0x0 0x40000>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index df992ac639..a672347e1a 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX8X"; @@ -320,8 +319,6 @@ gpio-controller; #gpio-cells = <2>; reg = <0x43>; - initial_io_dir = <0xff>; - initial_output = <0x05>; }; }; @@ -353,3 +350,18 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; status = "okay"; }; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 46e7ad6bab..c5d5a5ab7b 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -66,6 +66,12 @@ clocks = <&clks IMX6ULL_CLK_DCP_CLK>; clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi new file mode 100644 index 0000000000..c0b93bf9c1 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts new file mode 100644 index 0000000000..6d3667ef9a --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi new file mode 100644 index 0000000000..d945d27c54 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ audio-codec; + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + /delete-node/ sound-wm8524; + + leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&fec1 { + mdio { + ethphy0: ethernet-phy@0 { + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&sai3 { + status = "disabled"; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..27daf58a22 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts new file mode 100644 index 0000000000..418db5789e --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM DDR4 Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 9d8f07cfa9..95d339bb37 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -300,7 +300,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index 25bddb4610..311aa39d4c 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -39,6 +39,10 @@ u-boot,dm-spl; }; +&aips4 { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; }; @@ -57,12 +61,20 @@ &gpio5 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &i2c1 { u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -91,6 +103,18 @@ u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi new file mode 100644 index 0000000000..689f6f3218 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts new file mode 100644 index 0000000000..9a5b5f63f8 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi new file mode 100644 index 0000000000..039f3d549a --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + + gpio-leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + mdio { + ethphy0: ethernet-phy@0 { + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi new file mode 100644 index 0000000000..9d595da3a9 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ab2-u-boot.dtsi" + +&blob_1 { + filename = "ddr3_imem_1d_201810.bin"; +}; + +&blob_2 { + filename = "ddr3_dmem_1d_201810.bin"; +}; + +/delete-node/ &blob_3; + +/delete-node/ &blob_4; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts new file mode 100644 index 0000000000..b89e1ce81b --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr3l-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR3L Audio board 2.0"; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..6df56985d6 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts new file mode 100644 index 0000000000..40c9c56bfc --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 00c91d1ae4..d533520efa 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -115,7 +115,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 16d98cb659..203d05e66e 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -39,8 +39,11 @@ */ start-config = < RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index a5c797d357..61e8a70196 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -13,7 +13,7 @@ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { - bootargs = "console=ttymxc1,115200"; + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; @@ -308,7 +308,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h index 420e584bff..155aab1428 100644 --- a/arch/arm/dts/imx8mp-sec-def.h +++ b/arch/arm/dts/imx8mp-sec-def.h @@ -26,6 +26,7 @@ #define D0W 0x00000001 #define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */ +#define PDAP_D0D1_ACCESS 0x0000000F /* D0R|D0W|D1W|D1R */ #define MEM_D1_ACCESS 0x4000000C /* ENA|D1W|D1R */ #define MEM_D0D1_ACCESS 0x4000000F /* ENA|D0W|D0R|D1W|D1R */ @@ -53,6 +54,8 @@ #define RDC_MDA_uSDHC1 15 #define RDC_MDA_uSDHC2 16 #define RDC_MDA_uSDHC3 17 +#define RDC_MDA_ENET1_TX 22 +#define RDC_MDA_ENET1_RX 23 #define RDC_MDA_SDMA3_SPBA2 25 #define RDC_MDA_LCDIF2 27 #define RDC_MDA_HDMI_TX 28 diff --git a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi index 8aec33a463..3f44af90e7 100644 --- a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi @@ -74,6 +74,10 @@ }; +&crypto { + u-boot,dm-spl; +}; + &eqos { compatible = "fsl,imx-eqos"; /delete-property/ assigned-clocks; @@ -95,6 +99,10 @@ &gpio4 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &gpio5 { @@ -113,6 +121,10 @@ u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -150,6 +162,18 @@ u-boot,dm-spl; }; +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &uart3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-verdin.dts b/arch/arm/dts/imx8mp-verdin.dts index a50f42f4ce..19ce3ee193 100644 --- a/arch/arm/dts/imx8mp-verdin.dts +++ b/arch/arm/dts/imx8mp-verdin.dts @@ -88,7 +88,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; }; +}; +&gpio4 { ctrl_sleep_moci { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 2876b94b2a..4662d53183 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -979,7 +979,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-fspi-nand"; - reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; reg-names = "FlexSPI", "FlexSPI-memory"; status = "disabled"; }; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 0c2dcc0792..b22d62c0d9 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -33,6 +33,18 @@ u-boot,dm-spl; }; +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + &per_bridge3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8ulp-watch-u-boot.dtsi b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi new file mode 100644 index 0000000000..a918ce0a05 --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + dsi_host: dsi-host { + compatible = "northwest,mipi-dsi"; + status = "okay"; + }; +}; + +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + +&per_bridge3 { + u-boot,dm-spl; +}; + +&per_bridge4 { + u-boot,dm-spl; +}; + +&iomuxc1 { + u-boot,dm-spl; + fsl,mux_mask = <0xf00>; +}; + +&pinctrl_lpuart5 { + u-boot,dm-spl; +}; + +&s400_mu { + u-boot,dm-spl; +}; + +&lpuart5 { + u-boot,dm-spl; +}; + +&usdhc0 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&pinctrl_usdhc0 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; + +&scmi_buf { + reg = <0x0 0x1000>; /* Align page size */ +}; + +&dsi { + data-lanes-num = <4>; +}; + +&usbotg1 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb"; + fsl,usbphy = <&usbphy1>; +}; diff --git a/arch/arm/dts/imx8ulp-watch.dts b/arch/arm/dts/imx8ulp-watch.dts new file mode 100644 index 0000000000..232485486c --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP WATCH"; + compatible = "fsl,imx8ulp-watch", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + bootargs = "console=ttyLP1,115200 earlycon"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + linux,cma-default; + }; + + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + + +&clock_ext_ts { + /* External ts clock is 50MHZ from PHY on EVK board. */ + clock-frequency = <50000000>; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_otgid1>; + pinctrl-1 = <&pinctrl_otgid1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_otgid1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 + >; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "usmp,rm67162"; + reg = <0>; + dsi-lanes = <1>; + reset,otherway; + vcc-supply = <®_5v>; + iovcc-supply = <®_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dcnano { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&usbotg2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi index 155d29fb19..901766957d 100644 --- a/arch/arm/dts/imx8ulp.dtsi +++ b/arch/arm/dts/imx8ulp.dtsi @@ -157,6 +157,11 @@ reg = <0x11>; #power-domain-cells = <1>; }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi new file mode 100644 index 0000000000..13474a35fc --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c3 { + u-boot,dm-spl; +}; + +&fec { + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&ptn5110_2>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts new file mode 100644 index 0000000000..c82e5a9c67 --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk.dts @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + i2c8 = &flexio_i2c_master; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + audio: audio@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; + enable-active-low; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dsi_host: dsi-host { + compatible = "synopsys,dw-mipi-dsi"; + status = "okay"; + }; + + rm67199_panel { + compatible = "raydium,rm67199"; + reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_to_adv7535: endpoint { + remote-endpoint = <&adv7535_to_dsi>; + }; + }; + + port@2 { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + interrupt-parent = <&pcal6524>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585gpio: gpio@34 { + compatible = "adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&pcal6524>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + status = "okay"; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; + +&wdog3 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts new file mode 100644 index 0000000000..6eb09ec9e3 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" +#include "imx93-9x9-qsb-u-boot.dtsi" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1", "simple-panel"; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + + vsync-active = <0>; + hsync-active = <0>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + /*assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>;*/ +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 0000000000..06935ce1e4 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts new file mode 100644 index 0000000000..accb295c03 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-micfil"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 0000000000..4298a145f8 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 +#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 +#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 +#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 +#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 +#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 +#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 +#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 +#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 +#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 +#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 +#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 +#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 +#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 +#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 +#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 +#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 +#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 +#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 +#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 +#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 +#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 +#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 +#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 +#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 +#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 +#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 +#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 +#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 +#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 +#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 +#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 +#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 +#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 +#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 +#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 +#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 +#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 +#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 +#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 +#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 +#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 +#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 +#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 +#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 +#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 +#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 +#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 +#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 +#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 +#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 +#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 +#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 +#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 +#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 +#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 +#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 +#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 +#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 +#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 +#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 +#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 +#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 +#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 +#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 +#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 +#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 +#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 +#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 +#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 +#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 +#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 +#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 +#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 +#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 +#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 +#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 +#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 +#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 +#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 +#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 +#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 +#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 +#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 +#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 +#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 +#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 +#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 +#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 +#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 +#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 +#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 +#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 +#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 +#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 +#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 +#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 +#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 +#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 +#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 +#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 +#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 +#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 +#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 +#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 +#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 +#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 +#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 +#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 +#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 +#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 +#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 +#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 +#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 +#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 +#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 +#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 +#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 +#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 +#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 +#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 +#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 +#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 +#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 +#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 +#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 +#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 +#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 + +#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi new file mode 100644 index 0000000000..be4626d5e7 --- /dev/null +++ b/arch/arm/dts/imx93.dtsi @@ -0,0 +1,1503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/imx93-power.h> +#include <dt-bindings/usb/pd.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &flexspi; + isi0 = &isi_0; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + csi0 = &mipi_csi; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + edma1: dma-controller@44000000{ + compatible = "fsl,imx93-edma-v3"; + reg = <0x44000000 0x10000>, + <0x44010000 0x10000>, <0x44020000 0x10000>, + <0x44030000 0x10000>, <0x44040000 0x10000>, + <0x44050000 0x10000>, <0x44060000 0x10000>, + <0x44070000 0x10000>, <0x44080000 0x10000>, + <0x44090000 0x10000>, <0x440a0000 0x10000>, + <0x440b0000 0x10000>, <0x440c0000 0x10000>, + <0x440d0000 0x10000>, <0x440e0000 0x10000>, + <0x440f0000 0x10000>, <0x44100000 0x10000>, + <0x44110000 0x10000>, <0x44120000 0x10000>, + <0x44130000 0x10000>, <0x44140000 0x10000>, + <0x44150000 0x10000>, <0x44160000 0x10000>, + <0x44170000 0x10000>, <0x44180000 0x10000>, + <0x44190000 0x10000>, <0x441a0000 0x10000>, + <0x441b0000 0x10000>, <0x441c0000 0x10000>, + <0x441d0000 0x10000>, <0x441e0000 0x10000>, + <0x441f0000 0x10000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-err"; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + anomix_ns_gpr: blk-ctrl-anomix@42420000 { + compatible = "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + i3c1: i3c-master@44330000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_LPI2C1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_LPI2C2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_LPSPI1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_LPSPI2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + /* sai1 supports 2x TX/RX */ + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&anomix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + }; + + bbnsm: bbnsm@44440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,bbnsm-rtc"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,bbnsm-pwrkey"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + src: src@44460000 { + compatible = "fsl,imx93-src"; + reg = <0x44460000 0x10000>; + + slice { + #address-cells = <1>; + #size-cells = <0>; + + mlmix: slice@1800 { + reg = <IMX93_POWER_DOMAIN_MLMIX>; + #power-domain-cells = <0>; + }; + + mediamix: slice@2400 { + reg = <IMX93_POWER_DOMAIN_MEDIAMIX>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + + tmu: tmu@44482000 { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <0>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + /* + 199 pdm ipi_int_hwvad_err + 200 pdm ipi_int_hwvad_event + 201 pdm ipi_int_mic_err + 202 pdm ipi_int_mic_filter + */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "clkext3"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@42000000{ + compatible = "fsl,imx93-edma-v4"; + reg = <0x42000000 0x10000>, + <0x42010000 0x8000>, <0x42018000 0x8000>, + <0x42020000 0x8000>, <0x42028000 0x8000>, + <0x42030000 0x8000>, <0x42038000 0x8000>, + <0x42040000 0x8000>, <0x42048000 0x8000>, + <0x42050000 0x8000>, <0x42058000 0x8000>, + <0x42060000 0x8000>, <0x42068000 0x8000>, + <0x42070000 0x8000>, <0x42078000 0x8000>, + <0x42080000 0x8000>, <0x42088000 0x8000>, + <0x42090000 0x8000>, <0x42098000 0x8000>, + <0x420a0000 0x8000>, <0x420a8000 0x8000>, + <0x420b0000 0x8000>, <0x420b8000 0x8000>, + <0x420c0000 0x8000>, <0x420c8000 0x8000>, + <0x420d0000 0x8000>, <0x420d8000 0x8000>, + <0x420e0000 0x8000>, <0x420e8000 0x8000>, + <0x420f0000 0x8000>, <0x420f8000 0x8000>, + <0x42100000 0x8000>, <0x42108000 0x8000>, + <0x42110000 0x8000>, <0x42118000 0x8000>, + <0x42120000 0x8000>, <0x42128000 0x8000>, + <0x42130000 0x8000>, <0x42138000 0x8000>, + <0x42140000 0x8000>, <0x42148000 0x8000>, + <0x42150000 0x8000>, <0x42158000 0x8000>, + <0x42160000 0x8000>, <0x42168000 0x8000>, + <0x42170000 0x8000>, <0x42178000 0x8000>, + <0x42180000 0x8000>, <0x42188000 0x8000>, + <0x42190000 0x8000>, <0x42198000 0x8000>, + <0x421a0000 0x8000>, <0x421a8000 0x8000>, + <0x421b0000 0x8000>, <0x421b8000 0x8000>, + <0x421c0000 0x8000>, <0x421c8000 0x8000>, + <0x421d0000 0x8000>, <0x421d8000 0x8000>, + <0x421e0000 0x8000>, <0x421e8000 0x8000>, + <0x421f0000 0x8000>, <0x421f8000 0x8000>, + <0x42200000 0x8000>, <0x42208000 0x8000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx", + "edma2-chan32-tx", "edma2-chan33-tx", + "edma2-chan34-tx", "edma2-chan35-tx", + "edma2-chan36-tx", "edma2-chan37-tx", + "edma2-chan38-tx", "edma2-chan39-tx", + "edma2-chan40-tx", "edma2-chan41-tx", + "edma2-chan42-tx", "edma2-chan43-tx", + "edma2-chan44-tx", "edma2-chan45-tx", + "edma2-chan46-tx", "edma2-chan47-tx", + "edma2-chan48-tx", "edma2-chan49-tx", + "edma2-chan50-tx", "edma2-chan51-tx", + "edma2-chan52-tx", "edma2-chan53-tx", + "edma2-chan54-tx", "edma2-chan55-tx", + "edma2-chan56-tx", "edma2-chan57-tx", + "edma2-chan58-tx", "edma2-chan59-tx", + "edma2-chan60-tx", "edma2-chan61-tx", + "edma2-chan62-tx", "edma2-chan63-tx", + "edma2-err"; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { + compatible = "syscon"; + reg = <0x42420000 0x1000>; + }; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: wdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + assigned-clocks = <&clk IMX93_CLK_TPM4>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c-master@42520000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_LPI2C3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_LPI2C4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_LPSPI3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_LPSPI4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + dmas = <&edma2 17 0 0>, <&edma2 18 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + dmas = <&edma2 19 0 0>, <&edma2 20 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + dmas = <&edma2 21 0 0>, <&edma2 22 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + dmas = <&edma2 23 0 0>, <&edma2 24 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexspi: spi@425e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 59 0 1>, <&edma1 58 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif: spdif@42680000 { + compatible = "fsl,imx93-spdif"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + /* XCVR PHY - SPDIF wakeup IRQ */ + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + dmas = <&edma2 87 0 0>, <&edma2 88 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + dmas = <&edma2 89 0 0>, <&edma2 90 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_LPI2C5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_LPI2C6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_LPI2C7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_LPI2C8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_LPSPI5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_LPSPI6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_LPSPI7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_LPSPI8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexio_i2c_master: flexio@425c0000 { + compatible = "imx,flexio_i2c_master"; + reg = <0x425c0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXIO1_GATE>, + <&clk IMX93_CLK_FLEXIO1_GATE>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + reg = <0x42890000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_WAKEUP_AXI>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + clk_csr = <0>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + epxp: epxp@4ae20000 { + compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma"; + reg = <0x4ae20000 0x10000>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pxp_ipg", "pxp_axi"; + pxp-gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@4ae40000{ + compatible = "fsl,imx93-isi", "fsl,imx8-isi"; + reg = <0x4ae40000 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "per", "axi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333333>; + interface = <2 0 2>; + no-reset-control; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>; + gasket = <&media_blk_ctrl>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi: csi@4ae00000 { + compatible = "fsl,dwc-mipi-csi2-host"; + reg = <0x4ae00000 0x10000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + clock-names = "clk_core", "clk_pixel", "phy_cfg"; + assigned-clocks = <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_24M>; + assigned-clock-rates = <140000000>, <24000000>; + gasket = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>; + status = "disabled"; + }; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO2>, + <&clk IMX93_CLK_PCTL2>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO3>, + <&clk IMX93_CLK_PCTL3>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO4>, + <&clk IMX93_CLK_PCTL4>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO1>, + <&clk IMX93_CLK_PCTL1>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 0 32>; + }; + + ocotp: efuse@47510000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x1000>; + status = "disabled"; + }; + + s4muap: s4muap@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "txirq", "rxirq"; + #mbox-cells = <2>; + status = "okay"; + }; + + sentnl_mu: sentnl-mu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx-sentnl"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,sentnl_mu_id = <2>; + fsl,sentnl_mu_max_users = <4>; + status = "okay"; + dma-ranges = <0x80000000 0x80000000 0x20000000>; + }; + + media_blk_ctrl: blk-ctrl@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, + <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + }; + + parallel_disp_fmt: dpi { + compatible = "fsl,imx93-parallel-display-format"; + /* power-domains = <&mediamix>; [Not enable for U-Boot], otherwise driver probe fail */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + }; + }; + }; + + ldb: ldb@4ac10020 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-ldb"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + gpr = <&media_blk_ctrl>; + power-domains = <&mediamix>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + }; + }; + + ldb_phy: phy@4ac10024 { + compatible = "fsl,imx93-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_APB>; + clock-names = "apb"; + power-domains = <&mediamix>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + dsi: dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x4000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "byte", "pclk"; + assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <20000000>, <133333334>; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + }; + }; + + lcdif: lcd-controller@4ae30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + fsl,gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_LCDIF_GATE>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_24M>, + <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif_to_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_to_lcdif>; + }; + + lcdif_to_ldb: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif_to_dpi: endpoint@2 { + reg = <2>; + remote-endpoint = <&dpi_to_lcdif>; + }; + }; + }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp>; + }; +}; diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi new file mode 100644 index 0000000000..3711e42419 --- /dev/null +++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2022 NXP + */ + +&{/soc} { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index bf96af7e36..82df2f11bb 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -6,6 +6,7 @@ */ #include "ls1021a.dtsi" +#include "ls1021a-twr-u-boot.dtsi" / { model = "LS1021A TWR Board"; |