diff options
Diffstat (limited to 'arch/arm')
101 files changed, 11888 insertions, 598 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3284211556..09da1b375b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -839,6 +839,19 @@ config ARCH_IMX8ULP select SYS_FSL_HAS_SEC select SYS_FSL_SEC_LE select SYS_FSL_SEC_COMPAT_4 + select MISC + select IMX_SENTINEL + imply CMD_DM + +config ARCH_IMX9 + bool "NXP i.MX9 platform" + select ARM64 + select DM + select MACH_IMX + select SUPPORT_SPL + select GPIO_EXTRA_HEADER + select MISC + select IMX_SENTINEL imply CMD_DM config ARCH_IMXRT @@ -2137,6 +2150,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/imx8ulp/Kconfig" +source "arch/arm/mach-imx/imx9/Kconfig" + source "arch/arm/mach-imx/imxrt/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" @@ -2193,6 +2208,8 @@ source "arch/arm/cpu/armv7/Kconfig" source "arch/arm/cpu/armv8/Kconfig" +source "arch/arm/cpu/armv8/crypto/Kconfig" + source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-nexell/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f35b246a5c..5bfc30861b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -32,7 +32,7 @@ else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) endif -ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP),) +ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP)$(CONFIG_ARCH_IMX9),) arch-y += -mgeneral-regs-only endif @@ -116,11 +116,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imx9 imxrt)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imx9 imxrt vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 85fe0475c8..6e1498b470 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += crypto/ diff --git a/arch/arm/cpu/armv8/crypto/Kconfig b/arch/arm/cpu/armv8/crypto/Kconfig new file mode 100644 index 0000000000..379c673343 --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Kconfig @@ -0,0 +1,6 @@ +if ARM64 + +config CRYPTO_SHA2_ARM64_CE + tristate "SHA-224/SHA-256 digest algorithm (ARMv8 Crypto Extensions)" + +endif diff --git a/arch/arm/cpu/armv8/crypto/Makefile b/arch/arm/cpu/armv8/crypto/Makefile new file mode 100644 index 0000000000..8b23b166ed --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += sha2-ce.o +sha2-ce-y := sha2-ce-glue.o sha2-ce-core.o diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-core.S b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S new file mode 100644 index 0000000000..ad76362dff --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org> + * Copyright 2022 NXP + */ + +#include <linux/linkage.h> +#include <asm/macro.h> + + .text + .arch armv8-a+crypto + + dga .req q20 + dgav .req v20 + dgb .req q21 + dgbv .req v21 + + t0 .req v22 + t1 .req v23 + + dg0q .req q24 + dg0v .req v24 + dg1q .req q25 + dg1v .req v25 + dg2q .req q26 + dg2v .req v26 + + .macro add_only, ev, rc, s0 + mov dg2v.16b, dg0v.16b + .ifeq \ev + add t1.4s, v\s0\().4s, \rc\().4s + sha256h dg0q, dg1q, t0.4s + sha256h2 dg1q, dg2q, t0.4s + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha256h dg0q, dg1q, t1.4s + sha256h2 dg1q, dg2q, t1.4s + .endif + .endm + + .macro add_update, ev, rc, s0, s1, s2, s3 + sha256su0 v\s0\().4s, v\s1\().4s + add_only \ev, \rc, \s1 + sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s + .endm + + /* + * The SHA-256 round constants + */ + .section ".rodata", "a" + .align 4 +.Lsha2_rcon: + .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5 + .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5 + .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3 + .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174 + .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc + .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da + .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7 + .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967 + .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13 + .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85 + .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3 + .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070 + .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5 + .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3 + .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208 + .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 + + /* + * void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + * int blocks) + */ + .text +ENTRY(sha2_ce_transform) + /* load round constants */ + adr_l x8, .Lsha2_rcon + ld1 { v0.4s- v3.4s}, [x8], #64 + ld1 { v4.4s- v7.4s}, [x8], #64 + ld1 { v8.4s-v11.4s}, [x8], #64 + ld1 {v12.4s-v15.4s}, [x8] + + /* load state */ + ld1 {dgav.4s, dgbv.4s}, [x0] + + /* load sha256_ce_state::finalize */ + ldr_l w4, sha256_ce_offsetof_finalize, x4 + ldr w4, [x0, x4] + + /* load input */ +0: ld1 {v16.4s-v19.4s}, [x1], #64 + sub w2, w2, #1 + +CPU_LE( rev32 v16.16b, v16.16b ) +CPU_LE( rev32 v17.16b, v17.16b ) +CPU_LE( rev32 v18.16b, v18.16b ) +CPU_LE( rev32 v19.16b, v19.16b ) + +1: add t0.4s, v16.4s, v0.4s + mov dg0v.16b, dgav.16b + mov dg1v.16b, dgbv.16b + + add_update 0, v1, 16, 17, 18, 19 + add_update 1, v2, 17, 18, 19, 16 + add_update 0, v3, 18, 19, 16, 17 + add_update 1, v4, 19, 16, 17, 18 + + add_update 0, v5, 16, 17, 18, 19 + add_update 1, v6, 17, 18, 19, 16 + add_update 0, v7, 18, 19, 16, 17 + add_update 1, v8, 19, 16, 17, 18 + + add_update 0, v9, 16, 17, 18, 19 + add_update 1, v10, 17, 18, 19, 16 + add_update 0, v11, 18, 19, 16, 17 + add_update 1, v12, 19, 16, 17, 18 + + add_only 0, v13, 17 + add_only 1, v14, 18 + add_only 0, v15, 19 + add_only 1 + + /* update state */ + add dgav.4s, dgav.4s, dg0v.4s + add dgbv.4s, dgbv.4s, dg1v.4s + + /* handled all input blocks? */ + cbz w2, 2f + b 0b + + /* + * Final block: add padding and total bit count. + * Skip if the input size was not a round multiple of the block size, + * the padding is handled by the C code in that case. + */ +2: cbz x4, 3f + ldr_l w4, sha256_ce_offsetof_count, x4 + ldr x4, [x0, x4] + movi v17.2d, #0 + mov x8, #0x80000000 + movi v18.2d, #0 + ror x7, x4, #29 // ror(lsl(x4, 3), 32) + fmov d16, x8 + mov x4, #0 + mov v19.d[0], xzr + mov v19.d[1], x7 + b 1b + + /* store new state */ +3: st1 {dgav.4s, dgbv.4s}, [x0] + mov w0, w2 + ret +ENDPROC(sha2_ce_transform) diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c new file mode 100644 index 0000000000..31e436ef1d --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha2-ce-glue.c - SHA-256 using ARMv8 Crypto Extensions + * + * Copyright (C) 2014 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org> + * Copyright 2022 NXP + */ + +#include <linux/kernel.h> +#include <linux/linkage.h> +#include <crypto/sha256_base.h> + +struct sha256_ce_state { + struct sha256_state sst; + u32 finalize; +}; + +extern const u32 sha256_ce_offsetof_count; +extern const u32 sha256_ce_offsetof_finalize; + +asmlinkage int sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + int blocks); + +static void __sha2_ce_transform(struct sha256_state *sst, u8 const *src, + int blocks) +{ + while (blocks) { + int rem; + + rem = sha2_ce_transform(container_of(sst, struct sha256_ce_state, + sst), src, blocks); + src += (blocks - rem) * SHA256_BLOCK_SIZE; + blocks = rem; + } +} + +const u32 sha256_ce_offsetof_count = offsetof(struct sha256_ce_state, + sst.count); +const u32 sha256_ce_offsetof_finalize = offsetof(struct sha256_ce_state, + finalize); + +static void sha256_ce_update(struct sha256_ce_state *sctx, const u8 *data, + unsigned int len) +{ + sctx->finalize = 0; + sha256_base_do_update(&sctx->sst, data, len, __sha2_ce_transform); +} + +static void sha256_ce_final(struct sha256_ce_state *sctx, u8 *out) +{ + sctx->finalize = 0; + sha256_base_do_finalize(&sctx->sst, __sha2_ce_transform); + sha256_base_finish(&sctx->sst, out); +} + +/* + * Output = SHA-256( input buffer ). + */ +void sha256_ce(const unsigned char *input, unsigned int ilen, unsigned char *output) +{ + struct sha256_ce_state sctx; + + sha256_init(&sctx.sst); + sha256_ce_update(&sctx, input, ilen); + sha256_ce_final(&sctx, output); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8d35a96f61..45a79f0201 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -959,13 +959,16 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb \ imx8ulp-evk-i3c.dtb \ imx8ulp-9x9-evk.dtb \ - imx8ulp-9x9-evk-i3c.dtb + imx8ulp-9x9-evk-i3c.dtb \ + imx8ulp-watch.dtb dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-ddr4-evk.dtb \ + imx8mm-ddr4-ab2.dtb \ imx8mm-ddr3l-val.dtb \ imx8mm-ddr4-val.dtb \ imx8mm-evk.dtb \ + imx8mm-ab2.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-n801x-s.dtb \ @@ -980,8 +983,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ phycore-imx8mm.dtb \ imx8mn-ddr3l-evk.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-ddr4-ab2.dtb \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ + imx8mn-ab2.dtb \ imx8mn-var-som-symphony.dtb \ imx8mn-venice.dtb \ imx8mn-venice-gw7902.dtb \ @@ -999,6 +1004,11 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb +dtb-$(CONFIG_ARCH_IMX9) += \ + imx93-11x11-evk.dtb \ + imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dts + dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts index 040e52912e..3fe19b9848 100644 --- a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts +++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts @@ -100,8 +100,8 @@ SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c - SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index 956d724979..22b34c8feb 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -2,6 +2,32 @@ /* * Copyright 2019 Toradex AG */ +/ { + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-pre-proper; +}; &mu { u-boot,dm-pre-proper; @@ -75,6 +101,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -93,6 +135,12 @@ &gpio4 { u-boot,dm-pre-proper; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { @@ -123,6 +171,32 @@ u-boot,dm-pre-proper; }; +/* USB */ +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + dr_mode = "host"; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e..298e4b5907 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2019 Toradex + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -9,7 +9,6 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-apalis-u-boot.dtsi" / { model = "Toradex Apalis iMX8"; @@ -19,6 +18,34 @@ bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; stdout-path = &lpuart1; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-0 = <&pinctrl_gpio_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + }; }; &iomuxc { @@ -30,8 +57,6 @@ <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>, <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>, <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>, - <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>, - <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>, <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, @@ -587,10 +612,26 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; +}; + /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; @@ -598,8 +639,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; bus-width = <8>; cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ status = "okay"; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index 322429a98a..84417d0ea6 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -3,6 +3,34 @@ * Copyright 2019 Toradex AG */ +/ { + aliases { + usbgadget0 = &usbg1; + usbhost1 = &usbh3; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + chipidea,usb = <&usbotg1>; + dr_mode = "peripheral"; + status = "okay"; + u-boot,dm-pre-proper; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + cdns3,usb = <&usbotg3>; + dr_mode = "host"; + status = "okay"; + u-boot,dm-pre-proper; + }; +}; + &{/imx8qx-pm} { u-boot,dm-pre-proper; @@ -72,6 +100,22 @@ u-boot,dm-pre-proper; }; +&pd_conn_usbotg0 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2 { + u-boot,dm-pre-proper; +}; + +&pd_conn_usb2_phy { + u-boot,dm-pre-proper; +}; + &pd_conn_sdch0 { u-boot,dm-pre-proper; }; @@ -84,6 +128,21 @@ u-boot,dm-pre-proper; }; +&gpio_expander_43 { + usb-bypass-n-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + line-name = "usb-bypass-n"; + output-high; + }; + usb-reset-n-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + line-name = "usb-reset-n"; + output-low; + }; +}; + &gpio0 { u-boot,dm-pre-proper; }; @@ -120,6 +179,30 @@ u-boot,dm-pre-proper; }; +&usbmisc1 { + u-boot,dm-pre-proper; +}; + +&usbphy1 { + u-boot,dm-pre-proper; +}; + +&usbotg1 { + u-boot,dm-pre-proper; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-pre-proper; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + #phy-cells = <0>; + reg = <0x0 0x5B160000 0x0 0x40000>; + u-boot,dm-pre-proper; +}; + &usdhc1 { u-boot,dm-pre-proper; }; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index df992ac639..a672347e1a 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX8X"; @@ -320,8 +319,6 @@ gpio-controller; #gpio-cells = <2>; reg = <0x43>; - initial_io_dir = <0xff>; - initial_output = <0x05>; }; }; @@ -353,3 +350,18 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; status = "okay"; }; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 46e7ad6bab..c5d5a5ab7b 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -66,6 +66,12 @@ clocks = <&clks IMX6ULL_CLK_DCP_CLK>; clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi new file mode 100644 index 0000000000..c0b93bf9c1 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts new file mode 100644 index 0000000000..6d3667ef9a --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi new file mode 100644 index 0000000000..d945d27c54 --- /dev/null +++ b/arch/arm/dts/imx8mm-ab2.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ audio-codec; + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + /delete-node/ sound-wm8524; + + leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&buck5_reg>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&fec1 { + mdio { + ethphy0: ethernet-phy@0 { + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */ + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&sai3 { + status = "disabled"; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..27daf58a22 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk-u-boot.dtsi" + +/ { + usbg2: usbg2 { + status = "disabled"; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts new file mode 100644 index 0000000000..418db5789e --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mm-ddr4-evk.dts" +#include "imx8mm-ab2.dtsi" + +/ { + model = "NXP i.MX8MM DDR4 Audio board 2.0"; + compatible = "fsl,imx8mm-ab2", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 9d8f07cfa9..95d339bb37 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -300,7 +300,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index 25bddb4610..311aa39d4c 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -39,6 +39,10 @@ u-boot,dm-spl; }; +&aips4 { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; }; @@ -57,12 +61,20 @@ &gpio5 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &i2c1 { u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -91,6 +103,18 @@ u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi new file mode 100644 index 0000000000..689f6f3218 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts new file mode 100644 index 0000000000..9a5b5f63f8 --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi new file mode 100644 index 0000000000..039f3d549a --- /dev/null +++ b/arch/arm/dts/imx8mn-ab2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + /delete-node/ dsi-host; + /delete-node/ ir-receiver; + /delete-node/ rm67199_panel; + + gpio-leds { + panel { + label = "green:panel"; + gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ANA_12V0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + mdio { + ethphy0: ethernet-phy@0 { + max-speed = <100>; + }; + }; +}; + +&i2c2 { + /delete-node/ adv7535@3d; + /delete-node/ tcpc@50; + + pca6408_2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + ptn5150: tcpc@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + >; + }; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; + + /delete-node/ port@1; + /delete-node/ port@2; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg1 { + extcon = <&ptn5150>; +}; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi new file mode 100644 index 0000000000..9d595da3a9 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ab2-u-boot.dtsi" + +&blob_1 { + filename = "ddr3_imem_1d_201810.bin"; +}; + +&blob_2 { + filename = "ddr3_dmem_1d_201810.bin"; +}; + +/delete-node/ &blob_3; + +/delete-node/ &blob_4; diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts new file mode 100644 index 0000000000..b89e1ce81b --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2021 NXP + */ + +#include "imx8mn-ddr3l-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR3L Audio board 2.0"; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi new file mode 100644 index 0000000000..6df56985d6 --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk-u-boot.dtsi" + +&fec1 { + phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts new file mode 100644 index 0000000000..40c9c56bfc --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 NXP + */ + +#include "imx8mn-ddr4-evk.dts" +#include "imx8mn-ab2.dtsi" + +/ { + model = "NXP i.MX8MNano DDR4 Audio board 2.0"; + compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; +}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 00c91d1ae4..d533520efa 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -115,7 +115,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 16d98cb659..203d05e66e 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -39,8 +39,11 @@ */ start-config = < RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index a5c797d357..61e8a70196 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -13,7 +13,7 @@ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { - bootargs = "console=ttymxc1,115200"; + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; @@ -308,7 +308,7 @@ status = "okay"; adv_bridge: adv7535@3d { - compatible = "adi,adv7533"; + compatible = "adi,adv7535"; reg = <0x3d>; adi,addr-cec = <0x3c>; adi,dsi-lanes = <4>; diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h index 420e584bff..155aab1428 100644 --- a/arch/arm/dts/imx8mp-sec-def.h +++ b/arch/arm/dts/imx8mp-sec-def.h @@ -26,6 +26,7 @@ #define D0W 0x00000001 #define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */ +#define PDAP_D0D1_ACCESS 0x0000000F /* D0R|D0W|D1W|D1R */ #define MEM_D1_ACCESS 0x4000000C /* ENA|D1W|D1R */ #define MEM_D0D1_ACCESS 0x4000000F /* ENA|D0W|D0R|D1W|D1R */ @@ -53,6 +54,8 @@ #define RDC_MDA_uSDHC1 15 #define RDC_MDA_uSDHC2 16 #define RDC_MDA_uSDHC3 17 +#define RDC_MDA_ENET1_TX 22 +#define RDC_MDA_ENET1_RX 23 #define RDC_MDA_SDMA3_SPBA2 25 #define RDC_MDA_LCDIF2 27 #define RDC_MDA_HDMI_TX 28 diff --git a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi index 8aec33a463..3f44af90e7 100644 --- a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi @@ -74,6 +74,10 @@ }; +&crypto { + u-boot,dm-spl; +}; + &eqos { compatible = "fsl,imx-eqos"; /delete-property/ assigned-clocks; @@ -95,6 +99,10 @@ &gpio4 { u-boot,dm-spl; + + ctrl_sleep_moci { + u-boot,dm-spl; + }; }; &gpio5 { @@ -113,6 +121,10 @@ u-boot,dm-spl; }; +&pinctrl_ctrl_sleep_moci { + u-boot,dm-spl; +}; + &pinctrl_i2c1 { u-boot,dm-spl; }; @@ -150,6 +162,18 @@ u-boot,dm-spl; }; +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &uart3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-verdin.dts b/arch/arm/dts/imx8mp-verdin.dts index a50f42f4ce..19ce3ee193 100644 --- a/arch/arm/dts/imx8mp-verdin.dts +++ b/arch/arm/dts/imx8mp-verdin.dts @@ -88,7 +88,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; }; +}; +&gpio4 { ctrl_sleep_moci { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 2876b94b2a..4662d53183 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -979,7 +979,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-fspi-nand"; - reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; reg-names = "FlexSPI", "FlexSPI-memory"; status = "disabled"; }; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 0c2dcc0792..b22d62c0d9 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -33,6 +33,18 @@ u-boot,dm-spl; }; +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + &per_bridge3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8ulp-watch-u-boot.dtsi b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi new file mode 100644 index 0000000000..a918ce0a05 --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch-u-boot.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + dsi_host: dsi-host { + compatible = "northwest,mipi-dsi"; + status = "okay"; + }; +}; + +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/firmware} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi} { + u-boot,dm-pre-reloc; +}; + +&{/firmware/scmi/protocol@15} { + u-boot,dm-pre-reloc; +}; + +&per_bridge3 { + u-boot,dm-spl; +}; + +&per_bridge4 { + u-boot,dm-spl; +}; + +&iomuxc1 { + u-boot,dm-spl; + fsl,mux_mask = <0xf00>; +}; + +&pinctrl_lpuart5 { + u-boot,dm-spl; +}; + +&s400_mu { + u-boot,dm-spl; +}; + +&lpuart5 { + u-boot,dm-spl; +}; + +&usdhc0 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&pinctrl_usdhc0 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; + +&scmi_buf { + reg = <0x0 0x1000>; /* Align page size */ +}; + +&dsi { + data-lanes-num = <4>; +}; + +&usbotg1 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb"; + fsl,usbphy = <&usbphy1>; +}; diff --git a/arch/arm/dts/imx8ulp-watch.dts b/arch/arm/dts/imx8ulp-watch.dts new file mode 100644 index 0000000000..232485486c --- /dev/null +++ b/arch/arm/dts/imx8ulp-watch.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP WATCH"; + compatible = "fsl,imx8ulp-watch", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + bootargs = "console=ttyLP1,115200 earlycon"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + linux,cma-default; + }; + + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + + +&clock_ext_ts { + /* External ts clock is 50MHZ from PHY on EVK board. */ + clock-frequency = <50000000>; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_otgid1>; + pinctrl-1 = <&pinctrl_otgid1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_otgid1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 + >; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "usmp,rm67162"; + reg = <0>; + dsi-lanes = <1>; + reset,otherway; + vcc-supply = <®_5v>; + iovcc-supply = <®_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dcnano { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&usbotg2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi index 155d29fb19..901766957d 100644 --- a/arch/arm/dts/imx8ulp.dtsi +++ b/arch/arm/dts/imx8ulp.dtsi @@ -157,6 +157,11 @@ reg = <0x11>; #power-domain-cells = <1>; }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi new file mode 100644 index 0000000000..13474a35fc --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c3 { + u-boot,dm-spl; +}; + +&fec { + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&ptn5110_2>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts new file mode 100644 index 0000000000..c82e5a9c67 --- /dev/null +++ b/arch/arm/dts/imx93-11x11-evk.dts @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + i2c8 = &flexio_i2c_master; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + audio: audio@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>; + enable-active-low; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dsi_host: dsi-host { + compatible = "synopsys,dw-mipi-dsi"; + status = "okay"; + }; + + rm67199_panel { + compatible = "raydium,rm67199"; + reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + width-mm = <68>; + height-mm = <121>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_to_adv7535: endpoint { + remote-endpoint = <&adv7535_to_dsi>; + }; + }; + + port@2 { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_to_dsi: endpoint { + remote-endpoint = <&dsi_to_adv7535>; + }; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + interrupt-parent = <&pcal6524>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585gpio: gpio@34 { + compatible = "adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&pcal6524>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + status = "okay"; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; + +&wdog3 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts new file mode 100644 index 0000000000..6eb09ec9e3 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" +#include "imx93-9x9-qsb-u-boot.dtsi" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1", "simple-panel"; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + + vsync-active = <0>; + hsync-active = <0>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + /*assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>;*/ +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 0000000000..06935ce1e4 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts new file mode 100644 index 0000000000..accb295c03 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-micfil"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 0000000000..4298a145f8 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 +#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 +#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 +#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 +#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 +#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 +#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 +#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 +#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 +#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 +#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 +#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 +#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 +#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 +#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 +#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 +#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 +#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 +#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 +#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 +#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 +#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 +#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 +#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 +#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 +#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 +#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 +#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 +#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 +#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 +#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 +#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 +#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 +#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 +#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 +#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 +#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 +#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 +#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 +#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 +#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 +#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 +#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 +#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 +#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 +#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 +#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 +#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 +#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 +#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 +#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 +#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 +#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 +#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 +#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 +#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 +#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 +#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 +#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 +#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 +#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 +#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 +#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 +#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 +#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 +#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 +#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 +#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 +#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 +#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 +#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 +#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 +#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 +#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 +#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 +#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 +#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 +#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 +#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 +#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 +#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 +#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 +#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 +#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 +#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 +#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 +#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 +#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 +#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 +#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 +#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 +#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 +#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 +#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 +#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 +#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 +#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 +#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 +#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 +#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 +#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 +#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 +#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 +#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 +#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 +#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 +#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 +#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 +#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 +#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 +#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 +#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 +#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 +#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 +#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 +#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 +#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 +#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 +#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 +#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 +#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 +#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 +#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 +#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 +#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 +#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 +#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 +#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 + +#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi new file mode 100644 index 0000000000..be4626d5e7 --- /dev/null +++ b/arch/arm/dts/imx93.dtsi @@ -0,0 +1,1503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/imx93-power.h> +#include <dt-bindings/usb/pd.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &flexspi; + isi0 = &isi_0; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + csi0 = &mipi_csi; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + edma1: dma-controller@44000000{ + compatible = "fsl,imx93-edma-v3"; + reg = <0x44000000 0x10000>, + <0x44010000 0x10000>, <0x44020000 0x10000>, + <0x44030000 0x10000>, <0x44040000 0x10000>, + <0x44050000 0x10000>, <0x44060000 0x10000>, + <0x44070000 0x10000>, <0x44080000 0x10000>, + <0x44090000 0x10000>, <0x440a0000 0x10000>, + <0x440b0000 0x10000>, <0x440c0000 0x10000>, + <0x440d0000 0x10000>, <0x440e0000 0x10000>, + <0x440f0000 0x10000>, <0x44100000 0x10000>, + <0x44110000 0x10000>, <0x44120000 0x10000>, + <0x44130000 0x10000>, <0x44140000 0x10000>, + <0x44150000 0x10000>, <0x44160000 0x10000>, + <0x44170000 0x10000>, <0x44180000 0x10000>, + <0x44190000 0x10000>, <0x441a0000 0x10000>, + <0x441b0000 0x10000>, <0x441c0000 0x10000>, + <0x441d0000 0x10000>, <0x441e0000 0x10000>, + <0x441f0000 0x10000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-err"; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + anomix_ns_gpr: blk-ctrl-anomix@42420000 { + compatible = "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + i3c1: i3c-master@44330000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_LPI2C1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_LPI2C2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_LPSPI1_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_LPSPI2_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + /* sai1 supports 2x TX/RX */ + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&anomix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + }; + + bbnsm: bbnsm@44440000 { + compatible = "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,bbnsm-rtc"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,bbnsm-pwrkey"; + regmap = <&bbnsm>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + src: src@44460000 { + compatible = "fsl,imx93-src"; + reg = <0x44460000 0x10000>; + + slice { + #address-cells = <1>; + #size-cells = <0>; + + mlmix: slice@1800 { + reg = <IMX93_POWER_DOMAIN_MLMIX>; + #power-domain-cells = <0>; + }; + + mediamix: slice@2400 { + reg = <IMX93_POWER_DOMAIN_MEDIAMIX>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + + tmu: tmu@44482000 { + compatible = "fsl,imx93-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; + #thermal-sensor-cells = <0>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + /* + 199 pdm ipi_int_hwvad_err + 200 pdm ipi_int_hwvad_event + 201 pdm ipi_int_mic_err + 202 pdm ipi_int_mic_filter + */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "clkext3"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@42000000{ + compatible = "fsl,imx93-edma-v4"; + reg = <0x42000000 0x10000>, + <0x42010000 0x8000>, <0x42018000 0x8000>, + <0x42020000 0x8000>, <0x42028000 0x8000>, + <0x42030000 0x8000>, <0x42038000 0x8000>, + <0x42040000 0x8000>, <0x42048000 0x8000>, + <0x42050000 0x8000>, <0x42058000 0x8000>, + <0x42060000 0x8000>, <0x42068000 0x8000>, + <0x42070000 0x8000>, <0x42078000 0x8000>, + <0x42080000 0x8000>, <0x42088000 0x8000>, + <0x42090000 0x8000>, <0x42098000 0x8000>, + <0x420a0000 0x8000>, <0x420a8000 0x8000>, + <0x420b0000 0x8000>, <0x420b8000 0x8000>, + <0x420c0000 0x8000>, <0x420c8000 0x8000>, + <0x420d0000 0x8000>, <0x420d8000 0x8000>, + <0x420e0000 0x8000>, <0x420e8000 0x8000>, + <0x420f0000 0x8000>, <0x420f8000 0x8000>, + <0x42100000 0x8000>, <0x42108000 0x8000>, + <0x42110000 0x8000>, <0x42118000 0x8000>, + <0x42120000 0x8000>, <0x42128000 0x8000>, + <0x42130000 0x8000>, <0x42138000 0x8000>, + <0x42140000 0x8000>, <0x42148000 0x8000>, + <0x42150000 0x8000>, <0x42158000 0x8000>, + <0x42160000 0x8000>, <0x42168000 0x8000>, + <0x42170000 0x8000>, <0x42178000 0x8000>, + <0x42180000 0x8000>, <0x42188000 0x8000>, + <0x42190000 0x8000>, <0x42198000 0x8000>, + <0x421a0000 0x8000>, <0x421a8000 0x8000>, + <0x421b0000 0x8000>, <0x421b8000 0x8000>, + <0x421c0000 0x8000>, <0x421c8000 0x8000>, + <0x421d0000 0x8000>, <0x421d8000 0x8000>, + <0x421e0000 0x8000>, <0x421e8000 0x8000>, + <0x421f0000 0x8000>, <0x421f8000 0x8000>, + <0x42200000 0x8000>, <0x42208000 0x8000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx", + "edma2-chan32-tx", "edma2-chan33-tx", + "edma2-chan34-tx", "edma2-chan35-tx", + "edma2-chan36-tx", "edma2-chan37-tx", + "edma2-chan38-tx", "edma2-chan39-tx", + "edma2-chan40-tx", "edma2-chan41-tx", + "edma2-chan42-tx", "edma2-chan43-tx", + "edma2-chan44-tx", "edma2-chan45-tx", + "edma2-chan46-tx", "edma2-chan47-tx", + "edma2-chan48-tx", "edma2-chan49-tx", + "edma2-chan50-tx", "edma2-chan51-tx", + "edma2-chan52-tx", "edma2-chan53-tx", + "edma2-chan54-tx", "edma2-chan55-tx", + "edma2-chan56-tx", "edma2-chan57-tx", + "edma2-chan58-tx", "edma2-chan59-tx", + "edma2-chan60-tx", "edma2-chan61-tx", + "edma2-chan62-tx", "edma2-chan63-tx", + "edma2-err"; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "edma"; + status = "disabled"; + }; + + wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { + compatible = "syscon"; + reg = <0x42420000 0x1000>; + }; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: wdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + assigned-clocks = <&clk IMX93_CLK_TPM4>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c-master@42520000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_LPI2C3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_LPI2C4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_LPSPI3_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_LPSPI4_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + dmas = <&edma2 17 0 0>, <&edma2 18 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + dmas = <&edma2 19 0 0>, <&edma2 20 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + dmas = <&edma2 21 0 0>, <&edma2 22 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + dmas = <&edma2 23 0 0>, <&edma2 24 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + //fsl,stop-mode = <&gpr 0x10 4 0x10 20>; + status = "disabled"; + }; + + flexspi: spi@425e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 59 0 1>, <&edma1 58 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdif: spdif@42680000 { + compatible = "fsl,imx93-spdif"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + /* XCVR PHY - SPDIF wakeup IRQ */ + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + dmas = <&edma2 87 0 0>, <&edma2 88 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + dmas = <&edma2 89 0 0>, <&edma2 90 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_LPI2C5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_LPI2C6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_LPI2C7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_LPI2C8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_LPSPI5_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_LPSPI6_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_LPSPI7_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_LPSPI8_GATE>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 1>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + flexio_i2c_master: flexio@425c0000 { + compatible = "imx,flexio_i2c_master"; + reg = <0x425c0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_FLEXIO1_GATE>, + <&clk IMX93_CLK_FLEXIO1_GATE>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + reg = <0x42890000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_WAKEUP_AXI>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + clk_csr = <0>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + epxp: epxp@4ae20000 { + compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma"; + reg = <0x4ae20000 0x10000>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pxp_ipg", "pxp_axi"; + pxp-gpr = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>; + status = "disabled"; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + isi_0: isi@4ae40000{ + compatible = "fsl,imx93-isi", "fsl,imx8-isi"; + reg = <0x4ae40000 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "per", "axi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333333>; + interface = <2 0 2>; + no-reset-control; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>; + gasket = <&media_blk_ctrl>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi: csi@4ae00000 { + compatible = "fsl,dwc-mipi-csi2-host"; + reg = <0x4ae00000 0x10000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + clock-names = "clk_core", "clk_pixel", "phy_cfg"; + assigned-clocks = <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_24M>; + assigned-clock-rates = <140000000>, <24000000>; + gasket = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>; + status = "disabled"; + }; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO2>, + <&clk IMX93_CLK_PCTL2>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO3>, + <&clk IMX93_CLK_PCTL3>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO4>, + <&clk IMX93_CLK_PCTL4>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + /* + clocks = <&clk IMX93_CLK_RGPIO1>, + <&clk IMX93_CLK_PCTL1>; + clock-names = "gpio", "port"; + */ + gpio-ranges = <&iomuxc 0 0 32>; + }; + + ocotp: efuse@47510000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x1000>; + status = "disabled"; + }; + + s4muap: s4muap@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "txirq", "rxirq"; + #mbox-cells = <2>; + status = "okay"; + }; + + sentnl_mu: sentnl-mu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx-sentnl"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,sentnl_mu_id = <2>; + fsl,sentnl_mu_max_users = <4>; + status = "okay"; + dma-ranges = <0x80000000 0x80000000 0x20000000>; + }; + + media_blk_ctrl: blk-ctrl@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + + dphy: dphy { + compatible = "fsl,imx93-mipi-dphy"; + clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>, + <&clk IMX93_CLK_24M>; + clock-names = "phy_cfg", "phy_ref"; + assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + }; + + parallel_disp_fmt: dpi { + compatible = "fsl,imx93-parallel-display-format"; + /* power-domains = <&mediamix>; [Not enable for U-Boot], otherwise driver probe fail */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + }; + }; + }; + + ldb: ldb@4ac10020 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-ldb"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + gpr = <&media_blk_ctrl>; + power-domains = <&mediamix>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb_ch0: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + }; + }; + + ldb_phy: phy@4ac10024 { + compatible = "fsl,imx93-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_APB>; + clock-names = "apb"; + power-domains = <&mediamix>; + status = "disabled"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + dsi: dsi@4ae10000 { + compatible = "fsl,imx93-mipi-dsi"; + reg = <0x4ae10000 0x4000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "byte", "pclk"; + assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <20000000>, <133333334>; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsi>; + }; + }; + }; + }; + + lcdif: lcd-controller@4ae30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + fsl,gpr = <&media_blk_ctrl>; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_LCDIF_GATE>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_24M>, + <&clk IMX93_CLK_VIDEO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + lcdif_disp: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + lcdif_to_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_to_lcdif>; + }; + + lcdif_to_ldb: endpoint@1 { + reg = <1>; + remote-endpoint = <&ldb_ch0>; + }; + + lcdif_to_dpi: endpoint@2 { + reg = <2>; + remote-endpoint = <&dpi_to_lcdif>; + }; + }; + }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp>; + }; +}; diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi new file mode 100644 index 0000000000..3711e42419 --- /dev/null +++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2022 NXP + */ + +&{/soc} { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index bf96af7e36..82df2f11bb 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -6,6 +6,7 @@ */ #include "ls1021a.dtsi" +#include "ls1021a-twr-u-boot.dtsi" / { model = "LS1021A TWR Board"; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 63bb3fb2bf..36f51e0792 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -61,6 +61,14 @@ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ +#define MXC_CPU_IMX93 0xC1 /* dummy ID */ +#define MXC_CPU_IMX9351 0xC2 /* dummy ID */ +#define MXC_CPU_IMX9332 0xC3 /* dummy ID */ +#define MXC_CPU_IMX9331 0xC4 /* dummy ID */ +#define MXC_CPU_IMX9322 0xC5 /* dummy ID */ +#define MXC_CPU_IMX9321 0xC6 /* dummy ID */ +#define MXC_CPU_IMX9312 0xC7 /* dummy ID */ +#define MXC_CPU_IMX9311 0xC8 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 @@ -68,6 +76,7 @@ #define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_IMXRT 0xB0 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ +#define MXC_SOC_IMX9 0xC0 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c03..5e4fbecf05 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -724,6 +724,8 @@ void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + static inline void reg32_write(unsigned long addr, u32 val) { writel(val, addr); @@ -740,9 +742,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit) } #define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) #define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) extern struct dram_cfg_param ddrphy_trained_csr[]; extern uint32_t ddrphy_trained_csr_num; diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index f8115ce3fa..e07012e7d6 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -67,6 +67,8 @@ #define FEC_QUIRK_ENET_MAC +#define IMG_CONTAINER_BASE (0x22010000UL) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h index b002970fd8..cdea5d6f3c 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -30,6 +30,7 @@ enum { IMX8ULP_PAD_PTC8__FLEXSPI0_A_DATA2 = IOMUX_PAD(0x0120, 0x0120, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), IMX8ULP_PAD_PTC9__FLEXSPI0_A_DATA1 = IOMUX_PAD(0x0124, 0x0124, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), IMX8ULP_PAD_PTC10__FLEXSPI0_A_DATA0 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), IMX8ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0000, 0x0000, 0x8, 0x0000, 0x0, 0), @@ -72,6 +73,6 @@ enum { IMX8ULP_PAD_PTF5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0A6C, 0x2, 0), IMX8ULP_PAD_PTF0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0A68, 0x2, 0), IMX8ULP_PAD_PTF1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0A64, 0x2, 0), - + IMX8ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), }; #endif /* __ASM_ARCH_IMX8ULP_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h deleted file mode 100644 index b3e6b3fa45..0000000000 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - -#ifndef __S400_API_H__ -#define __S400_API_H__ - -#define AHAB_VERSION 0x6 -#define AHAB_CMD_TAG 0x17 -#define AHAB_RESP_TAG 0xe1 - -#define AHAB_LOG_CID 0x21 -#define AHAB_AUTH_OEM_CTNR_CID 0x87 -#define AHAB_VERIFY_IMG_CID 0x88 -#define AHAB_RELEASE_CTNR_CID 0x89 -#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 -#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 -#define AHAB_READ_FUSE_REQ_CID 0x97 -#define AHAB_GET_FW_VERSION_CID 0x9D -#define AHAB_RELEASE_RDC_REQ_CID 0xC4 -#define AHAB_WRITE_FUSE_REQ_CID 0xD6 -#define AHAB_CAAM_RELEASE_CID 0xD7 - -#define S400_MAX_MSG 255U - -struct imx8ulp_s400_msg { - u8 version; - u8 size; - u8 command; - u8 tag; - u32 data[(S400_MAX_MSG - 1U)]; -}; - -int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response); -int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); -int ahab_release_container(u32 *response); -int ahab_verify_image(u32 img_id, u32 *response); -int ahab_forward_lifecycle(u16 life_cycle, u32 *response); -int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); -int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); -int ahab_release_caam(u32 core_did, u32 *response); -int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); -int ahab_dump_buffer(u32 *buffer, u32 buffer_length); - -#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 5f030eaa0a..e240ee6fca 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -19,5 +19,6 @@ enum boot_device get_boot_device(void); void set_lpav_qos(void); void load_lposc_fuse(void); bool m33_image_booted(void); +bool is_m33_handshake_necessary(void); int m33_image_handshake(ulong timeout_ms); #endif diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 0000000000..d326a6ea51 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT 0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT 5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT 7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT 14 +#define LPTMR2_CLK_ROOT 15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT 33 +#define LPI2C2_CLK_ROOT 34 +#define LPI2C3_CLK_ROOT 35 +#define LPI2C4_CLK_ROOT 36 +#define LPI2C5_CLK_ROOT 37 +#define LPI2C6_CLK_ROOT 38 +#define LPI2C7_CLK_ROOT 39 +#define LPI2C8_CLK_ROOT 40 +#define LPSPI1_CLK_ROOT 41 +#define LPSPI2_CLK_ROOT 42 +#define LPSPI3_CLK_ROOT 43 +#define LPSPI4_CLK_ROOT 44 +#define LPSPI5_CLK_ROOT 45 +#define LPSPI6_CLK_ROOT 46 +#define LPSPI7_CLK_ROOT 47 +#define LPSPI8_CLK_ROOT 48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT 51 +#define USDHC2_CLK_ROOT 52 +#define USDHC3_CLK_ROOT 53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT 67 +#define ML_CLK_ROOT 68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT 72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT 74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT 80 +#define TSTMR2_CLK_ROOT 81 +#define MQS1_CLK_ROOT 82 +#define MQS2_CLK_ROOT 83 +#define AUDIO_XCVR_CLK_ROOT 84 +#define SPDIF_CLK_ROOT 85 +#define ENET_CLK_ROOT 86 +#define ENET_TIMER1_CLK_ROOT 87 +#define ENET_TIMER2_CLK_ROOT 88 +#define ENET_REF_CLK_ROOT 89 +#define ENET_REF_PHY_CLK_ROOT 90 +#define I3C1_SLOW_CLK_ROOT 91 +#define I3C2_SLOW_CLK_ROOT 92 +#define USB_PHY_BURUNIN_CLK_ROOT 93 +#define PAL_CAME_SCAN_CLK_ROOT 94 +#define CLK_ROOT_NUM 95 + +#define CCGR_A55 0 +#define CCGR_CM33 1 +#define CCGR_ARMTROUT 2 +#define CCGR_SENT 3 +#define CCGR_BUSM 4 +#define CCGR_BUS7 5 +#define CCGR_BUSD 6 +#define CCGR_ANAD 7 +#define CCGR_SRC 8 +#define CCGR_CCM 9 +#define CCGR_GPC 10 +#define CCGR_ADC 11 +#define CCGR_WDG1 12 +#define CCGR_WDG2 13 +#define CCGR_WDG3 14 +#define CCGR_WDG4 15 +#define CCGR_WDG5 16 +#define CCGR_SEM1 17 +#define CCGR_SEM2 18 +#define CCGR_MUA 19 +#define CCGR_MUB 20 +#define CCGR_DMA1 21 +#define CCGR_DMA2 22 +#define CCGR_ROMCA55 23 +#define CCGR_ROMCM33 24 +#define CCGR_QSP1 25 +#define CCGR_AONRDC 26 +#define CCGR_WKUPRDC 27 +#define CCGR_FUSE 28 +#define CCGR_SNVH 29 +#define CCGR_SNVS 30 +#define CCGR_TRAC 31 +#define CCGR_SWO 32 +#define CCGR_IOCG 33 +#define CCGR_PIO1 34 +#define CCGR_PIO2 35 +#define CCGR_PIO3 36 +#define CCGR_PIO4 37 +#define CCGR_FIO1 38 +#define CCGR_FIO2 39 +#define CCGR_PIT1 40 +#define CCGR_PIT2 41 +#define CCGR_GPT1 42 +#define CCGR_GPT2 43 +#define CCGR_TPM1 44 +#define CCGR_TPM2 45 +#define CCGR_TPM3 46 +#define CCGR_TPM4 47 +#define CCGR_TPM5 48 +#define CCGR_TPM6 49 +#define CCGR_CAN1 50 +#define CCGR_CAN2 51 +#define CCGR_URT1 52 +#define CCGR_URT2 53 +#define CCGR_URT3 54 +#define CCGR_URT4 55 +#define CCGR_URT5 56 +#define CCGR_URT6 57 +#define CCGR_URT7 58 +#define CCGR_URT8 59 +#define CCGR_I2C1 60 +#define CCGR_I2C2 61 +#define CCGR_I2C3 62 +#define CCGR_I2C4 63 +#define CCGR_I2C5 64 +#define CCGR_I2C6 65 +#define CCGR_I2C7 66 +#define CCGR_I2C8 67 +#define CCGR_SPI1 68 +#define CCGR_SPI2 69 +#define CCGR_SPI3 70 +#define CCGR_SPI4 71 +#define CCGR_SPI5 72 +#define CCGR_SPI6 73 +#define CCGR_SPI7 74 +#define CCGR_SPI8 75 +#define CCGR_I3C1 76 +#define CCGR_I3C2 77 +#define CCGR_USDHC1 78 +#define CCGR_USDHC2 79 +#define CCGR_USDHC3 80 +#define CCGR_SAI1 81 +#define CCGR_SAI2 82 +#define CCGR_SAI3 83 +#define CCGR_W2AO 84 +#define CCGR_AO2W 85 +#define CCGR_MIPIC 86 +#define CCGR_MIPID 87 +#define CCGR_LVDS 88 +#define CCGR_LCDIF 89 +#define CCGR_PXP 90 +#define CCGR_ISI 91 +#define CCGR_NMED 92 +#define CCGR_DFI 93 +#define CCGR_DDRC 94 +#define CCGR_DFIC 95 +#define CCGR_DSSI 96 +#define CCGR_DBYP 97 +#define CCGR_DAPB 98 +#define CCGR_DRAMP 99 +#define CCGR_DCLKC 100 +#define CCGR_NCTL 101 +#define CCGR_GIC 102 +#define CCGR_NICAPB 103 +#define CCGR_USBC 104 +#define CCGR_USBT 105 +#define CCGR_HSIO 106 +#define CCGR_PDM 107 +#define CCGR_MQS1 108 +#define CCGR_MQS2 109 +#define CCGR_AXCVR 110 +#define CCGR_MECC 111 +#define CCGR_SPDIF 112 +#define CCGR_ML2NIC 113 +#define CCGR_MED2NIC 114 +#define CCGR_HSIO2NIC 115 +#define CCGR_W2NIC 116 +#define CCGR_NIC2W 117 +#define CCGR_NIC2DDR 118 +#define CCGR_HSIO32K 119 +#define CCGR_ENET1 120 +#define CCGR_ENETQOS 121 +#define CCGR_SYSCNT 122 +#define CCGR_TSTMR1 123 +#define CCGR_TSTMR2 124 +#define CCGR_TMC 125 +#define CCGR_PMRO 126 +#define CCGR_NUM 127 + +#define SHARED_GPR_EXT_CLK 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT1 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0) +#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1) +#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0) + +#define SHARED_GPR_A55_CLK 1 +#define SHARED_GPR_A55_CLK_SEL_CCM 0 +#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0) + +#define SHARED_GPR_DRAM_CLK 2 +#define SHARED_GPR_DRAM_CLK_SEL_PLL 0 +#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) + +#define SHARED_GPR_NUM 8 +#define PRIVATE_GPR_NUM 8 + +#define CLK_ROOT_STATUS_OFF BIT(24) +#define CLK_ROOT_STATUS_CHANGING BIT(31) +#define CLK_ROOT_MUX_MASK GENMASK(9, 8) +#define CLK_ROOT_MUX_SHIFT 8 +#define CLK_ROOT_DIV_MASK GENMASK(7, 0) + +#define CCM_AUTHEN_LOCK_TZ BIT(11) +#define CCM_AUTHEN_TZ_NS BIT(9) +#define CCM_AUTHEN_TZ_USER BIT(8) +#define CCM_AUTHEN_CPULPM_MODE BIT(2) +#define CCM_AUTHEN_AUTO_CTRL BIT(3) + +#endif diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h new file mode 100644 index 0000000000..758ee26ff2 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan at nxp.com> + */ + +#ifndef __CLOCK_IMX9__ +#define __CLOCK_IMX9__ + +#include <linux/bitops.h> + +#define MHZ(x) ((x) * 1000000UL) + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +enum ccm_clk_src { + OSC_24M_CLK, + ARM_PLL, + ARM_PLL_CLK, + SYS_PLL_PG, + SYS_PLL_PFD0_PG, + SYS_PLL_PFD0, + SYS_PLL_PFD0_DIV2, + SYS_PLL_PFD1_PG, + SYS_PLL_PFD1, + SYS_PLL_PFD1_DIV2, + SYS_PLL_PFD2_PG, + SYS_PLL_PFD2, + SYS_PLL_PFD2_DIV2, + AUDIO_PLL, + AUDIO_PLL_CLK, + DRAM_PLL, + DRAM_PLL_CLK, + VIDEO_PLL, + VIDEO_PLL_CLK, + OSCPLL_END, + EXT_CLK, +}; + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_FLEXSPI_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_UART_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +struct ccm_obs { + u32 direct; + u32 reserved[31]; +}; + +struct ccm_gpr { + u32 gpr; + u32 gpr_set; + u32 gpr_clr; + u32 gpr_tog; + u32 authen; + u32 authen_set; + u32 authen_clr; + u32 authen_tog; +}; + +struct ccm_lpcg_oscpll { + u32 direct; + u32 lpm_status0; + u32 lpm_status1; + u32 reserved0; + u32 lpm0; + u32 lpm1; + u32 reserved1; + u32 lpm_cur; + u32 status0; + u32 status1; + u32 reserved2[2]; + u32 authen; + u32 reserved3[3]; +}; + +struct ccm_root { + u32 control; + u32 control_set; + u32 control_clr; + u32 control_tog; + u32 reserved[4]; + u32 status0; + u32 reserved1[3]; + u32 authen; + u32 reserved2[19]; +}; + +struct ccm_reg { + struct ccm_root clk_roots[95]; /* 0x0 */ + u32 reserved_0[1312]; + struct ccm_obs clk_obs[6]; /* 0x4400 */ + u32 reserved_1[64]; + struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */ + u32 reserved_2[192]; + struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */ + u32 reserved_3[192]; + struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */ + u32 reserved_4[2768]; + struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */ +}; + +struct ana_pll_reg_elem { + u32 reg; + u32 reg_set; + u32 reg_clr; + u32 reg_tog; +}; + +struct ana_pll_dfs { + struct ana_pll_reg_elem dfs_ctrl; + struct ana_pll_reg_elem dfs_div; +}; + +struct ana_pll_reg { + struct ana_pll_reg_elem ctrl; + struct ana_pll_reg_elem ana_prg; + struct ana_pll_reg_elem test; + struct ana_pll_reg_elem ss; /* Spread spectrum */ + struct ana_pll_reg_elem num; /* numerator */ + struct ana_pll_reg_elem denom; /* demoninator */ + struct ana_pll_reg_elem div; + struct ana_pll_dfs dfs[4]; + u32 pll_status; + u32 dfs_status; + u32 reserved[2]; +}; + +struct anatop_reg { + u32 osc_ctrl; + u32 osc_state; + u32 reserved_0[510]; + u32 chip_version; + u32 reserved_1[511]; + struct ana_pll_reg arm_pll; + struct ana_pll_reg sys_pll; + struct ana_pll_reg audio_pll; + struct ana_pll_reg dram_pll; + struct ana_pll_reg video_pll; +}; + +#define PLL_CTRL_HW_CTRL_SEL BIT(16) +#define PLL_CTRL_CLKMUX_BYPASS BIT(2) +#define PLL_CTRL_CLKMUX_EN BIT(1) +#define PLL_CTRL_POWERUP BIT(0) + +#define PLL_STATUS_PLL_LOCK BIT(0) +#define PLL_DFS_CTRL_ENABLE BIT(31) +#define PLL_DFS_CTRL_CLKOUT BIT(30) +#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29) +#define PLL_DFS_CTRL_BYPASS BIT(23) + +#define PLL_SS_EN BIT(15) + +struct imx_intpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; +}; + +struct imx_fracpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; + int mfn; + int mfd; +}; + +#define INT_PLL_RATE(_rate, _r, _m, _o) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + } + +#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + .mfn = (_n), \ + .mfd = (_d), \ + } + +struct clk_root_map { + u32 clk_root_id; + u32 mux_type; +}; + + +int clock_init(void); +u32 get_clk_src_rate(enum ccm_clk_src source); +u32 get_lpuart_clk(void); +void init_uart_clk(u32 index); +void init_clk_usdhc(u32 index); +int enable_i2c_clk(unsigned char enable, u32 i2c_num); +u32 imx_get_i2cclk(u32 i2c_num); +u32 mxc_get_clock(enum mxc_clock clk); +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); +void set_arm_core_max_clk(void); + +int configure_intpll(enum ccm_clk_src pll, u32 freq); + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val); +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll); +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div); +u32 ccm_clk_root_get_rate(u32 clk_root_id); +int ccm_clk_root_tz_access(u32 clk_root_id, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_lpcg_on(u32 lpcg, bool enable); +int ccm_lpcg_lpm(u32 lpcg, bool enable); +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val); +bool ccm_lpcg_is_clk_on(u32 lpcg); +int ccm_lpcg_tz_access(u32 lpcg, + bool non_secure, bool user_mode, bool lock_tz); +int ccm_shared_gpr_set(u32 gpr, u32 val); +int ccm_shared_gpr_get(u32 gpr, u32 *val); +int ccm_shared_gpr_tz_access(u32 gpr, + bool non_secure, bool user_mode, bool lock_tz); + +void enable_usboh3_clk(unsigned char enable); +int set_clk_enet(enum enet_freq type); +int set_clk_eqos(enum enet_freq type); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +#endif diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h new file mode 100644 index 0000000000..af5e6b5764 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include <asm/io.h> +#include <asm/types.h> + +#define DDR_CTL_BASE 0x4E300000 +#define DDR_PHY_BASE 0x4E100000 +#define DDRMIX_BLK_CTRL_BASE 0x4E010000 + +#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) +#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) +#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) +#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114) +#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) +#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) +#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) + +#define SRC_BASE_ADDR (0x44460000) +#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) +#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20) +#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24) + +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + (X * 0x2000000)) +#define DDRPHY_MEM(X) (DDR_PHY_BASE + (X * 0x2000000) + 0x50000) + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +int ddr_init(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); +void board_dram_ecc_scrub(void); +void ddrc_inline_ecc_scrub(unsigned int start_address, + unsigned int range_address); +void ddrc_inline_ecc_scrub_end(unsigned int start_address, + unsigned int range_address); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +void get_trained_CDD(unsigned int fsp); + +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +#endif diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h new file mode 100644 index 0000000000..599f7511c3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_GPIO_H +#define __ASM_ARCH_IMX9_GPIO_H + +#include <common.h> + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_pidr; + u8 gpio_pxdr[32]; +}; + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h new file mode 100644 index 0000000000..593409c30c --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_REGS_H__ +#define __ASM_ARCH_IMX9_REGS_H__ + +#define ARCH_MXC +#define FEC_QUIRK_ENET_MAC + +#define IOMUXC_BASE_ADDR 0x443C0000UL +#define CCM_BASE_ADDR 0x44450000UL +#define CCM_CCGR_BASE_ADDR 0x44458000UL +#define SYSCNT_CTRL_BASE_ADDR 0x44290000 + +#define WDG3_BASE_ADDR 0x42490000UL +#define WDG4_BASE_ADDR 0x424a0000UL +#define WDG5_BASE_ADDR 0x424b0000UL + +#define ANATOP_BASE_ADDR 0x44480000UL + +#define USB1_BASE_ADDR 0x4c100000 +#define USB2_BASE_ADDR 0x4c200000 + +#define USB_BASE_ADDR USB1_BASE_ADDR + +#define FSB_BASE_ADDR 0x47510000 + +#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000 +#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000 + +#define SRC_IPS_BASE_ADDR (0x44460000) +#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x0000) + +#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000) +#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800) +#define SRC_MEDIA_RBASE (SRC_IPS_BASE_ADDR + 0x2400) +#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800) + +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0) +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2) +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4) +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12) + +#define IMG_CONTAINER_BASE (0x80000000UL) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#include <stdbool.h> + +#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) +#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + +#define BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK BIT(2) + +enum mix_power_domain { + MIX_PD_MEDIAMIX, + MIX_PD_MLMIX, + MIX_PD_DDRMIX, +}; + +enum src_mix_slice_id { + SRC_MIX_EDGELOCK = 0, + SRC_MIX_AONMIX = 1, + SRC_MIX_WAKEUPMIX = 2, + SRC_MIX_DDRMIX = 3, + SRC_MIX_DDRPHY = 4, + SRC_MIX_ML = 5, + SRC_MIX_NIC = 6, + SRC_MIX_HSIO = 7, + SRC_MIX_MEDIA = 8, + SRC_MIX_CM33 = 9, + SRC_MIX_CA55C0 = 10, + SRC_MIX_CA55C1 = 11, + SRC_MIX_CA55CLUSTER = 12, +}; + +enum src_mem_slice_id { + SRC_MEM_AONMIX = 0, + SRC_MEM_WAKEUPMIX = 1, + SRC_MEM_DDRMIX = 2, + SRC_MEM_DDRPHY = 3, + SRC_MEM_ML = 4, + SRC_MEM_NIC = 5, + SRC_MEM_OCRAM = 6, + SRC_MEM_HSIO = 7, + SRC_MEM_MEDIA = 8, + SRC_MEM_CA55C0 = 9, + SRC_MEM_CA55C1 = 10, + SRC_MEM_CA55CLUSTER = 11, + SRC_MEM_L3 = 12, +}; + +struct blk_ctrl_s_aonmix_regs { + u32 cm33_irq_mask[7]; + u32 initnsvtor; + u32 reserved1[8]; + u32 ca55_irq_mask[7]; + u32 initsvtor; + u32 m33_cfg; + u32 reserved2[11]; + u32 axbs_aon_ctrl; + u32 reserved3[27]; + u32 dap_access_stkybit; + u32 reserved4[3]; + u32 lp_handshake[2]; + u32 ca55_cpuwait; + u32 ca55_rvbaraddr0_l; + u32 ca55_rvbaraddr0_h; + u32 ca55_rvbaraddr1_l; + u32 ca55_rvbaraddr1_h; + u32 s401_irq_mask; + u32 s401_reset_req_mask; + u32 s401_halt_st; + u32 ca55_mode; + u32 nmi_mask; + u32 nmi_clr; + u32 wdog_any_mask; + u32 s4v1_ipi_noclk_ref1; +}; + +struct blk_ctrl_wakeupmix_regs { + u32 upper_addr; + u32 ipg_debug_cm33; + u32 reserved[2]; + u32 qch_dis; + u32 ssi; + u32 reserved1[1]; + u32 dexsc_err; + u32 mqs_setting; + u32 sai_clk_sel; + u32 eqos_gpr; + u32 enet_clk_sel; + u32 reserved2[1]; + u32 volt_detect; + u32 i3c2_wakeup; + u32 ipg_debug_ca55c0; + u32 ipg_debug_ca55c1; + u32 axi_attr_cfg; + u32 i3c2_sda_irq; +}; + +struct mu_type { + u32 ver; + u32 par; + u32 cr; + u32 sr; + u32 reserved0[60]; + u32 fcr; + u32 fsr; + u32 reserved1[2]; + u32 gier; + u32 gcr; + u32 gsr; + u32 reserved2; + u32 tcr; + u32 tsr; + u32 rcr; + u32 rsr; + u32 reserved3[52]; + u32 tr[16]; + u32 reserved4[16]; + u32 rr[16]; + u32 reserved5[14]; + u32 mu_attr; +}; + +struct src_general_regs { + u32 reserved[1]; + u32 authen_ctrl; + u32 reserved1[2]; + u32 scr; + u32 srtmr; + u32 srmask; + u32 reserved2[1]; + u32 srmr[6]; + u32 reserved3[2]; + u32 sbmr[2]; + u32 reserved4[2]; + u32 srsr; + u32 gpr[19]; + u32 reserved5[24]; + u32 gpr20; + u32 cm_quiesce; + u32 cold_reset_ssar_ack_ctrl; + u32 sp_iso_ctrl; + u32 rom_lp_ctrl; + u32 a55_deny_stat; +}; + +struct src_mem_slice_regs { + u32 reserved[1]; + u32 mem_ctrl; + u32 memlp_ctrl_0; + u32 reserved1[1]; + u32 memlp_ctrl_1; + u32 memlp_ctrl_2; + u32 mem_stat; +}; + +struct src_mix_slice_regs { + u32 reserved[1]; + u32 authen_ctrl; + u32 reserved1[2]; + u32 lpm_setting[3]; + u32 reserved2[1]; + u32 slice_sw_ctrl; + u32 single_reset_sw_ctrl; + u32 reserved3[6]; + u32 a55_hdsk_ack_ctrl; + u32 a55_hdsk_ack_stat; + u32 reserved4[2]; + u32 ssar_ack_ctrl; + u32 ssar_ack_stat; + u32 reserved5[1]; + u32 iso_off_dly_por; + u32 iso_on_dly; + u32 iso_off_dly; + u32 psw_off_lf_dly; + u32 reserved6[1]; + u32 psw_off_hf_dly; + u32 psw_on_lf_dly; + u32 psw_on_hf_dly; + u32 reserved7[1]; + u32 psw_ack_ctrl[2]; + u32 psw_ack_stat; + u32 reserved8[1]; + u32 mtr_ack_ctrl; + u32 mtr_ack_stat; + u32 reserved9[2]; + u32 upi_stat[4]; + u32 fsm_stat; + u32 func_stat; +}; + +bool is_usb_boot(void); +void disconnect_from_pc(void); +#define is_boot_from_usb is_usb_boot + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h new file mode 100644 index 0000000000..ae0eaa8354 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX93_PINS_H__ +#define __ASM_ARCH_IMX93_PINS_H__ + +#include <asm/mach-imx/iomux-v3.h> + +enum { + MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x01B0, 0x0000, 0, 0x03D8, 0, 0), + MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x01B0, 0x0000, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x01B0, 0x0000, 3, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x01B0, 0x0000, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x01B0, 0x0000, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x01B0, 0x0000, 6, 0x0430, 0, 0), + + MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x01B4, 0x0004, 0, 0x03DC, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x01B4, 0x0004, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x01B4, 0x0004, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x01B4, 0x0004, 6, 0x0000, 0, 0), + + MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x01B8, 0x0008, 0, 0x03D4, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x01B8, 0x0008, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x01B8, 0x0008, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x01B8, 0x0008, 6, 0x042C, 0, 0), + + MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x01BC, 0x000C, 0, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x01BC, 0x000C, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x01BC, 0x000C, 3, 0x0364, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x01BC, 0x000C, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x01BC, 0x000C, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x01BC, 0x000C, 6, 0x0434, 0, 0), + + MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x01C0, 0x0010, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x01C0, 0x0010, 1 | IOMUX_CONFIG_SION, 0x03E4, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x01C0, 0x0010, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x01C0, 0x0010, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x01C0, 0x0010, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x01C0, 0x0010, 5, 0x0434, 1, 0), + MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x01C0, 0x0010, 6 | IOMUX_CONFIG_SION, 0x03EC, 0, 0), + MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x01C0, 0x0010, 7, 0x036C, 0, 0), + + MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x01C4, 0x0014, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x01C4, 0x0014, 1 | IOMUX_CONFIG_SION, 0x03E0, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x01C4, 0x0014, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x01C4, 0x0014, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x01C4, 0x0014, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x01C4, 0x0014, 5, 0x0430, 1, 0), + MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x01C4, 0x0014, 6 | IOMUX_CONFIG_SION, 0x03E8, 0, 0), + MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x01C4, 0x0014, 7, 0x0370, 0, 0), + + MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x01C8, 0x0018, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x01C8, 0x0018, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x01C8, 0x0018, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x01C8, 0x0018, 5, 0x042C, 1, 0), + MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x01C8, 0x0018, 6 | IOMUX_CONFIG_SION, 0x03F4, 0, 0), + MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x01C8, 0x0018, 7, 0x0374, 0, 0), + + MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x01CC, 0x001C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x01CC, 0x001C, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x01CC, 0x001C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x01CC, 0x001C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x01CC, 0x001C, 6 | IOMUX_CONFIG_SION, 0x03F0, 0, 0), + MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x01CC, 0x001C, 7, 0x0378, 0, 0), + + MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x01D0, 0x0020, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x01D0, 0x0020, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x01D0, 0x0020, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x01D0, 0x0020, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x01D0, 0x0020, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x01D0, 0x0020, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x01D0, 0x0020, 6 | IOMUX_CONFIG_SION, 0x03F4, 1, 0), + MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x01D0, 0x0020, 7, 0x037C, 0, 0), + + MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x01D4, 0x0024, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x01D4, 0x0024, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 = IOMUX_PAD(0x01D4, 0x0024, 2, 0x0438, 0, 0), + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x01D4, 0x0024, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x01D4, 0x0024, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x01D4, 0x0024, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x01D4, 0x0024, 6 | IOMUX_CONFIG_SION, 0x03F0, 1, 0), + MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x01D4, 0x0024, 7, 0x0380, 0, 0), + + MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x01D8, 0x0028, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x01D8, 0x0028, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 = IOMUX_PAD(0x01D8, 0x0028, 2, 0x043C, 0, 0), + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x01D8, 0x0028, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x01D8, 0x0028, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x01D8, 0x0028, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x01D8, 0x0028, 6 | IOMUX_CONFIG_SION, 0x03FC, 0, 0), + MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x01D8, 0x0028, 7, 0x0384, 0, 0), + + MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x01DC, 0x002C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x01DC, 0x002C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 = IOMUX_PAD(0x01DC, 0x002C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x01DC, 0x002C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x01DC, 0x002C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x01DC, 0x002C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x01DC, 0x002C, 6 | IOMUX_CONFIG_SION, 0x03F8, 0, 0), + MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x01DC, 0x002C, 7, 0x0388, 0, 0), + + MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x01E0, 0x0030, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x01E0, 0x0030, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 = IOMUX_PAD(0x01E0, 0x0030, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x01E0, 0x0030, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x01E0, 0x0030, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x01E0, 0x0030, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x01E0, 0x0030, 6 | IOMUX_CONFIG_SION, 0x03FC, 1, 0), + MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x01E0, 0x0030, 7, 0x038C, 0, 0), + + MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x01E4, 0x0034, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x01E4, 0x0034, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 = IOMUX_PAD(0x01E4, 0x0034, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x01E4, 0x0034, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x01E4, 0x0034, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x01E4, 0x0034, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x01E4, 0x0034, 6 | IOMUX_CONFIG_SION, 0x03F8, 1, 0), + MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x01E4, 0x0034, 7, 0x0390, 0, 0), + + MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x01E8, 0x0038, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x01E8, 0x0038, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 = IOMUX_PAD(0x01E8, 0x0038, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x01E8, 0x0038, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x01E8, 0x0038, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x01E8, 0x0038, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x01E8, 0x0038, 6 | IOMUX_CONFIG_SION, 0x0404, 0, 0), + MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x01E8, 0x0038, 7, 0x0394, 0, 0), + + MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x01EC, 0x003C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x01EC, 0x003C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 = IOMUX_PAD(0x01EC, 0x003C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x01EC, 0x003C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x01EC, 0x003C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x01EC, 0x003C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x01EC, 0x003C, 6 | IOMUX_CONFIG_SION, 0x0400, 0, 0), + MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x01EC, 0x003C, 7, 0x0398, 0, 0), + + MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x01F0, 0x0040, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x01F0, 0x0040, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 = IOMUX_PAD(0x01F0, 0x0040, 2, 0x0440, 0, 0), + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x01F0, 0x0040, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x01F0, 0x0040, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x01F0, 0x0040, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x01F0, 0x0040, 6 | IOMUX_CONFIG_SION, 0x0404, 1, 0), + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x01F0, 0x0040, 7, 0x0450, 0, 0), + + MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x01F4, 0x0044, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x01F4, 0x0044, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 = IOMUX_PAD(0x01F4, 0x0044, 2, 0x0444, 0, 0), + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x01F4, 0x0044, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x01F4, 0x0044, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x01F4, 0x0044, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x01F4, 0x0044, 6 | IOMUX_CONFIG_SION, 0x0400, 1, 0), + MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x01F4, 0x0044, 7, 0x039C, 0, 0), + + MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x01F8, 0x0048, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x01F8, 0x0048, 1, 0x041C, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 = IOMUX_PAD(0x01F8, 0x0048, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x01F8, 0x0048, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x01F8, 0x0048, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x01F8, 0x0048, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x01F8, 0x0048, 6, 0x0428, 0, 0), + MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x01F8, 0x0048, 7, 0x03A0, 0, 0), + + MX93_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x01FC, 0x004C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x01FC, 0x004C, 1, 0x0418, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 = IOMUX_PAD(0x01FC, 0x004C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x01FC, 0x004C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x01FC, 0x004C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x01FC, 0x004C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x01FC, 0x004C, 6, 0x0424, 0, 0), + MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x01FC, 0x004C, 7, 0x03A4, 0, 0), + + MX93_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x0200, 0x0050, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x0200, 0x0050, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 = IOMUX_PAD(0x0200, 0x0050, 2, 0x0440, 1, 0), + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x0200, 0x0050, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x0200, 0x0050, 4, 0x0414, 0, 0), + MX93_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x0200, 0x0050, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x0200, 0x0050, 6, 0x0420, 0, 0), + MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x0200, 0x0050, 7, 0x03A8, 0, 0), + + MX93_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x0204, 0x0054, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x0204, 0x0054, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 = IOMUX_PAD(0x0204, 0x0054, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x0204, 0x0054, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x0204, 0x0054, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x0204, 0x0054, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x0204, 0x0054, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x0204, 0x0054, 7, 0x03AC, 0, 0), + + MX93_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x0208, 0x0058, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x0208, 0x0058, 1, 0x044C, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 = IOMUX_PAD(0x0208, 0x0058, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x0208, 0x0058, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x0208, 0x0058, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x0208, 0x0058, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x0208, 0x0058, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x0208, 0x0058, 7, 0x03B0, 0, 0), + + MX93_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x020C, 0x005C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x020C, 0x005C, 1, 0x0450, 1, 0), + MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 = IOMUX_PAD(0x020C, 0x005C, 2, 0x0444, 1, 0), + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x020C, 0x005C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x020C, 0x005C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x020C, 0x005C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x020C, 0x005C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 = IOMUX_PAD(0x020C, 0x005C, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x0210, 0x0060, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 = IOMUX_PAD(0x0210, 0x0060, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 = IOMUX_PAD(0x0210, 0x0060, 2, 0x0438, 1, 0), + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x0210, 0x0060, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x0210, 0x0060, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x0210, 0x0060, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x0210, 0x0060, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x0210, 0x0060, 7, 0x03B4, 0, 0), + + MX93_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x0214, 0x0064, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 = IOMUX_PAD(0x0214, 0x0064, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x0214, 0x0064, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x0214, 0x0064, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x0214, 0x0064, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x0214, 0x0064, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x0214, 0x0064, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x0214, 0x0064, 7, 0x044C, 1, 0), + + MX93_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x0218, 0x0068, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x0218, 0x0068, 1, 0x0458, 0, 0), + MX93_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x0218, 0x0068, 2, 0x0454, 0, 0), + MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x0218, 0x0068, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x0218, 0x0068, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x0218, 0x0068, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x0218, 0x0068, 6 | IOMUX_CONFIG_SION, 0x03EC, 1, 0), + MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x0218, 0x0068, 7, 0x03B8, 0, 0), + + MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x021C, 0x006C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x021C, 0x006C, 1, 0x045C, 0, 0), + MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x021C, 0x006C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x021C, 0x006C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x021C, 0x006C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x021C, 0x006C, 6 | IOMUX_CONFIG_SION, 0x03E8, 1, 0), + MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x021C, 0x006C, 7, 0x03BC, 0, 0), + + MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x0220, 0x0070, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x0220, 0x0070, 1, 0x0460, 0, 0), + MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x0220, 0x0070, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x0220, 0x0070, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x0220, 0x0070, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x0220, 0x0070, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x0220, 0x0070, 7, 0x03C0, 0, 0), + + MX93_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x0224, 0x0074, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x0224, 0x0074, 1, 0x0464, 0, 0), + MX93_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x0224, 0x0074, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x0224, 0x0074, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x0224, 0x0074, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x0224, 0x0074, 5, 0x03D4, 1, 0), + MX93_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x0224, 0x0074, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x0224, 0x0074, 7, 0x03C4, 0, 0), + + MX93_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x0228, 0x0078, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x0228, 0x0078, 1, 0x0468, 0, 0), + MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 = IOMUX_PAD(0x0228, 0x0078, 2, 0x043C, 1, 0), + MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x0228, 0x0078, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x0228, 0x0078, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x0228, 0x0078, 5, 0x03D8, 1, 0), + MX93_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x0228, 0x0078, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x0228, 0x0078, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x022C, 0x007C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x022C, 0x007C, 1, 0x046C, 0, 0), + MX93_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x022C, 0x007C, 2, 0x0364, 1, 0), + MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x022C, 0x007C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x022C, 0x007C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x022C, 0x007C, 5, 0x03DC, 1, 0), + MX93_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x022C, 0x007C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x022C, 0x007C, 7, 0x03C8, 0, 0), + + MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x0230, 0x0080, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x0230, 0x0080, 1 | IOMUX_CONFIG_SION, 0x03E4, 1, 0), + MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x0230, 0x0080, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x0234, 0x0084, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x0234, 0x0084, 1 | IOMUX_CONFIG_SION, 0x03E0, 1, 0), + MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x0234, 0x0084, 7, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0238, 0x0088, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x0238, 0x0088, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x0238, 0x0088, 5, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x023C, 0x008C, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x023C, 0x008C, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x023C, 0x008C, 4, 0x03C8, 1, 0), + + MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x0240, 0x0090, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x0240, 0x0090, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x0240, 0x0090, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x0244, 0x0094, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x0244, 0x0094, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x0244, 0x0094, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDC__ENET_QOS_MDC = IOMUX_PAD(0x0248, 0x0098, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x0248, 0x0098, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x0248, 0x0098, 2 | IOMUX_CONFIG_SION, 0x03CC, 0, 0), + MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x0248, 0x0098, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 = IOMUX_PAD(0x0248, 0x0098, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__GPIO4_IO00 = IOMUX_PAD(0x0248, 0x0098, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x024C, 0x009C, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x024C, 0x009C, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x024C, 0x009C, 2 | IOMUX_CONFIG_SION, 0x03D0, 0, 0), + MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x024C, 0x009C, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 = IOMUX_PAD(0x024C, 0x009C, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__GPIO4_IO01 = IOMUX_PAD(0x024C, 0x009C, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x0250, 0x00A0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 = IOMUX_PAD(0x0250, 0x00A0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__GPIO4_IO02 = IOMUX_PAD(0x0250, 0x00A0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x0254, 0x00A4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x0254, 0x00A4, 2, 0x0364, 2, 0), + MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x0254, 0x00A4, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 = IOMUX_PAD(0x0254, 0x00A4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__GPIO4_IO03 = IOMUX_PAD(0x0254, 0x00A4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x0258, 0x00A8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x0258, 0x00A8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x0258, 0x00A8, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x0258, 0x00A8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 = IOMUX_PAD(0x0258, 0x00A8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__GPIO4_IO04 = IOMUX_PAD(0x0258, 0x00A8, 5, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x0258, 0x00A8, 6, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x025C, 0x00AC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x025C, 0x00AC, 1, 0x041C, 1, 0), + MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 = IOMUX_PAD(0x025C, 0x00AC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__GPIO4_IO05 = IOMUX_PAD(0x025C, 0x00AC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x0260, 0x00B0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x0260, 0x00B0, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 = IOMUX_PAD(0x0260, 0x00B0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 = IOMUX_PAD(0x0260, 0x00B0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x0264, 0x00B4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x0264, 0x00B4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 = IOMUX_PAD(0x0264, 0x00B4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__GPIO4_IO07 = IOMUX_PAD(0x0264, 0x00B4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x0268, 0x00B8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x0268, 0x00B8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x0268, 0x00B8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 = IOMUX_PAD(0x0268, 0x00B8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 = IOMUX_PAD(0x0268, 0x00B8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x026C, 0x00BC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x026C, 0x00BC, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 = IOMUX_PAD(0x026C, 0x00BC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__GPIO4_IO09 = IOMUX_PAD(0x026C, 0x00BC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x0270, 0x00C0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x0270, 0x00C0, 1, 0x0418, 1, 0), + MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x0270, 0x00C0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x0270, 0x00C0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x0274, 0x00C4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x0274, 0x00C4, 1, 0x0414, 1, 0), + MX93_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x0274, 0x00C4, 3, 0x0408, 0, 0), + MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x0274, 0x00C4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x0274, 0x00C4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x0278, 0x00C8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x0278, 0x00C8, 3, 0x040C, 0, 0), + MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x0278, 0x00C8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x0278, 0x00C8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x027C, 0x00CC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x027C, 0x00CC, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x027C, 0x00CC, 3, 0x0410, 0, 0), + MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x027C, 0x00CC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x027C, 0x00CC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDC__ENET1_MDC = IOMUX_PAD(0x0280, 0x00D0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x0280, 0x00D0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x0280, 0x00D0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x0280, 0x00D0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x0280, 0x00D0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDIO__ENET1_MDIO = IOMUX_PAD(0x0284, 0x00D4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x0284, 0x00D4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x0284, 0x00D4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x0284, 0x00D4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x0284, 0x00D4, 5, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 = IOMUX_PAD(0x0288, 0x00D8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x0288, 0x00D8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x0288, 0x00D8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x0288, 0x00D8, 0, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x028C, 0x00DC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__ENET1_TX_CLK = IOMUX_PAD(0x028C, 0x00DC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 = IOMUX_PAD(0x028C, 0x00DC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x028C, 0x00DC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x028C, 0x00DC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x0290, 0x00E0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x0290, 0x00E0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 = IOMUX_PAD(0x0290, 0x00E0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x0290, 0x00E0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x0290, 0x00E0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x0294, 0x00E4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x0294, 0x00E4, 1, 0x0428, 1, 0), + MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 = IOMUX_PAD(0x0294, 0x00E4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x0294, 0x00E4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x0294, 0x00E4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0298, 0x00E8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x0298, 0x00E8, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x0298, 0x00E8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x0298, 0x00E8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x0298, 0x00E8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x029C, 0x00EC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__ENET1_TX_ER = IOMUX_PAD(0x029C, 0x00EC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x029C, 0x00EC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x029C, 0x00EC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x029C, 0x00EC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02A0, 0x00F0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x02A0, 0x00F0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 = IOMUX_PAD(0x02A0, 0x00F0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x02A0, 0x00F0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x02A0, 0x00F0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x02A4, 0x00F4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__ENET1_RX_ER = IOMUX_PAD(0x02A4, 0x00F4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 = IOMUX_PAD(0x02A4, 0x00F4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x02A4, 0x00F4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x02A4, 0x00F4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x02A8, 0x00F8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x02A8, 0x00F8, 1, 0x0424, 1, 0), + MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 = IOMUX_PAD(0x02A8, 0x00F8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x02A8, 0x00F8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x02A8, 0x00F8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x02AC, 0x00FC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x02AC, 0x00FC, 1, 0x0454, 1, 0), + MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 = IOMUX_PAD(0x02AC, 0x00FC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x02AC, 0x00FC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x02AC, 0x00FC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x02B0, 0x0100, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x02B0, 0x0100, 1, 0x0420, 1, 0), + MX93_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x02B0, 0x0100, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x02B0, 0x0100, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x02B0, 0x0100, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x02B0, 0x0100, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x02B4, 0x0104, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x02B4, 0x0104, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x02B4, 0x0104, 2, 0x0454, 2, 0), + MX93_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x02B4, 0x0104, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x02B4, 0x0104, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x02B4, 0x0104, 5, 0x0000, 0, 0), + MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x02B8, 0x0108, 4, 0x038C, 1, 0), + MX93_PAD_SD1_CLK__GPIO3_IO08 = IOMUX_PAD(0x02B8, 0x0108, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02B8, 0x0108, 0, 0x0000, 0, 0), + + MX93_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02BC, 0x010C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x02BC, 0x010C, 4, 0x0390, 1, 0), + MX93_PAD_SD1_CMD__GPIO3_IO09 = IOMUX_PAD(0x02BC, 0x010C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02C0, 0x0110, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x02C0, 0x0110, 4, 0x0394, 1, 0), + MX93_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x02C0, 0x0110, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02C4, 0x0114, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x02C4, 0x0114, 4, 0x0398, 1, 0), + MX93_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x02C4, 0x0114, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02C4, 0x0114, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02C8, 0x0118, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x02C8, 0x0118, 4, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x02C8, 0x0118, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02C8, 0x0118, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x02CC, 0x011C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x02CC, 0x011C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x02CC, 0x011C, 4, 0x039C, 1, 0), + MX93_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x02CC, 0x011C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 = IOMUX_PAD(0x02D0, 0x0120, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x02D0, 0x0120, 4, 0x03A0, 1, 0), + MX93_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x02D0, 0x0120, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 = IOMUX_PAD(0x02D4, 0x0124, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x02D4, 0x0124, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x02D4, 0x0124, 4, 0x03A4, 1, 0), + MX93_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x02D4, 0x0124, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 = IOMUX_PAD(0x02D8, 0x0128, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x02D8, 0x0128, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x02D8, 0x0128, 4, 0x03A8, 1, 0), + MX93_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x02D8, 0x0128, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 = IOMUX_PAD(0x02DC, 0x012C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x02DC, 0x012C, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x02DC, 0x012C, 4, 0x03AC, 1, 0), + MX93_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x02DC, 0x012C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x02E0, 0x0130, 0, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x02E0, 0x0130, 1, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x02E0, 0x0130, 4, 0x03B0, 1, 0), + MX93_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x02E0, 0x0130, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x02E4, 0x0134, 0, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x02E4, 0x0134, 1, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x02E4, 0x0134, 2, 0x0410, 1, 0), + MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x02E4, 0x0134, 4, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x02E4, 0x0134, 5, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x02E4, 0x0134, 6, 0x0368, 0, 0), + + MX93_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x02E8, 0x0138, 0, 0x0458, 1, 0), + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x02E8, 0x0138, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x02E8, 0x0138, 4, 0x03B4, 1, 0), + MX93_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x02E8, 0x0138, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x02EC, 0x013C, 0, 0x045C, 1, 0), + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x02EC, 0x013C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x02EC, 0x013C, 4, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x02EC, 0x013C, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0, 0x0460, 1, 0), + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 = IOMUX_PAD(0x02F0, 0x0140, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x02F0, 0x0140, 4, 0x03B8, 1, 0), + MX93_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x02F0, 0x0140, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0, 0x0464, 1, 0), + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 = IOMUX_PAD(0x02F4, 0x0144, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x02F4, 0x0144, 4, 0x03BC, 1, 0), + MX93_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x02F4, 0x0144, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0, 0x0468, 1, 0), + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 = IOMUX_PAD(0x02F8, 0x0148, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x02F8, 0x0148, 4, 0x03C0, 1, 0), + MX93_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x02F8, 0x0148, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0, 0x046C, 1, 0), + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 = IOMUX_PAD(0x02FC, 0x014C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x02FC, 0x014C, 4, 0x03C4, 1, 0), + MX93_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x02FC, 0x014C, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0300, 0x0150, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0300, 0x0150, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x0300, 0x0150, 2 | IOMUX_CONFIG_SION, 0x03CC, 1, 0), + MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x0300, 0x0150, 4, 0x036C, 1, 0), + MX93_PAD_SD2_CD_B__GPIO3_IO00 = IOMUX_PAD(0x0300, 0x0150, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0304, 0x0154, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0304, 0x0154, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x0304, 0x0154, 2 | IOMUX_CONFIG_SION, 0x03D0, 1, 0), + MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x0304, 0x0154, 4, 0x0370, 1, 0), + MX93_PAD_SD2_CLK__GPIO3_IO01 = IOMUX_PAD(0x0304, 0x0154, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0304, 0x0154, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0308, 0x0158, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x0308, 0x0158, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x0308, 0x0158, 2, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x0308, 0x0158, 3, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x0308, 0x0158, 4, 0x0374, 1, 0), + MX93_PAD_SD2_CMD__GPIO3_IO02 = IOMUX_PAD(0x0308, 0x0158, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0308, 0x0158, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x030C, 0x015C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x030C, 0x015C, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x030C, 0x015C, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x030C, 0x015C, 4, 0x0378, 1, 0), + MX93_PAD_SD2_DATA0__GPIO3_IO03 = IOMUX_PAD(0x030C, 0x015C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x030C, 0x015C, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0310, 0x0160, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0310, 0x0160, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x0310, 0x0160, 2, 0x0364, 3, 0), + MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x0310, 0x0160, 4, 0x037C, 1, 0), + MX93_PAD_SD2_DATA1__GPIO3_IO04 = IOMUX_PAD(0x0310, 0x0160, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0310, 0x0160, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0314, 0x0164, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0314, 0x0164, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x0314, 0x0164, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x0314, 0x0164, 4, 0x0380, 1, 0), + MX93_PAD_SD2_DATA2__GPIO3_IO05 = IOMUX_PAD(0x0314, 0x0164, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0314, 0x0164, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0318, 0x0168, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x0318, 0x0168, 1, 0x0408, 1, 0), + MX93_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x0318, 0x0168, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x0318, 0x0168, 4, 0x0384, 1, 0), + MX93_PAD_SD2_DATA3__GPIO3_IO06 = IOMUX_PAD(0x0318, 0x0168, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0318, 0x0168, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x031C, 0x016C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x031C, 0x016C, 1, 0x040C, 1, 0), + MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x031C, 0x016C, 4, 0x0388, 1, 0), + MX93_PAD_SD2_RESET_B__GPIO3_IO07 = IOMUX_PAD(0x031C, 0x016C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x031C, 0x016C, 6, 0x0000, 0, 0), + + MX93_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x0320, 0x0170, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x0320, 0x0170, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x0320, 0x0170, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__GPIO1_IO00 = IOMUX_PAD(0x0320, 0x0170, 5, 0x0000, 0, 0), + + MX93_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x0324, 0x0174, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x0324, 0x0174, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x0324, 0x0174, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__GPIO1_IO01 = IOMUX_PAD(0x0324, 0x0174, 5, 0x0000, 0, 0), + + MX93_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x0328, 0x0178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x0328, 0x0178, 1, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__GPIO1_IO02 = IOMUX_PAD(0x0328, 0x0178, 5, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 6, 0x0000, 0, 0), + + MX93_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x032C, 0x017C, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x032C, 0x017C, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x032C, 0x017C, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__GPIO1_IO03 = IOMUX_PAD(0x032C, 0x017C, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x0330, 0x0180, 0, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__S400_UART_RX = IOMUX_PAD(0x0330, 0x0180, 1, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x0330, 0x0180, 2, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x0330, 0x0180, 3, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__GPIO1_IO04 = IOMUX_PAD(0x0330, 0x0180, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x0334, 0x0184, 0, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__S400_UART_TX = IOMUX_PAD(0x0334, 0x0184, 1, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x0334, 0x0184, 2, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x0334, 0x0184, 3, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__GPIO1_IO05 = IOMUX_PAD(0x0334, 0x0184, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x0338, 0x0188, 0, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x0338, 0x0188, 1, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x0338, 0x0188, 2, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x0338, 0x0188, 3, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x0338, 0x0188, 4, 0x0448, 0, 0), + MX93_PAD_UART2_RXD__GPIO1_IO06 = IOMUX_PAD(0x0338, 0x0188, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x033C, 0x018C, 0, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x033C, 0x018C, 1, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x033C, 0x018C, 2, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x033C, 0x018C, 3, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__GPIO1_IO07 = IOMUX_PAD(0x033C, 0x018C, 5, 0x0000, 0, 0), + + MX93_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x0340, 0x0190, 0, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x0340, 0x0190, 1, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x0340, 0x0190, 4, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__GPIO1_IO08 = IOMUX_PAD(0x0340, 0x0190, 5, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x0340, 0x0190, 6, 0x0000, 0, 0), + + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 = IOMUX_PAD(0x0344, 0x0194, 0, 0x0438, 2, 0), + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x0344, 0x0194, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x0344, 0x0194, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x0344, 0x0194, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x0344, 0x0194, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 = IOMUX_PAD(0x0344, 0x0194, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x0344, 0x0194, 6, 0x0360, 0, 0), + + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 = IOMUX_PAD(0x0348, 0x0198, 0, 0x043C, 2, 0), + MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI = IOMUX_PAD(0x0348, 0x0198, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x0348, 0x0198, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x0348, 0x0198, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x0348, 0x0198, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x0348, 0x0198, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0348, 0x0198, 6, 0x0368, 1, 0), + + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x034C, 0x019C, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 = IOMUX_PAD(0x034C, 0x019C, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x034C, 0x019C, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x034C, 0x019C, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x034C, 0x019C, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x034C, 0x019C, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x0350, 0x01A0, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x0350, 0x01A0, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x0350, 0x01A0, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x0350, 0x01A0, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x0350, 0x01A0, 4, 0x0360, 1, 0), + MX93_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x0350, 0x01A0, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 = IOMUX_PAD(0x0354, 0x01A4, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x0354, 0x01A4, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x0354, 0x01A4, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x0354, 0x01A4, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x0354, 0x01A4, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x0354, 0x01A4, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 = IOMUX_PAD(0x0358, 0x01A8, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x0358, 0x01A8, 1, 0x0448, 1, 0), + MX93_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x0358, 0x01A8, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x0358, 0x01A8, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x0358, 0x01A8, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x0358, 0x01A8, 5, 0x0000, 0, 0), + + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x01AC, 0, 0x0000, 0, 0), + MX93_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x035C, 0x01AC, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX93_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h new file mode 100644 index 0000000000..292635982f --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 NXP + */ + +#ifndef __ARCH_IMX9_SYS_PROTO_H +#define __ARCH_NMX9_SYS_PROTO_H + +#include <asm/mach-imx/sys_proto.h> + +ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf); +ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); +extern unsigned long rom_pointer[]; +enum boot_device get_boot_device(void); +bool is_usb_boot(void); +int mix_power_init(enum mix_power_domain pd); +void soc_power_init(void); +bool m33_is_rom_kicked(void); +int m33_prepare(void); +#endif diff --git a/arch/arm/include/asm/arch-imx9/trdc.h b/arch/arm/include/asm/arch-imx9/trdc.h new file mode 100644 index 0000000000..7c984d9ce9 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/trdc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_TRDC_H +#define __ASM_ARCH_IMX9_TRDC_H + +int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, + u32 glbac_id, u32 glbac_val); +int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, + u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id); +int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, + u32 glbac_id, u32 glbac_val); +int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, + u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id); + +void trdc_early_init(void); +void trdc_init(void); + +#endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 085e12b5d4..8d25c32c3a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -90,10 +90,16 @@ struct arch_global_data { struct udevice *scu_dev; #endif -#ifdef CONFIG_ARCH_IMX8ULP +#ifdef CONFIG_IMX_SENTINEL struct udevice *s400_dev; + u32 soc_rev; + u32 lifecycle; + u32 uid[4]; #endif +#ifdef CONFIG_ARCH_IMX8ULP + bool m33_handshake_done; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index dcf9bd8966..cd2c6e73e0 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_IMX8M +#ifdef CONFIG_IMX93 +#define PAD_CTL_FSEL2 (0x2 << 7) +#define PAD_CTL_FSEL3 (0x3 << 7) +#define PAD_CTL_PUE (0x1 << 9) +#define PAD_CTL_PDE (0x1 << 10) +#define PAD_CTL_ODE (0x1 << 11) +#define PAD_CTL_HYS (0x1 << 12) +#define PAD_CTL_DSE(x) (((x) << 1) & 0x7f) + +#elif defined(CONFIG_IMX8M) #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h index 10d966d5d4..5db559c1ac 100644 --- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h +++ b/arch/arm/include/asm/mach-imx/mu_hal.h @@ -3,8 +3,8 @@ * Copyright 2021 NXP */ -#ifndef __IMX8ULP_MU_HAL_H__ -#define __IMX8ULP_MU_HAL_H__ +#ifndef __SNT_MU_HAL_H__ +#define __SNT_MU_HAL_H__ void mu_hal_init(ulong base); int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg); diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h new file mode 100644 index 0000000000..3862c5a39b --- /dev/null +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __S400_API_H__ +#define __S400_API_H__ + +#define AHAB_VERSION 0x6 +#define AHAB_CMD_TAG 0x17 +#define AHAB_RESP_TAG 0xe1 + +/* ELE commands */ +#define ELE_PING_REQ (0x01) +#define ELE_FW_AUTH_REQ (0x02) +#define ELE_RESTART_RST_TIMER_REQ (0x04) +#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21) +#define ELE_OEM_CNTN_AUTH_REQ (0x87) +#define ELE_VERIFY_IMAGE_REQ (0x88) +#define ELE_RELEASE_CONTAINER_REQ (0x89) +#define ELE_WRITE_SECURE_FUSE_REQ (0x91) +#define ELE_FWD_LIFECYCLE_UP_REQ (0x95) +#define ELE_READ_FUSE_REQ (0x97) +#define ELE_GET_FW_VERSION_REQ (0x9D) +#define ELE_RET_LIFECYCLE_UP_REQ (0xA0) +#define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_START_RNG (0xA3) +#define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_ENABLE_PATCH_REQ (0xC3) +#define ELE_RELEASE_RDC_REQ (0xC4) +#define ELE_GET_FW_STATUS_REQ (0xC5) +#define ELE_ENABLE_OTFAD_REQ (0xC6) +#define ELE_RESET_REQ (0xC7) +#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0) +#define ELE_POWER_DOWN_REQ (0xD1) +#define ELE_ENABLE_APC_REQ (0xD2) +#define ELE_ENABLE_RTC_REQ (0xD3) +#define ELE_DEEP_POWER_DOWN_REQ (0xD4) +#define ELE_STOP_RST_TIMER_REQ (0xD5) +#define ELE_WRITE_FUSE_REQ (0xD6) +#define ELE_RELEASE_CAAM_REQ (0xD7) +#define ELE_RESET_A35_CTX_REQ (0xD8) +#define ELE_MOVE_TO_UNSECURED_REQ (0xD9) +#define ELE_GET_INFO_REQ (0xDA) +#define ELE_ATTEST_REQ (0xDB) +#define ELE_RELEASE_PATCH_REQ (0xDC) +#define ELE_OTP_SEQ_SWITH_REQ (0xDD) + +/* ELE failure indications */ +#define ELE_ROM_PING_FAILURE_IND (0x0A) +#define ELE_FW_PING_FAILURE_IND (0x1A) +#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0) +#define ELE_BAD_HASH_FAILURE_IND (0xF1) +#define ELE_INVALID_LIFECYCLE_IND (0xF2) +#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3) +#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4) +#define ELE_BAD_VALUE_FAILURE_IND (0xF5) +#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6) +#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7) +#define ELE_BAD_VERSION_FAILURE_IND (0xF8) +#define ELE_INVALID_KEY_FAILURE_IND (0xF9) +#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA) +#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB) +#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC) +#define ELE_BAD_UID_FAILURE_IND (0xFD) +#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE) +#define ELE_MUST_SIGNED_FAILURE_IND (0xE0) +#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE) +#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF) +#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6) +#define ELE_WRONG_SIZE_FAILURE_IND (0xA7) +#define ELE_ENCRYPTION_FAILURE_IND (0xA8) +#define ELE_DECRYPTION_FAILURE_IND (0xA9) +#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA) +#define ELE_OTP_LOCKED_FAILURE_IND (0xAB) +#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD) +#define ELE_TIME_OUT_FAILURE_IND (0xB0) +#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1) +#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4) +#define ELE_DMA_FAILURE_IND (0xB5) +#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6) +#define ELE_MUST_ATTEST_FAILURE_IND (0xB7) +#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8) +#define ELE_CRC_ERROR_IND (0xB9) +#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB) +#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC) +#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD) +#define ELE_LOCKED_REG_FAILURE_IND (0xBE) +#define ELE_BAD_ID_FAILURE_IND (0xBF) +#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0) +#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1) +#define ELE_MSG_TRUNCATED_IND (0xC2) +#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3) +#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4) +#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5) +#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6) +#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0) +#define ELE_OUT_OF_MEMORY_IND (0xD1) +#define ELE_CSTM_FAILURE_IND (0xCF) +#define ELE_OLD_VERSION_FAILURE_IND (0xCE) +#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD) +#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB) +#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC) +#define ELE_ABORT_IND (0xFF) + +/* ELE IPC identifier */ +#define ELE_IPC_MU_RTD (0x1) +#define ELE_IPC_MU_APD (0x2) + +/* ELE Status*/ +#define ELE_SUCCESS_IND (0xD6) +#define ELE_FAILURE_IND (0x29) + +#define S400_MAX_MSG 255U + +struct sentinel_msg { + u8 version; + u8 size; + u8 command; + u8 tag; + u32 data[(S400_MAX_MSG - 1U)]; +}; + +struct sentinel_get_info_data{ + u32 hdr; + u32 soc; + u32 lc; + u32 uid[4]; + u32 sha256_rom_patch[8]; + u32 sha_fw[8]; +}; + +int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response); +int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); +int ahab_release_container(u32 *response); +int ahab_verify_image(u32 img_id, u32 *response); +int ahab_forward_lifecycle(u16 life_cycle, u32 *response); +int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); +int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); +int ahab_release_caam(u32 core_did, u32 *response); +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); +int ahab_dump_buffer(u32 *buffer, u32 buffer_length); +int ahab_get_info(struct sentinel_get_info_data *info, u32 *response); +int ahab_get_fw_status(u32 *status, u32 *response); +int ahab_release_m33_trout(void); +int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ahab_start_rng(void); +int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, + u32 max_output_size); +int ahab_write_secure_fuse(ulong signed_msg_blk, u32 *response); + +#endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 593a1cf404..04505d948c 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -32,6 +32,7 @@ struct bd_info; #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imx9() (is_soc_type(MXC_SOC_IMX9)) #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) @@ -83,6 +84,17 @@ struct bd_info; #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL)) +#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ + is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || is_cpu_type(MXC_CPU_IMX9322) || \ + is_cpu_type(MXC_CPU_IMX9321) || is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311)) +#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) +#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) +#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) +#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) +#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) +#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) +#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311)) + #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) @@ -151,7 +163,7 @@ struct rproc_att { u32 size; /* size of reg range */ }; -#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) +#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX9) struct rom_api { u16 ver; u16 tag; @@ -172,6 +184,13 @@ enum boot_dev_type_e { BT_DEV_TYPE_INVALID = 0xFF }; +enum boot_stage_type { + BT_STAGE_PRIMARY = 0x6, + BT_STAGE_SECONDARY = 0x9, + BT_STAGE_RECOVERY = 0xa, + BT_STAGE_USB = 0x5, +}; + #define QUERY_ROM_VER 1 #define QUERY_BT_DEV 2 #define QUERY_PAGE_SZ 3 diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ec0171e0e6..4e982892f8 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -3,6 +3,7 @@ * include/asm-arm/macro.h * * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * Copyright 2022 NXP */ #ifndef __ASM_ARM_MACRO_H__ @@ -356,6 +357,45 @@ lr .req x30 .endm #endif +/* + * Select code when configured for LE. + */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define CPU_LE(code...) +#else +#define CPU_LE(code...) code +#endif + +/* + * Pseudo-ops for PC-relative adr/ldr <reg>, <symbol> where + * <symbol> is within the range +/- 4 GB of the PC. + */ + /* + * @dst: destination register (64 bit wide) + * @sym: name of the symbol + */ + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + /* + * @dst: destination register (32 or 64 bit wide) + * @sym: name of the symbol + * @tmp: optional 64-bit scratch register to be used if <dst> is a + * 32-bit wide register, in which case it cannot be used to hold + * the address + */ + .macro ldr_l, dst, sym, tmp= + .ifb \tmp + adrp \dst, \sym + ldr \dst, [\dst, :lo12:\sym] + .else + adrp \tmp, \sym + ldr \dst, [\tmp, :lo12:\sym] + .endif + .endm + #endif /* CONFIG_ARM64 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index fecc0b6107..3fe77a5e49 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -81,6 +81,14 @@ config IMX_HAB This option enables the support for secure boot (HAB). See doc/imx/habv4/* for more details. +config IMX_SPL_FIT_FDT_SIGNATURE + bool "Enable to verify signature of FIT FDT" + depends on IMX_HAB + depends on ARCH_IMX8M + help + Enable SPL to verify signature of FIT FDT during FIT loading. + This needs additional signing to FIT FDT part. + config CSF_SIZE hex "Maximum size for Command Sequence File (CSF) binary" depends on IMX_HAB @@ -109,6 +117,7 @@ config CMD_DEKBLOB select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M select IMX_SECO_DEK_ENCAP if ARCH_IMX8 + select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and @@ -137,6 +146,12 @@ config IMX_SECO_DEK_ENCAP This enabled the DEK blob encapsulation with the SECO API. This option is only available on imx8. +config IMX_ELE_DEK_ENCAP + bool "Support the DEK blob encapsulation with ELE" + help + This enabled the DEK blob encapsulation with the ELE API. This option + is only available on imx8ulp and imx9. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB @@ -229,7 +244,7 @@ config DDRMC_VF610_CALIBRATION config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" - depends on IMX8MN || IMX8MP || IMX8ULP + depends on IMX8MN || IMX8MP || IMX8ULP || IMX9 config IMX_DCD_ADDR hex "DCD Blocks location on the image" @@ -275,6 +290,7 @@ config ANDROID_SUPPORT select SUPPORT_RAW_INITRD select LIBAVB select AVB_SUPPORT + imply IMX_SPL_FIT_FDT_SIGNATURE config ANDROID_AUTO_SUPPORT bool "Android Automotive features support" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 6dc02efe2c..4ebf95d2b3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,7 +5,7 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610)) obj-y = iomux-v3.o endif @@ -30,12 +30,12 @@ endif obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp imx9)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif -ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp)) +ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp imx9)) obj-y += dt_optee.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) @@ -89,6 +89,10 @@ ifeq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o endif +ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9)) +obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o +endif + PLUGIN = board/$(BOARDDIR)/plugin ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y) @@ -292,6 +296,7 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/ obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ +obj-$(CONFIG_ARCH_IMX9) += imx9/ obj-$(CONFIG_ARCH_IMXRT) += imxrt/ obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 701bf516df..9e69f2c505 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * * Command for encapsulating DEK blob */ @@ -20,6 +21,11 @@ #include <asm/arch/sci/sci.h> #include <asm/mach-imx/image.h> #endif +#ifdef CONFIG_IMX_ELE_DEK_ENCAP +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/image.h> +#endif + #include <cpu_func.h> /** @@ -284,6 +290,84 @@ error: } #endif /* CONFIG_IMX_SECO_DEK_ENCAP */ +#ifdef CONFIG_IMX_ELE_DEK_ENCAP + +#define DEK_BLOB_HDR_SIZE 8 +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_DEK_BLOB 0x01 +#define AHAB_ALG_AES 0x03 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + u8 in_size, out_size; + u8 *src_ptr, *dst_ptr; + struct generate_key_blob_hdr hdr; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = 0x0; + hdr.length_lsb = in_size; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = 0x0; /* Not used by the ELE */ + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Move input key and append blob header */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache */ + flush_dcache_range(src_addr, src_addr + in_size); + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Call ELE */ + if (ahab_generate_dek_blob(0x00, src_addr, dst_addr, out_size)) + return -1; + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + return 0; +} +#endif /* CONFIG_IMX_ELE_DEK_ENCAP */ + /** * do_dek_blob() - Handle the "dek_blob" command-line command * @cmdtp: Command data struct pointer diff --git a/arch/arm/mach-imx/cmd_qspihdr.c b/arch/arm/mach-imx/cmd_qspihdr.c index 6e2758664f..ef4a3cf113 100644 --- a/arch/arm/mach-imx/cmd_qspihdr.c +++ b/arch/arm/mach-imx/cmd_qspihdr.c @@ -235,6 +235,7 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) unsigned long addr; char *endp; void *tmp; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF + QSPI_HDR_TAG_OFF; @@ -266,7 +267,11 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) return 1; } } else { - spi_flash_read(flash, off, 4, &buf); + ret = spi_flash_read(flash, off, 4, &buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } if (buf == tag) { if (flag & FLAG_VERBOSE) @@ -398,6 +403,7 @@ static int do_qspihdr_dump(int argc, char * const argv[]) char *endp; void *tmp; void *buf; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF; @@ -431,7 +437,11 @@ static int do_qspihdr_dump(int argc, char * const argv[]) return 0; } - spi_flash_read(flash, off, HDR_LEN, buf); + ret = spi_flash_read(flash, off, HDR_LEN, buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } hdr_dump(buf); free(buf); diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c new file mode 100644 index 0000000000..192f90e6b1 --- /dev/null +++ b/arch/arm/mach-imx/ele_ahab.c @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/arch-imx/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/image.h> +#include <console.h> +#include <cpu_func.h> +#include <asm/mach-imx/ahab.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) + +#define AHAB_MAX_EVENTS 8 + +static char *ele_ipc_str[] = { + "IPC = MU RTD (0x1)\n", + "IPC = MU APD (0x2)\n", + "IPC = INVALID\n", + NULL +}; + +static char *ele_status_str[] = { + "STA = ELE_SUCCESS_IND (0xD6)\n", + "STA = ELE_FAILURE_IND (0x29)\n", + "STA = INVALID\n", + NULL +}; + +static char *ele_cmd_str[] = { + "CMD = ELE_PING_REQ (0x01)\n", + "CMD = ELE_FW_AUTH_REQ (0x02)\n", + "CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n", + "CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n", + "CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n", + "CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n", + "CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n", + "CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n", + "CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n", + "CMD = ELE_READ_FUSE_REQ (0x97)\n", + "CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n", + "CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n", + "CMD = ELE_GET_EVENTS_REQ (0xA2)\n", + "CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n", + "CMD = ELE_RELEASE_RDC_REQ (0xC4)\n", + "CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n", + "CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n", + "CMD = ELE_RESET_REQ (0xC7)\n", + "CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n", + "CMD = ELE_POWER_DOWN_REQ (0xD1)\n", + "CMD = ELE_ENABLE_APC_REQ (0xD2)\n", + "CMD = ELE_ENABLE_RTC_REQ (0xD3)\n", + "CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n", + "CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n", + "CMD = ELE_WRITE_FUSE_REQ (0xD6)\n", + "CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n", + "CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n", + "CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n", + "CMD = ELE_GET_INFO_REQ (0xDA)\n", + "CMD = ELE_ATTEST_REQ (0xDB)\n", + "CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n", + "CMD = ELE_OTP_SEQ_SWITH_REQ (0xDD)\n", + "CMD = INVALID\n", + NULL +}; + +static char *ele_ind_str[] = { + "IND = ELE_ROM_PING_FAILURE_IND (0x0A)\n", + "IND = ELE_FW_PING_FAILURE_IND (0x1A)\n", + "IND = ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)\n", + "IND = ELE_BAD_HASH_FAILURE_IND (0xF1)\n", + "IND = ELE_INVALID_LIFECYCLE_IND (0xF2)\n", + "IND = ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)\n", + "IND = ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)\n", + "IND = ELE_BAD_VALUE_FAILURE_IND (0xF5)\n", + "IND = ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)\n", + "IND = ELE_BAD_CONTAINER_FAILURE_IND (0xF7)\n", + "IND = ELE_BAD_VERSION_FAILURE_IND (0xF8)\n", + "IND = ELE_INVALID_KEY_FAILURE_IND (0xF9)\n", + "IND = ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)\n", + "IND = ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)\n", + "IND = ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)\n", + "IND = ELE_BAD_UID_FAILURE_IND (0xFD)\n", + "IND = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)\n", + "IND = ELE_MUST_SIGNED_FAILURE_IND (0xE0)\n", + "IND = ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)\n", + "IND = ELE_BAD_SRK_SET_FAILURE_IND (0xEF)\n", + "IND = ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)\n", + "IND = ELE_WRONG_SIZE_FAILURE_IND (0xA7)\n", + "IND = ELE_ENCRYPTION_FAILURE_IND (0xA8)\n", + "IND = ELE_DECRYPTION_FAILURE_IND (0xA9)\n", + "IND = ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)\n", + "IND = ELE_OTP_LOCKED_FAILURE_IND (0xAB)\n", + "IND = ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)\n", + "IND = ELE_TIME_OUT_FAILURE_IND (0xB0)\n", + "IND = ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)\n", + "IND = ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)\n", + "IND = ELE_DMA_FAILURE_IND (0xB5)\n", + "IND = ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)\n", + "IND = ELE_MUST_ATTEST_FAILURE_IND (0xB7)\n", + "IND = ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)\n", + "IND = ELE_CRC_ERROR_IND (0xB9)\n", + "IND = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)\n", + "IND = ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)\n", + "IND = ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)\n", + "IND = ELE_LOCKED_REG_FAILURE_IND (0xBE)\n", + "IND = ELE_BAD_ID_FAILURE_IND (0xBF)\n", + "IND = ELE_INVALID_OPERATION_FAILURE_IND (0xC0)\n", + "IND = ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)\n", + "IND = ELE_MSG_TRUNCATED_IND (0xC2)\n", + "IND = ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)\n", + "IND = ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)\n", + "IND = ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)\n", + "IND = ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)\n", + "IND = ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)\n", + "IND = ELE_OUT_OF_MEMORY_IND (0xD1)\n", + "IND = ELE_CSTM_FAILURE_IND (0xCF)\n", + "IND = ELE_OLD_VERSION_FAILURE_IND (0xCE)\n", + "IND = ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)\n", + "IND = ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)\n", + "IND = ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)\n", + "IND = ELE_ABORT_IND (0xFF)\n", + "IND = INVALID\n", + NULL +}; + +static u8 ele_cmd[] = { + ELE_PING_REQ, + ELE_FW_AUTH_REQ, + ELE_RESTART_RST_TIMER_REQ, + ELE_DUMP_DEBUG_BUFFER_REQ, + ELE_OEM_CNTN_AUTH_REQ, + ELE_VERIFY_IMAGE_REQ, + ELE_RELEASE_CONTAINER_REQ, + ELE_WRITE_SECURE_FUSE_REQ, + ELE_FWD_LIFECYCLE_UP_REQ, + ELE_READ_FUSE_REQ, + ELE_GET_FW_VERSION_REQ, + ELE_RET_LIFECYCLE_UP_REQ, + ELE_GET_EVENTS_REQ, + ELE_ENABLE_PATCH_REQ, + ELE_RELEASE_RDC_REQ, + ELE_GET_FW_STATUS_REQ, + ELE_ENABLE_OTFAD_REQ, + ELE_RESET_REQ, + ELE_UPDATE_OTP_CLKDIV_REQ, + ELE_POWER_DOWN_REQ, + ELE_ENABLE_APC_REQ, + ELE_ENABLE_RTC_REQ, + ELE_DEEP_POWER_DOWN_REQ, + ELE_STOP_RST_TIMER_REQ, + ELE_WRITE_FUSE_REQ, + ELE_RELEASE_CAAM_REQ, + ELE_RESET_A35_CTX_REQ, + ELE_MOVE_TO_UNSECURED_REQ, + ELE_GET_INFO_REQ, + ELE_ATTEST_REQ, + ELE_RELEASE_PATCH_REQ, + ELE_OTP_SEQ_SWITH_REQ +}; + +static u8 ele_ind[] = { + ELE_ROM_PING_FAILURE_IND, + ELE_FW_PING_FAILURE_IND, + ELE_BAD_SIGNATURE_FAILURE_IND, + ELE_BAD_HASH_FAILURE_IND, + ELE_INVALID_LIFECYCLE_IND, + ELE_PERMISSION_DENIED_FAILURE_IND, + ELE_INVALID_MESSAGE_FAILURE_IND, + ELE_BAD_VALUE_FAILURE_IND, + ELE_BAD_FUSE_ID_FAILURE_IND, + ELE_BAD_CONTAINER_FAILURE_IND, + ELE_BAD_VERSION_FAILURE_IND, + ELE_INVALID_KEY_FAILURE_IND, + ELE_BAD_KEY_HASH_FAILURE_IND, + ELE_NO_VALID_CONTAINER_FAILURE_IND, + ELE_BAD_CERTIFICATE_FAILURE_IND, + ELE_BAD_UID_FAILURE_IND, + ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND, + ELE_MUST_SIGNED_FAILURE_IND, + ELE_NO_AUTHENTICATION_FAILURE_IND, + ELE_BAD_SRK_SET_FAILURE_IND, + ELE_UNALIGNED_PAYLOAD_FAILURE_IND, + ELE_WRONG_SIZE_FAILURE_IND, + ELE_ENCRYPTION_FAILURE_IND, + ELE_DECRYPTION_FAILURE_IND, + ELE_OTP_PROGFAIL_FAILURE_IND, + ELE_OTP_LOCKED_FAILURE_IND, + ELE_OTP_INVALID_IDX_FAILURE_IND, + ELE_TIME_OUT_FAILURE_IND, + ELE_BAD_PAYLOAD_FAILURE_IND, + ELE_WRONG_ADDRESS_FAILURE_IND, + ELE_DMA_FAILURE_IND, + ELE_DISABLED_FEATURE_FAILURE_IND, + ELE_MUST_ATTEST_FAILURE_IND, + ELE_RNG_NOT_STARTED_FAILURE_IND, + ELE_CRC_ERROR_IND, + ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND, + ELE_INCONSISTENT_PAR_FAILURE_IND, + ELE_RNG_INST_FAILURE_FAILURE_IND, + ELE_LOCKED_REG_FAILURE_IND, + ELE_BAD_ID_FAILURE_IND, + ELE_INVALID_OPERATION_FAILURE_IND, + ELE_NON_SECURE_STATE_FAILURE_IND, + ELE_MSG_TRUNCATED_IND, + ELE_BAD_IMAGE_NUM_FAILURE_IND, + ELE_BAD_IMAGE_ADDR_FAILURE_IND, + ELE_BAD_IMAGE_PARAM_FAILURE_IND, + ELE_BAD_IMAGE_TYPE_FAILURE_IND, + ELE_CORRUPTED_SRK_FAILURE_IND, + ELE_OUT_OF_MEMORY_IND, + ELE_CSTM_FAILURE_IND, + ELE_OLD_VERSION_FAILURE_IND, + ELE_WRONG_BOOT_MODE_FAILURE_IND, + ELE_APC_ALREADY_ENABLED_FAILURE_IND, + ELE_RTC_ALREADY_ENABLED_FAILURE_IND, + ELE_ABORT_IND +}; + +static u8 ele_ipc[] = { + ELE_IPC_MU_RTD, + ELE_IPC_MU_APD +}; + +static u8 ele_status[] = { + ELE_SUCCESS_IND, + ELE_FAILURE_IND +}; + +static inline u32 get_idx(u8 *list, u8 tgt, u32 size) +{ + u32 i; + + for (i = 0; i < size; i++) { + if (list[i] == tgt) + return i; + } + + return i; /* last str is invalid */ +} + +static void display_ahab_auth_ind(u32 event) +{ + u8 resp_ind = (event >> 8) & 0xff; + + printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]); +} + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + u32 resp; + memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + flush_dcache_range(IMG_CONTAINER_BASE, + IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); + + err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, + &resp); + if (err) { + printf("Authenticate container hdr failed, return %d, resp 0x%x\n", + err, resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_auth_release(void) +{ + int err; + u32 resp; + + err = ahab_release_container(&resp); + if (err) { + printf("Error: release container failed, resp 0x%x!\n", resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + int err; + u32 resp; + + err = ahab_verify_image(image_index, &resp); + if (err) { + printf("Authenticate img %d failed, return %d, resp 0x%x\n", + image_index, err, resp); + display_ahab_auth_ind(resp); + + return -EIO; + } + + return 0; +} + +static inline bool check_in_dram(ulong addr) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + if (addr >= bd->bi_dram[i].start && + addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + return true; + } + } + + return false; +} + +int authenticate_os_container(ulong addr) +{ + struct container_hdr *phdr; + int i, ret = 0; + int err; + u16 length; + struct boot_img_t *img; + unsigned long s, e; + + if (addr % 4) { + puts("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_dram(addr)) { + puts("Error: Image's address is invalid\n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 || phdr->version != 0x0) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + + err = ahab_auth_cntr_hdr(phdr, length); + if (err) { + ret = -EIO; + goto exit; + } + + debug("Verify images\n"); + + /* Copy images to dest address */ + for (i = 0; i < phdr->num_images; i++) { + img = (struct boot_img_t *)(addr + + sizeof(struct container_hdr) + + i * sizeof(struct boot_img_t)); + + debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", + i, (uint32_t) img->dst, img->offset + addr, img->size); + + memcpy((void *)img->dst, (const void *)(img->offset + addr), + img->size); + + s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; + + flush_dcache_range(s, e); + + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; + } + +exit: + debug("ahab_auth_release, 0x%x\n", ret); + ahab_auth_release(); + + return ret; +} + +static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + printf("Authenticate OS container at 0x%lx\n", addr); + + if (authenticate_os_container(addr)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB\n\n"); + break; + case 0x4: + printf("NXP Provisioned\n\n"); + break; + case 0x8: + printf("OEM Open\n\n"); + break; + case 0x20: + printf("OEM closed\n\n"); + break; + case 0x40: + printf("Field Return OEM\n\n"); + break; + case 0x80: + printf("Field Return NXP\n\n"); + break; + case 0x100: + printf("OEM Locked\n\n"); + break; + case 0x200: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} + +static int confirm_close(void) +{ + puts("Warning: Please ensure your sample is in NXP closed state, " + "OEM SRK hash has been fused, \n" + " and you are able to boot a signed image successfully " + "without any SECO events reported.\n" + " If not, your sample will be unrecoverable.\n" + "\nReally perform this operation? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Ahab close aborted\n"); + return 0; +} + +static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err; + u32 resp; + u32 lc; + + if (!confirm_close()) + return -EACCES; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3ff; + + if (lc != 0x8) { + puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n"); + display_life_cycle(lc); + return -EPERM; + } + + err = ahab_forward_lifecycle(8, &resp); + if (err != 0) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + printf("Change to OEM closed successfully\n"); + + return 0; +} + +int ahab_dump(void) +{ + u32 buffer[32]; + int ret, i = 0; + + do { + ret = ahab_dump_buffer(buffer, 32); + if (ret < 0) { + printf("Error in dump AHAB log\n"); + return -EIO; + } + + if (ret == 1) { + break; + } else { + for (i = 0; i < ret; i++) + printf("0x%x\n", buffer[i]); + } + } while (ret >= 21); + + return 0; +} + +static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return ahab_dump(); +} + +static void display_event(u32 event) +{ + printf("\n\t0x%08x\n", event); + printf("\t%s", ele_ipc_str[get_idx(ele_ipc, + (event >> 24) & 0xFF, ARRAY_SIZE(ele_ipc))]); + printf("\t%s", ele_cmd_str[get_idx(ele_cmd, + (event >> 16) & 0xFF, ARRAY_SIZE(ele_cmd))]); + printf("\t%s", ele_ind_str[get_idx(ele_ind, + (event >> 8) & 0xFF, ARRAY_SIZE(ele_ind))]); + printf("\t%s", ele_status_str[get_idx(ele_status, + event & 0xFF, ARRAY_SIZE(ele_status))]); +} + +static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 lc, i; + u32 events[AHAB_MAX_EVENTS]; + u32 cnt = AHAB_MAX_EVENTS; + int ret; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3ff; + + display_life_cycle(lc); + + ret = ahab_get_events(events, &cnt, NULL); + if (ret) { + printf("Get ELE EVENTS error %d\n", ret); + return CMD_RET_FAILURE; + } + + if (!cnt) { + puts("\n\tNo Events Found!\n"); + return 0; + } + + for (i = 0; i < cnt; i++) + display_event(events[i]); + + return 0; +} + +static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ahab_write_secure_fuse(addr, &response)) { + printf("Program secure fuse failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Program secure fuse completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + + +U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, + "autenticate OS container via AHAB", + "addr\n" + "addr - OS container hex address\n" +); + +U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, + "Change AHAB lifecycle to OEM closed", + "" +); + +U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, + "Dump AHAB log for debug", + "" +); + +U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, + "display AHAB lifecycle only", + "" +); + +U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog, + "Program secure fuse via signed message block", + "addr\n" + "addr - Signed message block for secure fuse\n" +); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index b857a48da1..367410b154 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -191,39 +191,41 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) unsigned long offset = 0, sec_set_off = 0; bool sec_boot = false; - sec_boot = check_secondary_cnt_set(&sec_set_off); - if (sec_boot) - printf("Secondary set selected\n"); - else - printf("Primary set selected\n"); - - if (dev_type == MMC_DEV) { - struct mmc *mmc = (struct mmc *)dev; + if (dev_type == ROM_API_DEV) { + offset = (unsigned long)dev; + } else { + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + printf("Secondary set selected\n"); + else + printf("Primary set selected\n"); - if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { - offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; - } else { - u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + if (dev_type == MMC_DEV) { + struct mmc *mmc = (struct mmc *)dev; - if (part == 1 || part == 2) { - if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) - offset = CONTAINER_HDR_MMCSD_OFFSET; - else - offset = CONTAINER_HDR_EMMC_OFFSET; - } else { + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; + } else { + u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == 1 || part == 2) { + if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) + offset = CONTAINER_HDR_MMCSD_OFFSET; + else + offset = CONTAINER_HDR_EMMC_OFFSET; + } else { + offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; + } } + } else if (dev_type == QSPI_DEV) { + offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET; + } else if (dev_type == NAND_DEV) { + offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET; + } else if (dev_type == QSPI_NOR_DEV) { + offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; + } else if (dev_type == RAM_DEV) { + offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET; } - } else if (dev_type == QSPI_DEV) { - offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET; - } else if (dev_type == NAND_DEV) { - offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET; - } else if (dev_type == QSPI_NOR_DEV) { - offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; - } else if (dev_type == ROM_API_DEV) { - offset = (unsigned long)dev; - } else if (dev_type == RAM_DEV) { - offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET; } debug("container set offset 0x%lx\n", offset); diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b2b8ade0bd..7abcfeca86 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -176,6 +176,7 @@ config TARGET_IMX8DXL_EVK bool "Support i.MX8DXL EVK board" select BOARD_LATE_INIT select IMX8DXL + select CRYPTO_SHA2_ARM64_CE select FSL_CAAM select FSL_BLOB select ARCH_MISC_INIT diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 3c3c4cdc4f..deb18a3bb2 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2022 NXP */ #include <common.h> @@ -16,6 +16,7 @@ #include <asm/mach-imx/image.h> #include <console.h> #include <cpu_func.h> +#include <crypto/sha2.h> #include <asm/mach-imx/ahab.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) #define SECO_PT 2U +#define AHAB_HASH_TYPE_MASK 0x00000700 +#define AHAB_HASH_TYPE_SHA256 0 int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { @@ -130,6 +133,9 @@ int authenticate_os_container(ulong addr) u16 length; struct boot_img_t *img; unsigned long s, e; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + u8 hash_value[SHA256_DIGEST_SIZE]; +#endif if (addr % 4) { puts("Error: Image's address is not 4 byte aligned\n"); @@ -179,9 +185,23 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) { + sha256_ce((void *)img->dst, img->size, hash_value); + err = memcmp(&img->hash, &hash_value, SHA256_DIGEST_SIZE); + if (err) { + printf("img %d hash comparison failed, error %d\n", i, err); + ret = -EIO; + goto exit; + } + } else { +#endif ret = ahab_verify_cntr_image(img, i); if (ret) goto exit; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + } +#endif } exit: diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 10fcada0cb..a94cd0df40 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -33,6 +33,10 @@ #include <asm/mach-imx/imx_vservice.h> #include <usb/ci_udc.h> +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + DECLARE_GLOBAL_DATA_PTR; #define BT_PASSOVER_TAG 0x504F diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 456073873d..a225a9784f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -120,6 +120,24 @@ config TARGET_IMX8MM_DDR4_EVK select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MM_AB2 + bool "imx8mm LPDDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MM_DDR4_AB2 + bool "imx8mm DDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" select IMX8MM @@ -179,6 +197,33 @@ config TARGET_IMX8MN_DDR3_EVK select FSL_BLOB select SPL_CRYPTO if SPL +config TARGET_IMX8MN_AB2 + bool "imx8mn LPDDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MN_DDR4_AB2 + bool "imx8mn DDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + +config TARGET_IMX8MN_DDR3L_AB2 + bool "imx8mn DDR3L Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR3L + select FSL_CAAM + select FSL_BLOB + select SPL_CRYPTO if SPL + config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" select BINMAN @@ -305,6 +350,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/engicam/imx8mm/Kconfig" source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mq_val/Kconfig" +source "board/freescale/imx8mm_ab2/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mm_val/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d6be307e6e..203c52d1d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -83,7 +83,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 74e0c1d199..c2f6acdde7 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -747,7 +747,7 @@ bool is_usb_boot(void) { return get_boot_device() == USB_BOOT; } -#ifdef CONFIG_SERIAL_TAG +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) void get_board_serial(struct tag_serialnr *serialnr) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -1761,6 +1761,16 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; switch (dev) { + case USB_BOOT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) + return ENVL_NAND; + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + return ENVL_UNKNOWN; case QSPI_BOOT: if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) return ENVL_SPI_FLASH; diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 1e465ab720..e82347ed68 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -40,12 +40,22 @@ config TARGET_IMX8ULP_9X9_EVK select IMX8ULP_DRAM select FSL_CAAM select FSL_BLOB - select MISC select ARCH_MISC_INIT select SPL_CRYPTO_SUPPORT if SPL +config TARGET_IMX8ULP_WATCH + bool "imx8ulp_watch" + select IMX8ULP + select SUPPORT_SPL + select IMX8ULP_DRAM + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL + endchoice source "board/freescale/imx8ulp_evk/Kconfig" +source "board/freescale/imx8ulp_watch/Kconfig" endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index f7692cf3a7..2c9938fcdf 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,7 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -obj-$(CONFIG_AHAB_BOOT) += ahab.o ifeq ($(CONFIG_SPL_BUILD),y) obj-y += upower/ diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c deleted file mode 100644 index 93957f74e0..0000000000 --- a/arch/arm/mach-imx/imx8ulp/ahab.c +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 NXP - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/s400_api.h> -#include <asm/mach-imx/sys_proto.h> -#include <asm/arch-imx/cpu.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-imx/image.h> -#include <console.h> -#include <cpu_func.h> -#include <asm/mach-imx/ahab.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define IMG_CONTAINER_BASE (0x22010000UL) -#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) - -#define AHAB_NO_AUTHENTICATION_IND 0xee -#define AHAB_BAD_KEY_HASH_IND 0xfa -#define AHAB_INVALID_KEY_IND 0xf9 -#define AHAB_BAD_SIGNATURE_IND 0xf0 -#define AHAB_BAD_HASH_IND 0xf1 - -static void display_ahab_auth_ind(u32 event) -{ - u8 resp_ind = (event >> 8) & 0xff; - - switch (resp_ind) { - case AHAB_NO_AUTHENTICATION_IND: - printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_KEY_HASH_IND: - printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_INVALID_KEY_IND: - printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_SIGNATURE_IND: - printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind); - break; - case AHAB_BAD_HASH_IND: - printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind); - break; - default: - printf("Unknown Indicator (0x%02X)\n\n", resp_ind); - break; - } -} - -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) -{ - int err; - u32 resp; - memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, - ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - - flush_dcache_range(IMG_CONTAINER_BASE, - IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); - - err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, - &resp); - if (err) { - printf("Authenticate container hdr failed, return %d, resp 0x%x\n", - err, resp); - display_ahab_auth_ind(resp); - } - - return err; -} - -int ahab_auth_release(void) -{ - int err; - u32 resp; - - err = ahab_release_container(&resp); - if (err) { - printf("Error: release container failed, resp 0x%x!\n", resp); - display_ahab_auth_ind(resp); - } - - return err; -} - -int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) -{ - int err; - u32 resp; - - err = ahab_verify_image(image_index, &resp); - if (err) { - printf("Authenticate img %d failed, return %d, resp 0x%x\n", - image_index, err, resp); - display_ahab_auth_ind(resp); - return -EIO; - } - - return 0; -} - -static inline bool check_in_dram(ulong addr) -{ - int i; - struct bd_info *bd = gd->bd; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) - return true; - } - } - - return false; -} - -int authenticate_os_container(ulong addr) -{ - struct container_hdr *phdr; - int i, ret = 0; - int err; - u16 length; - struct boot_img_t *img; - unsigned long s, e; - - if (addr % 4) { - puts("Error: Image's address is not 4 byte aligned\n"); - return -EINVAL; - } - - if (!check_in_dram(addr)) { - puts("Error: Image's address is invalid\n"); - return -EINVAL; - } - - phdr = (struct container_hdr *)addr; - if (phdr->tag != 0x87 || phdr->version != 0x0) { - printf("Error: Wrong container header\n"); - return -EFAULT; - } - - if (!phdr->num_images) { - printf("Error: Wrong container, no image found\n"); - return -EFAULT; - } - - length = phdr->length_lsb + (phdr->length_msb << 8); - - debug("container length %u\n", length); - - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { - ret = -EIO; - goto exit; - } - - debug("Verify images\n"); - - /* Copy images to dest address */ - for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + - sizeof(struct container_hdr) + - i * sizeof(struct boot_img_t)); - - debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", - i, (uint32_t) img->dst, img->offset + addr, img->size); - - memcpy((void *)img->dst, (const void *)(img->offset + addr), - img->size); - - s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); - e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; - - flush_dcache_range(s, e); - - ret = ahab_verify_cntr_image(img, i); - if (ret) - goto exit; - } - -exit: - debug("ahab_auth_release, 0x%x\n", ret); - ahab_auth_release(); - - return ret; -} - -static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - ulong addr; - - if (argc < 2) - return CMD_RET_USAGE; - - addr = simple_strtoul(argv[1], NULL, 16); - - printf("Authenticate OS container at 0x%lx\n", addr); - - if (authenticate_os_container(addr)) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -static void display_life_cycle(u32 lc) -{ - printf("Lifecycle: 0x%08X, ", lc); - switch (lc) { - case 0x1: - printf("BLANK\n\n"); - break; - case 0x2: - printf("FAB\n\n"); - break; - case 0x4: - printf("NXP Provisioned\n\n"); - break; - case 0x8: - printf("OEM Open\n\n"); - break; - case 0x10: - printf("OEM Secure World Closed\n\n"); - break; - case 0x20: - printf("OEM closed\n\n"); - break; - case 0x40: - printf("Field Return OEM\n\n"); - break; - case 0x80: - printf("Field Return NXP\n\n"); - break; - case 0x100: - printf("OEM Locked\n\n"); - break; - case 0x200: - printf("BRICKED\n\n"); - break; - default: - printf("Unknown\n\n"); - break; - } -} - -static int confirm_close(void) -{ - puts("Warning: Please ensure your sample is in NXP closed state, " - "OEM SRK hash has been fused, \n" - " and you are able to boot a signed image successfully " - "without any SECO events reported.\n" - " If not, your sample will be unrecoverable.\n" - "\nReally perform this operation? <y/N>\n"); - - if (confirm_yesno()) - return 1; - - puts("Ahab close aborted\n"); - return 0; -} - -static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - int err; - u32 resp; - - if (!confirm_close()) - return -EACCES; - - err = ahab_forward_lifecycle(8, &resp); - if (err != 0) { - printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; - } - - printf("Change to OEM closed successfully\n"); - - return 0; -} - -int ahab_dump(void) -{ - u32 buffer[32]; - int ret, i = 0; - - do { - ret = ahab_dump_buffer(buffer, 32); - if (ret < 0) { - printf("Error in dump AHAB log\n"); - return -EIO; - } - - if (ret == 1) { - break; - } else { - for (i = 0; i < ret; i++) - printf("0x%x\n", buffer[i]); - } - } while (ret >= 21); - - return 0; -} - -static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - return ahab_dump(); -} - -static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - u32 lc; - - lc = readl(FSB_BASE_ADDR + 0x41c); - lc &= 0x3ff; - - display_life_cycle(lc); - return 0; -} - -U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, - "autenticate OS container via AHAB", - "addr\n" - "addr - OS container hex address\n" -); - -U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, - "Change AHAB lifecycle to OEM closed", - "" -); - -U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, - "Dump AHAB log for debug", - "" -); - -U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, - "display AHAB lifecycle only", - "" -); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 3913b17051..b19268c822 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -136,39 +136,34 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7)); clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F); - - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */ - } else { - setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */ - } - + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); /* PFD1 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16); + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 16); /* PFD2 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24); - setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 24); /* PFD3 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x03010000); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */ + else + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x01000000); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */ clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); @@ -179,6 +174,17 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23)); clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31)); + /* NIC_AP: + * OD source PLL3 PFD0, 324M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21)); + } + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28)); /* nicclk select pll3 pfd0 */ while (!(readl(&cgc1_regs->nicclk) & BIT(27))) @@ -218,18 +224,9 @@ void cgc2_pll4_init(bool pll4_reset) /* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21); /* 99Mhz for NIC_LPAV */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); /* 198Mhz for NIC_LPAV */ - } else { - setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ - clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); - } - setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */ - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 16); /* 316.8Mhz */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396Mhz */ clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31)); @@ -241,9 +238,22 @@ void cgc2_pll4_init(bool pll4_reset) clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31)); clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); - while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) - ; + /* NIC_LPAV: + * OD source PLL4 PFD1, 316.8M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); + } + + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); + while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) + ; + } } void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd) diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index b4240c83a1..17dff404fb 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -183,37 +183,20 @@ void clock_init_late(void) */ cgc1_pll3_init(540672000); - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } else { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD3_DIV1); /* 389M for OD, 194M for LD/ND*/ + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND */ + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND*/ + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); /* enable MU0_MUB clock before access the register of MU0_MUB */ pcc_clock_enable(3, MU0_B_PCC3_SLOT, true); @@ -432,6 +415,8 @@ void reset_lcdclk(void) pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true); } +/* PLL4 PFD0 max frequency */ +#define PLL4_PFD0_MAX_RATE 600000 /*khz*/ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) { u8 pcd, best_pcd = 0; @@ -447,10 +432,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; + if (parent_rate > PLL4_PFD0_MAX_RATE) + continue; + parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index e2eca0633e..f5423ec7b9 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -8,8 +8,8 @@ #include <asm/types.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/mu_hal.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/mu_hal.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/rdc.h> #include <div64.h> @@ -184,14 +184,14 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; - struct imx8ulp_s400_msg msg; + struct sentinel_msg msg; int ret; u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ; msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ mu_hal_init(s_mu_base); @@ -276,6 +276,36 @@ void xrdc_init_mda(void) void xrdc_init_mrc(void) { + /* Re-config MRC3 for SRAM0 in case protected by S400 */ + xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000); + xrdc_config_mrc_dx_perm(3, 0, 0, 1); + xrdc_config_mrc_dx_perm(3, 0, 1, 1); + xrdc_config_mrc_dx_perm(3, 0, 4, 1); + xrdc_config_mrc_dx_perm(3, 0, 5, 1); + xrdc_config_mrc_dx_perm(3, 0, 6, 1); + xrdc_config_mrc_dx_perm(3, 0, 7, 1); + xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF); + + /* Clear other 3 regions of MRC3 to invalid */ + xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0); + + /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */ + xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(4, 0, 1, 1); + xrdc_config_mrc_dx_perm(4, 0, 7, 1); + xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF); + + xrdc_config_mrc_w0_w1(5, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(5, 0, 1, 1); + xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF); + + /* Set MRC6 for DDR access from Sentinel */ + xrdc_config_mrc_w0_w1(6, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(6, 0, 4, 1); + xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF); + /* The MRC8 is for SRAM1 */ xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000); /* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index dc1fa70e3c..6e20b11801 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -13,8 +13,8 @@ #include <efi_loader.h> #include <spl.h> #include <asm/arch/rdc.h> -#include <asm/arch/s400_api.h> -#include <asm/arch/mu_hal.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/mu_hal.h> #include <cpu_func.h> #include <asm/setup.h> #include <dm.h> @@ -152,9 +152,18 @@ int board_usb_gadget_port_auto(void) } #endif +static void set_cpu_info(struct sentinel_get_info_data *info) +{ + gd->arch.soc_rev = info->soc; + gd->arch.lifecycle = info->lc; + memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); +} + u32 get_cpu_rev(void) { - return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; + u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; + + return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev); } enum bt_mode get_boot_mode(void) @@ -177,14 +186,70 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - u32 gp6 = 0; + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 gp6 = 0; + + /* DGO_GP6 */ + gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); + if (gp6 & (1 << 5)) + return true; + + return false; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x1) + return true; + + return false; + } +} + +bool rdc_enabled_in_boot(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 val = 0; + int ret; + bool rdc_en = true; /* Default assume DBD_EN is set */ - /* DGO_GP6 */ - gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); - if (gp6 & (1 << 5)) - return true; + /* Read DBD_EN fuse */ + ret = fuse_read(8, 1, &val); + if (!ret) + rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/ + + return rdc_en; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x2) + return true; + + return false; + } +} + +static void spl_pass_boot_info(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + bool m33_booted = m33_image_booted(); + bool rdc_en = rdc_enabled_in_boot(); + u32 val = 0; + + if (m33_booted) + val |= 0x1; + + if (rdc_en) + val |= 0x2; + + writel(val, SIM1_BASE_ADDR); + } +} - return false; +bool is_m33_handshake_necessary(void) +{ + /* Only need handshake in u-boot */ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return (m33_image_booted() || rdc_enabled_in_boot()); + else + return false; } int m33_image_handshake(ulong timeout_ms) @@ -290,7 +355,7 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); -#if defined(CONFIG_IMX_PMC_TEMPERATURE) +#if defined(CONFIG_SCMI_THERMAL) struct udevice *udev; int ret, temp; @@ -632,33 +697,65 @@ static void set_core0_reset_vector(u32 entry) setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); } -static int trdc_set_access(void) +/* Not used now */ +int trdc_set_access(void) { /* * TRDC mgr + 4 MBC + 2 MRC. - * S400 should already configure when release RDC - * A35 only map non-secure region for pbridge0 and 1, set sec_access to false */ - trdc_mbc_set_access(2, 7, 0, 49, false); - trdc_mbc_set_access(2, 7, 0, 50, false); - trdc_mbc_set_access(2, 7, 0, 51, false); - trdc_mbc_set_access(2, 7, 0, 52, false); - trdc_mbc_set_access(2, 7, 0, 53, false); - trdc_mbc_set_access(2, 7, 0, 54, false); - - /* CGC0: PBridge0 slot 47 */ + trdc_mbc_set_access(2, 7, 0, 49, true); + trdc_mbc_set_access(2, 7, 0, 50, true); + trdc_mbc_set_access(2, 7, 0, 51, true); + trdc_mbc_set_access(2, 7, 0, 52, true); + trdc_mbc_set_access(2, 7, 0, 53, true); + trdc_mbc_set_access(2, 7, 0, 54, true); + + /* 0x1fff8000 used for resource table by remoteproc */ + trdc_mbc_set_access(0, 7, 2, 31, false); + + /* CGC0: PBridge0 slot 47 and PCC0 slot 48 */ trdc_mbc_set_access(2, 7, 0, 47, false); + trdc_mbc_set_access(2, 7, 0, 48, false); + + /* PCC1 */ + trdc_mbc_set_access(2, 7, 1, 17, false); + trdc_mbc_set_access(2, 7, 1, 34, false); /* Iomuxc0: : PBridge1 slot 33 */ trdc_mbc_set_access(2, 7, 1, 33, false); /* flexspi0 */ + trdc_mbc_set_access(2, 7, 0, 57, false); trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); /* tpm0: PBridge1 slot 21 */ trdc_mbc_set_access(2, 7, 1, 21, false); /* lpi2c0: PBridge1 slot 24 */ trdc_mbc_set_access(2, 7, 1, 24, false); + + /* Allow M33 to access TRDC MGR */ + trdc_mbc_set_access(2, 6, 0, 49, true); + trdc_mbc_set_access(2, 6, 0, 50, true); + trdc_mbc_set_access(2, 6, 0, 51, true); + trdc_mbc_set_access(2, 6, 0, 52, true); + trdc_mbc_set_access(2, 6, 0, 53, true); + trdc_mbc_set_access(2, 6, 0, 54, true); + + /* Set SAI0 for eDMA 0, NS */ + trdc_mbc_set_access(2, 0, 1, 28, false); + + /* Set SSRAM for eDMA0 access */ + trdc_mbc_set_access(0, 0, 2, 0, false); + trdc_mbc_set_access(0, 0, 2, 1, false); + trdc_mbc_set_access(0, 0, 2, 2, false); + trdc_mbc_set_access(0, 0, 2, 3, false); + trdc_mbc_set_access(0, 0, 2, 4, false); + trdc_mbc_set_access(0, 0, 2, 5, false); + trdc_mbc_set_access(0, 0, 2, 6, false); + trdc_mbc_set_access(0, 0, 2, 7, false); + + writel(0x800000a0, 0x28031840); + return 0; } @@ -705,10 +802,6 @@ void set_lpav_qos(void) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - u32 val = 0; - int ret; - bool rdc_en = true; /* Default assume DBD_EN is set */ - /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -725,29 +818,21 @@ int arch_cpu_init(void) /* Disable wdog */ init_wdog(); - /* Read DBD_EN fuse */ - ret = fuse_read(8, 1, &val); - if (!ret) - rdc_en = !!(val & 0x4000); - if (get_boot_mode() == SINGLE_BOOT) { - if (rdc_en) - release_rdc(RDC_TRDC); - - trdc_set_access(); - lpav_configure(false); } else { lpav_configure(true); } /* Release xrdc, then allow A35 to write SRAM2 */ - if (rdc_en) + if (rdc_enabled_in_boot()) release_rdc(RDC_XRDC); xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); clock_init_early(); + + spl_pass_boot_info(); } else { /* reconfigure core0 reset vector to ROM */ set_core0_reset_vector(0x1000); @@ -756,10 +841,36 @@ int arch_cpu_init(void) return 0; } +int checkcpu(void) +{ + if (is_m33_handshake_necessary()) { + if (!gd->arch.m33_handshake_done) { + puts("M33 Sync: Timeout, Boot Stop!\n"); + hang(); + } else { + puts("M33 Sync: OK\n"); + } + } + return 0; +} + int arch_cpu_init_dm(void) { struct udevice *devp; int node, ret; + u32 res; + struct sentinel_get_info_data info; + + if (!IS_ENABLED(CONFIG_SPL_BUILD) && is_m33_handshake_necessary()) { + /* Start handshake with M33 to ensure TRDC configuration completed */ + ret = m33_image_handshake(1000); + if (!ret) { + gd->arch.m33_handshake_done = true; + } else { + gd->arch.m33_handshake_done = false; + return 0; /* Skip and go through to panic in checkcpu as console is ready then */ + } + } node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu"); @@ -769,6 +880,16 @@ int arch_cpu_init_dm(void) return ret; } + ret = ahab_get_info(&info, &res); + if (ret) { + printf("ahab_get_info failed %d\n", ret); + /* fallback to A0.1 revision */ + memset((void *)&info, 0, sizeof(struct sentinel_get_info_data)); + info.soc = 0xa000084d; + } + + set_cpu_info(&info); + return 0; } @@ -856,7 +977,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc; u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev) { /* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */ - if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en()) + if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && + card_emmc_is_boot_part_en()) image_offset = 0; return image_offset; diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index c24bc079ec..ee215a4c76 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -6,6 +6,7 @@ #include <log.h> #include <asm/io.h> #include <linux/delay.h> +#include <asm/arch/sys_proto.h> #include "upower_soc_defs.h" #include "upower_api.h" @@ -13,6 +14,24 @@ #define UPOWER_AP_MU1_ADDR 0x29280000 +#define PS_RTD BIT(0) +#define PS_DSP BIT(1) +#define PS_A35_0 BIT(2) +#define PS_A35_1 BIT(3) +#define PS_L2 BIT(4) +#define PS_FAST_NIC BIT(5) +#define PS_APD_PERIPH BIT(6) +#define PS_GPU3D BIT(7) +#define PS_HIFI4 BIT(8) +#define PS_DDR GENMASK(12, 9) +#define PS_PXP_EPDC BIT(13) +#define PS_MIPI_DSI BIT(14) +#define PS_MIPI_CSI BIT(15) +#define PS_NIC_LPAV BIT(16) +#define PS_FUSION_AO BIT(17) +#define PS_FUSE BIT(18) +#define PS_UPOWER BIT(19) + static struct MU_tag *muptr = (struct MU_tag *)UPOWER_AP_MU1_ADDR; extern void upwr_txrx_isr(void); @@ -123,6 +142,7 @@ int upower_init(void) u32 fw_major, fw_minor, fw_vfixes; u32 soc_id; int status; + upwr_resp_t err_code; uint32_t swton; uint64_t memon; @@ -155,27 +175,92 @@ int upower_init(void) } } while(0); - swton = 0xfff80; + swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR | + PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI; ret = upwr_pwm_power_on(&swton, NULL /* no memories */, NULL /* no callback */); if (ret) printf("Turn on switches fail %d\n", ret); else - printf("Turn on switches ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on switches...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on switches ok\n"); - memon = 0x3FFFFFFFFFFFFCUL; + /* + * Ascending Order -> bit [0:54) + * CA35 Core 0 L1 cache + * CA35 Core 1 L1 cache + * L2 Cache 0 + * L2 Cache 1 + * L2 Cache victim/tag + * CAAM Secure RAM + * DMA1 RAM + * FlexSPI2 FIFO, Buffer + * SRAM0 + * AD ROM + * USB0 TX/RX RAM + * uSDHC0 FIFO RAM + * uSDHC1 FIFO RAM + * uSDHC2 FIFO and USB1 TX/RX RAM + * GIC RAM + * ENET TX FIXO + * Reserved(Brainshift) + * DCNano Tile2Linear and RGB Correction + * DCNano Cursor and FIFO + * EPDC LUT + * EPDC FIFO + * DMA2 RAM + * GPU2D RAM Group 1 + * GPU2D RAM Group 2 + * GPU3D RAM Group 1 + * GPU3D RAM Group 2 + * HIFI4 Caches, IRAM, DRAM + * ISI Buffers + * MIPI-CSI FIFO + * MIPI-DSI FIFO + * PXP Caches, Buffers + * SRAM1 + * Casper RAM + * DMA0 RAM + * FlexCAN RAM + * FlexSPI0 FIFO, Buffer + * FlexSPI1 FIFO, Buffer + * CM33 Cache + * PowerQuad RAM + * ETF RAM + * Sentinel PKC, Data RAM1, Inst RAM0/1 + * Sentinel ROM + * uPower IRAM/DRAM + * uPower ROM + * CM33 ROM + * SSRAM Partition 0 + * SSRAM Partition 1 + * SSRAM Partition 2,3,4 + * SSRAM Partition 5 + * SSRAM Partition 6 + * SSRAM Partition 7_a(128KB) + * SSRAM Partition 7_b(64KB) + * SSRAM Partition 7_c(64KB) + * Sentinel Data RAM0, Inst RAM2 + */ + /* MIPI-CSI FIFO BIT28 not set */ + memon = 0x3FFFFFEFFFFFFCUL; ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon /* no memories */, NULL /* no callback */); if (ret) printf("Turn on memories fail %d\n", ret); else - printf("Turn on memories ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on memories...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on memories ok\n"); mdelay(1); @@ -183,28 +268,34 @@ int upower_init(void) if (ret) printf("Clear DDR retention fail %d\n", ret); else - printf("Clear DDR retention ok\n"); + printf("Clearing DDR retention...\n"); upower_wait_resp(); - - ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000); + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Clear DDR retention ok\n"); - /* Enable AFBB for AP domain */ - bias.apply = BIAS_APPLY_APD; - bias.dommode = AFBB_BIAS_MODE; - ret = upwr_pwm_chng_dom_bias(&bias, NULL); + if (is_soc_rev(CHIP_REV_1_0)) { + /* Enable AFBB for AP domain */ + bias.apply = BIAS_APPLY_APD; + bias.dommode = AFBB_BIAS_MODE; + ret = upwr_pwm_chng_dom_bias(&bias, NULL); - if (ret) - printf("Enable AFBB for APD bias fail %d\n", ret); - else - printf("Enable AFBB for APD bias ok\n"); + if (ret) + printf("Enable AFBB for APD bias fail %d\n", ret); + else + printf("Enabling AFBB for APD bias...\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); - if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); + if (ret != UPWR_REQ_OK) + printf("Enable AFBB fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Enable AFBB for APD bias ok\n"); + + } return 0; } diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig new file mode 100644 index 0000000000..f4fc1ac5ce --- /dev/null +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -0,0 +1,46 @@ +if ARCH_IMX9 + +config AHAB_BOOT + bool "Support i.MX9 AHAB features" + help + This option enables the support for AHAB secure boot. + +config IMX9_LOW_DRIVE_MODE + bool "Configure to i.MX9 low drive mode" + help + This option enables the settings for iMX9 low drive mode. + +config IMX9 + bool + select ARCH_EARLY_INIT_R + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + +config IMX93 + bool + select IMX9 + select ARMV8_SPL_EXCEPTION_VECTORS + +config SYS_SOC + default "imx9" + +choice + prompt "NXP i.MX9 board select" + optional + +config TARGET_IMX93_11X11_EVK + bool "imx93_11x11_evk" + select IMX93 + +config TARGET_IMX93_9X9_QSB + bool "imx93_9x9_qsb" + select IMX93 + select IMX9_LPDDR4X + +endchoice + +source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_qsb/Kconfig" + +endif + diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile new file mode 100644 index 0000000000..e1b09ab534 --- /dev/null +++ b/arch/arm/mach-imx/imx9/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2022 NXP + +obj-y += lowlevel_init.o +obj-y += soc.o clock.o clock_root.o trdc.o + +#ifndef CONFIG_SPL_BUILD +obj-y += imx_bootaux.o +#endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c new file mode 100644 index 0000000000..909a770e1c --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock.c @@ -0,0 +1,947 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <div64.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; + +static struct imx_intpll_rate_table imx9_intpll_tbl[] = { + INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ + INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */ + INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ + INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ + INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ +}; + +static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { + FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ + FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ + FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ + FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), + FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), + FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ + FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ + FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), +}; + +/* return in khz */ +static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl; + u32 pll_status; + u32 div; + int rdiv, mfi, mfn, mfd; + int clk = 24000; + + ctrl = readl(®->ctrl.reg); + pll_status = readl(®->pll_status); + div = readl(®->div.reg); + + if (!(ctrl & PLL_CTRL_POWERUP)) + return 0; + + if (!(pll_status & PLL_STATUS_PLL_LOCK)) + return 0; + + mfi = (div & GENMASK(24, 16)) >> 16; + rdiv = (div & GENMASK(15, 13)) >> 13; + + if (rdiv == 0) + rdiv = 1; + + if (fracpll) { + mfn = (int)readl(®->num.reg); + mfn >>= 2; + mfd = (int)(readl(®->denom.reg) & GENMASK(29, 0)); + + clk = clk * (mfi * mfd + mfn) / mfd / rdiv; + } else { + clk = clk * mfi / rdiv; + } + + return (u32)clk; +} + +/* return in khz */ +static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl = readl(®->ctrl.reg); + u32 div; + + if (ctrl & PLL_CTRL_CLKMUX_BYPASS) + return 24000; + + if (!(ctrl & PLL_CTRL_CLKMUX_EN)) + return 0; + + div = readl(®->div.reg); + div &= 0xff; /* odiv */ + + if (div == 0) + div = 2; + else if (div == 1) + div = 3; + + return decode_pll_vco(reg, fracpll) / div; +} + +/* return in khz */ +static u32 decode_pll_pfd(struct ana_pll_reg *reg, + struct ana_pll_dfs *dfs_reg, bool div2, bool fracpll) +{ + u32 pllvco = decode_pll_vco(reg, fracpll); + u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg); + u32 dfs_div = readl(&dfs_reg->dfs_div.reg); + u32 mfn, mfi; + u32 output; + + if (dfs_ctrl & PLL_DFS_CTRL_BYPASS) + return pllvco; + + if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) || + (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) || + (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT))) + return 0; + + mfn = dfs_div & GENMASK(2, 0); + mfi = (dfs_div & GENMASK(15, 8)) >> 8; + + if (mfn > 3) + return 0; /* valid mfn 0-3 */ + + if (mfi == 0 || mfi == 1) + return 0; /* valid mfi 2-255 */ + + output = (pllvco * 5) / (mfi * 5 + mfn); + + if (div2) + return output >> 1; + + return output; +} + +static u32 decode_pll(enum ccm_clk_src pll) +{ + switch (pll) { + case ARM_PLL_CLK: + return decode_pll_out(&ana_regs->arm_pll, false); + case SYS_PLL_PG: + return decode_pll_out(&ana_regs->sys_pll, false); + case SYS_PLL_PFD0: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], false, true); + case SYS_PLL_PFD0_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], true, true); + case SYS_PLL_PFD1: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], false, true); + case SYS_PLL_PFD1_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], true, true); + case SYS_PLL_PFD2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], false, true); + case SYS_PLL_PFD2_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], true, true); + case AUDIO_PLL_CLK: + return decode_pll_out(&ana_regs->audio_pll, true); + case DRAM_PLL_CLK: + return decode_pll_out(&ana_regs->dram_pll, true); + case VIDEO_PLL_CLK: + return decode_pll_out(&ana_regs->video_pll, true); + default: + printf("Invalid clock source to decode\n"); + break; + } + + return 0; +} + +int configure_intpll(enum ccm_clk_src pll, u32 freq) +{ + int i; + struct imx_intpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + + for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) { + if (freq == imx9_intpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_intpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_intpll_tbl[i]; + + /* ROM has configured SYS PLL and PFD, no need for it */ + switch (pll) { + case ARM_PLL_CLK: + reg = &ana_regs->arm_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | + ((rate->rdiv << 13 ) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* wait 5us */ + udelay(5); +#endif + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + udelay(100); +#endif + + pll_status = readl(®->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set); + + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + + +int configure_fracpll(enum ccm_clk_src pll, u32 freq) +{ + int i; + struct imx_fracpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + + for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) { + if (freq == imx9_fracpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_fracpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_fracpll_tbl[i]; + + switch (pll) { + case SYS_PLL_PG: + reg = &ana_regs->sys_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | + ((rate->rdiv << 13 ) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg); + + /* Set SPREAD_SPECRUM enable to 0 */ + writel(PLL_SS_EN, ®->ss.reg_clr); + + /* Program NUMERATOR and DENOMINATOR */ + writel((rate->mfn << 2), ®->num.reg); + writel((rate->mfd & GENMASK(29, 0)), ®->denom.reg); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* wait 5us */ + udelay(5); +#endif + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + udelay(100); +#endif + + pll_status = readl(®->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* check the MFN is updated */ + pll_status = readl(®->pll_status); + if ((pll_status & ~0x3) != (rate->mfn << 2)) { + debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n", + pll_status, rate->mfn); + return -EIO; + } +#endif + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + +int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en) +{ + struct ana_pll_dfs *dfs; + struct ana_pll_reg *reg; + u32 dfs_status; + u32 index; + + if (mfn > 3) + return -EINVAL; /* valid mfn 0-3 */ + + if (mfi < 2 || mfi > 255) + return -EINVAL; /* valid mfi 2-255 */ + + switch (pll_pfg) { + case SYS_PLL_PFD0: + reg = &ana_regs->sys_pll; + index = 0; + break; + case SYS_PLL_PFD1: + reg = &ana_regs->sys_pll; + index = 1; + break; + case SYS_PLL_PFD2: + reg = &ana_regs->sys_pll; + index = 2; + break; + default: + return -EPERM; + } + + dfs = ®->dfs[index]; + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set); + + /* disable DFS and output */ + writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT | + PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr); + + writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)), + &dfs->dfs_div.reg); + + writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set); + if (div2_en) + writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set); + writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set); + +#ifndef CONFIG_TARGET_IMX93_EMU + /* + * As HW expert said: after enabling the DFS, clock will start + * coming after 6 cycles output clock period. + * 5us is much bigger than expected, so it will be safe + */ + udelay(5); +#endif + + dfs_status = readl(®->dfs_status); + + if (!(dfs_status & (1 << index))) { + debug("DFS lock failed\n"); + return -EIO; + } + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr); + + return 0; +} + +int update_fracpll_mfn(enum ccm_clk_src pll, int mfn) +{ + struct ana_pll_reg *reg; + bool repoll = false; + u32 pll_status; + int count = 20; + + switch (pll) { + case AUDIO_PLL_CLK: + reg = &ana_regs->audio_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + printf("Invalid pll %u for update FRAC PLL MFN\n", pll); + return -EINVAL; + } + + if (readl(®->pll_status) & PLL_STATUS_PLL_LOCK) + repoll = true; + + mfn <<= 2; + writel(mfn, ®->num); + + if (repoll) { + do { + pll_status = readl(®->pll_status); + udelay(5); + count--; + } while (((pll_status & ~0x3) != (u32)mfn) && count > 0); + + if (count <= 0) { + printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n", + pll_status, mfn); + return -EIO; + } + } + + return 0; +} + +int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn) +{ + struct ana_pll_dfs *dfs; + u32 val; + u32 index; + + switch (pll_pfd) { + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + index = 0; + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + index = 1; + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + index = 2; + break; + default: + printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd); + return -EINVAL; + } + + dfs = &ana_regs->sys_pll.dfs[index]; + + val = readl(&dfs->dfs_div.reg); + val &= ~0x3; + val |= mfn & 0x3; + writel(val, &dfs->dfs_div.reg); + + return 0; +} + +/* return in khz */ +u32 get_clk_src_rate(enum ccm_clk_src source) +{ + u32 ctrl; + bool clk_on; + + switch (source) { + case ARM_PLL_CLK: + ctrl = readl(&ana_regs->arm_pll.ctrl.reg); + case AUDIO_PLL_CLK: + ctrl = readl(&ana_regs->audio_pll.ctrl.reg); + break; + case DRAM_PLL_CLK: + ctrl = readl(&ana_regs->dram_pll.ctrl.reg); + break; + case VIDEO_PLL_CLK: + ctrl = readl(&ana_regs->video_pll.ctrl.reg); + break; + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg); + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg); + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg); + break; + case OSC_24M_CLK: + return 24000; + default: + printf("Invalid clock source to get rate\n"); + return 0; + } + + if (ctrl & PLL_CTRL_HW_CTRL_SEL) { + /* When using HW ctrl, check OSCPLL */ + clk_on = ccm_clk_src_is_clk_on(source); + if (clk_on) + return decode_pll(source); + else + return 0; + } else { + /* controlled by pll registers */ + return decode_pll(source); + } +} + +u32 get_arm_core_clk(void) +{ + u32 val; + ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val); + + if (val & SHARED_GPR_A55_CLK_SEL_PLL) + return decode_pll(ARM_PLL_CLK) * 1000; + + return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT); +} + +void set_arm_core_max_clk(void) +{ + u32 speed; + + /* Increase ARM clock to max rate according to speed grade */ + speed = get_cpu_speed_grade_hz(); + + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, speed); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + +void set_arm_core_low_drive_clk(void) +{ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 900000000); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_arm_core_clk(); + case MXC_IPG_CLK: + return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT); + case MXC_CSPI_CLK: + return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT); + case MXC_ESDHC_CLK: + return ccm_clk_root_get_rate(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return ccm_clk_root_get_rate(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return ccm_clk_root_get_rate(USDHC3_CLK_ROOT); + case MXC_UART_CLK: + return ccm_clk_root_get_rate(LPUART1_CLK_ROOT); + case MXC_FLEXSPI_CLK: + return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT); + default: + return -1; + }; + + return -1; +}; + +int enable_i2c_clk(unsigned char enable, u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + if (enable) { + /* 24M */ + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_I2C1 + i2c_num, true); + } else { + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + } + + return 0; +} + +u32 imx_get_i2cclk(u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num); +} + +u32 get_lpuart_clk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + +void init_uart_clk(u32 index) +{ + switch(index) { + case LPUART1_CLK_ROOT: + /* 24M */ + ccm_lpcg_on(CCGR_URT1, false); + ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_URT1, true); + break; + default: + break; + } +} + +void init_clk_usdhc(u32 index) +{ + u32 div; + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + div = 3; /* 266.67 Mhz */ + else + div = 2; /* 400 Mhz */ + + switch (index) { + case 0: + ccm_lpcg_on(CCGR_USDHC1, 0); + ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC1, 1); + break; + case 1: + ccm_lpcg_on(CCGR_USDHC2, 0); + ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC2, 1); + break; + case 2: + ccm_lpcg_on(CCGR_USDHC3, 0); + ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div); + ccm_lpcg_on(CCGR_USDHC3, 1); + break; + default: + return; + }; +} + +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + ccm_lpcg_on(CCGR_USBC, 1); + } else { + ccm_lpcg_on(CCGR_USBC, 0); + } +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(ulong pll_val) +{ + configure_fracpll(DRAM_PLL_CLK, pll_val); +} + +void dram_enable_bypass(ulong clk_val) +{ + switch (clk_val) { + case MHZ(400): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); + break; + case MHZ(333): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3); + break; + case MHZ(200): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4); + break; + case MHZ(100): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8); + break; + default: + printf("No matched freq table %lu\n", clk_val); + return; + } + + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from PLL to CCM */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM); +} + +void dram_disable_bypass(void) +{ + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Switch from DRAM clock root from CCM to PLL */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); +} +#endif + +void bus_clock_init_low_drive(void) +{ + /* Set A55 clk to 500M */ + ccm_clk_root_cfg(ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2); + /* Set A55 periphal to 200M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 133M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 133M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* WAKEUP_AXI to 200M */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + /* NIC to 250M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD0, 4); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +void bus_clock_init(void) +{ + /* Set A55 periphal to 333M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 200M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 200M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for generating MII clock at 2.5M */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + /* NIC to 400M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +int clock_init(void) +{ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + bus_clock_init_low_drive(); + set_arm_core_low_drive_clk(); + } else { + bus_clock_init(); + } + + /* allow for non-secure access */ + int i; + for (i = 0; i < OSCPLL_END; i++) + ccm_clk_src_tz_access(i, true, false, false); + + for (i = 0; i < CLK_ROOT_NUM; i++) + ccm_clk_root_tz_access(i, true, false, false); + + for (i = 0; i < CCGR_NUM; i++) + ccm_lpcg_tz_access(i, true, false, false); + + for (i = 0; i < SHARED_GPR_NUM; i++) + ccm_shared_gpr_tz_access(i, true, false, false); + + return 0; +} + +int set_clk_eqos(enum enet_freq type) +{ + u32 eqos_post_div; + + switch (type) { + case ENET_125MHZ: + eqos_post_div = 2; /* 250M clock */ + break; + case ENET_50MHZ: + eqos_post_div = 5; /* 100M clock */ + break; + case ENET_25MHZ: + eqos_post_div = 10; /* 50M clock*/ + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENETQOS, false); + + ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div); + ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + + /* enable clock */ + ccm_lpcg_on(CCGR_ENETQOS, true); + + return 0; +} + +u32 imx_get_eqos_csr_clk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +u32 imx_get_fecclk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +int set_clk_enet(enum enet_freq type) +{ + u32 div; + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENET1, false); + + switch (type) { + case ENET_125MHZ: + div = 2; /* 250Mhz */ + break; + case ENET_50MHZ: + div = 5; /* 100Mhz */ + break; + case ENET_25MHZ: + div = 10; /* 50Mhz */ + break; + default: + return -EINVAL; + } + + ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div); + ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20); +#endif + + /* enable clock */ + ccm_lpcg_on(CCGR_ENET1, true); + + return 0; +} + +void mxs_set_lcdclk(u32 base_addr, u32 freq) +{ + u32 div, i, krate, temp; + u32 best = 0, best_div = 0, best_pll = 0; + + debug("%s to set rate to %dkhz\n", __func__, freq); + + for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) { + krate = imx9_fracpll_tbl[i].rate / 1000; + div = (krate + freq - 1) / freq; + + if (div > 256) + continue; + + temp = krate / div; + if (best == 0 || temp > best) { + best = temp; + best_div = div; + best_pll = imx9_fracpll_tbl[i].rate; + } + } + + if (best == 0) { + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq); + return; + } + + /* Select to video PLL */ + debug("%s, best_pll = %u, div = %u\n", __func__, best_pll, best_div); + + configure_fracpll(VIDEO_PLL_CLK, best_pll); + ccm_clk_root_cfg(MEDIA_DISP_PIX_CLK_ROOT, VIDEO_PLL_CLK, best_div); +} + +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + + freq = decode_pll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(DRAM_PLL_CLK); + printf("DRAM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0); + printf("SYS_PLL_PFD0 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0_DIV2); + printf("SYS_PLL_PFD0_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1); + printf("SYS_PLL_PFD1 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1_DIV2); + printf("SYS_PLL_PFD1_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2); + printf("SYS_PLL_PFD2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2_DIV2); + printf("SYS_PLL_PFD2_DIV2 %8d MHz\n", freq / 1000); + freq = mxc_get_clock(MXC_ARM_CLK); + printf("ARM CORE %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_IPG_CLK); + printf("IPG %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_UART_CLK); + printf("UART3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_ESDHC_CLK); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_FLEXSPI_CLK); + printf("FLEXSPI %8d MHz\n", freq / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); +#endif + diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c new file mode 100644 index 0000000000..5748e28ff0 --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/ccm_regs.h> +#include <asm/global_data.h> +#include <linux/iopoll.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; + +static enum ccm_clk_src clk_root_mux[][4] = { + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/ + { OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */ +}; + +static struct clk_root_map clk_root_array[] = { + { ARM_A55_PERIPH_CLK_ROOT, 0 }, + { ARM_A55_MTR_BUS_CLK_ROOT, 2 }, + { ARM_A55_CLK_ROOT, 0 }, + { M33_CLK_ROOT, 2 }, + { SENTINEL_CLK_ROOT, 2 }, + { BUS_WAKEUP_CLK_ROOT, 2 }, + { BUS_AON_CLK_ROOT, 2 }, + { WAKEUP_AXI_CLK_ROOT, 0 }, + { SWO_TRACE_CLK_ROOT, 2 }, + { M33_SYSTICK_CLK_ROOT, 2 }, + { FLEXIO1_CLK_ROOT, 2 }, + { FLEXIO2_CLK_ROOT, 2 }, + { LPIT1_CLK_ROOT, 2 }, + { LPIT2_CLK_ROOT, 2 }, + { LPTMR1_CLK_ROOT, 2 }, + { LPTMR2_CLK_ROOT, 2 }, + { TPM1_CLK_ROOT, 3 }, + { TPM2_CLK_ROOT, 3 }, + { TPM3_CLK_ROOT, 3 }, + { TPM4_CLK_ROOT, 3 }, + { TPM5_CLK_ROOT, 3 }, + { TPM6_CLK_ROOT, 3 }, + { FLEXSPI1_CLK_ROOT, 0 }, + { CAN1_CLK_ROOT, 2 }, + { CAN2_CLK_ROOT, 2 }, + { LPUART1_CLK_ROOT, 2 }, + { LPUART2_CLK_ROOT, 2 }, + { LPUART3_CLK_ROOT, 2 }, + { LPUART4_CLK_ROOT, 2 }, + { LPUART5_CLK_ROOT, 2 }, + { LPUART6_CLK_ROOT, 2 }, + { LPUART7_CLK_ROOT, 2 }, + { LPUART8_CLK_ROOT, 2 }, + { LPI2C1_CLK_ROOT, 2 }, + { LPI2C2_CLK_ROOT, 2 }, + { LPI2C3_CLK_ROOT, 2 }, + { LPI2C4_CLK_ROOT, 2 }, + { LPI2C5_CLK_ROOT, 2 }, + { LPI2C6_CLK_ROOT, 2 }, + { LPI2C7_CLK_ROOT, 2 }, + { LPI2C8_CLK_ROOT, 2 }, + { LPSPI1_CLK_ROOT, 2 }, + { LPSPI2_CLK_ROOT, 2 }, + { LPSPI3_CLK_ROOT, 2 }, + { LPSPI4_CLK_ROOT, 2 }, + { LPSPI5_CLK_ROOT, 2 }, + { LPSPI6_CLK_ROOT, 2 }, + { LPSPI7_CLK_ROOT, 2 }, + { LPSPI8_CLK_ROOT, 2 }, + { I3C1_CLK_ROOT, 2 }, + { I3C2_CLK_ROOT, 2 }, + { USDHC1_CLK_ROOT, 0 }, + { USDHC2_CLK_ROOT, 0 }, + { USDHC3_CLK_ROOT, 0 }, + { SAI1_CLK_ROOT, 4 }, + { SAI2_CLK_ROOT, 4 }, + { SAI3_CLK_ROOT, 4 }, + { CCM_CKO1_CLK_ROOT, 6 }, + { CCM_CKO2_CLK_ROOT, 7 }, + { CCM_CKO3_CLK_ROOT, 6 }, + { CCM_CKO4_CLK_ROOT, 7 }, + { HSIO_CLK_ROOT, 2 }, + { HSIO_USB_TEST_60M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_80M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_480M_CLK_ROOT, 0 }, + { NIC_CLK_ROOT, 0 }, + { NIC_APB_CLK_ROOT, 2 }, + { ML_APB_CLK_ROOT, 2 }, + { ML_CLK_ROOT, 0 }, + { MEDIA_AXI_CLK_ROOT, 0 }, + { MEDIA_APB_CLK_ROOT, 2 }, + { MEDIA_LDB_CLK_ROOT, 5 }, + { MEDIA_DISP_PIX_CLK_ROOT, 5 }, + { CAM_PIX_CLK_ROOT, 5 }, + { MIPI_TEST_BYTE_CLK_ROOT, 5 }, + { MIPI_PHY_CFG_CLK_ROOT, 5 }, + { DRAM_ALT_CLK_ROOT, 0 }, + { DRAM_APB_CLK_ROOT, 1 }, + { ADC_CLK_ROOT, 2 }, + { PDM_CLK_ROOT, 4 }, + { TSTMR1_CLK_ROOT, 2 }, + { TSTMR2_CLK_ROOT, 2 }, + { MQS1_CLK_ROOT, 4 }, + { MQS2_CLK_ROOT, 4 }, + { AUDIO_XCVR_CLK_ROOT, 1 }, + { SPDIF_CLK_ROOT, 4 }, + { ENET_CLK_ROOT, 1 }, + { ENET_TIMER1_CLK_ROOT, 2 }, + { ENET_TIMER2_CLK_ROOT, 2 }, + { ENET_REF_CLK_ROOT, 1 }, + { ENET_REF_PHY_CLK_ROOT, 2 }, + { I3C1_SLOW_CLK_ROOT, 2 }, + { I3C2_SLOW_CLK_ROOT, 2 }, + { USB_PHY_BURUNIN_CLK_ROOT, 2 }, + { PAL_CAME_SCAN_CLK_ROOT, 8 }, +}; + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_oscplls[oscpll].direct); + else + writel(0, &ccm_reg->clk_oscplls[oscpll].direct); + + return 0; +} + +/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */ +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) { + writel(authen | CCM_AUTHEN_AUTO_CTRL, + &ccm_reg->clk_oscplls[oscpll].authen); + } else + writel((authen & ~CCM_AUTHEN_AUTO_CTRL), + &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */ + if (authen & CCM_AUTHEN_AUTO_CTRL) + return -EPERM; + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, + &ccm_reg->clk_oscplls[oscpll].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), + &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (oscpll >= OSCPLL_END || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1); + } else { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0); + } + + return 0; +} + +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll) +{ + return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1); +} + +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div) +{ + int i; + int ret; + u32 mux, status; + + if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0) + return -EINVAL; + + mux = clk_root_array[clk_root_id].mux_type; + + for (i = 0; i < 4; i++) { + if (src == clk_root_mux[mux][i]) + break; + } + + if (i == 4) { + printf("Invalid source [%u] for this clk root\n", src); + return -EINVAL; + } + + writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control); + + ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status, + !(status & CLK_ROOT_STATUS_CHANGING), 200000); + if (ret) + printf("%s: failed, status: 0x%x\n", __func__, + readl(&ccm_reg->clk_roots[clk_root_id].status0)); + + return ret; +}; + +u32 ccm_clk_root_get_rate(u32 clk_root_id) +{ + u32 mux, status, div, rate; + enum ccm_clk_src src; + + if (clk_root_id >= CLK_ROOT_NUM) + return 0; + + status = readl(&ccm_reg->clk_roots[clk_root_id].control); + + if (status & CLK_ROOT_STATUS_OFF) + return 0; /* clock is off */ + + mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT; + div = status & CLK_ROOT_DIV_MASK; + src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux]; + + rate = get_clk_src_rate(src) * 1000; + + return rate / (div + 1); /* return in hz */ +} + +int ccm_clk_root_tz_access(u32 clk_root_id, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (clk_root_id >= CLK_ROOT_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_roots[clk_root_id].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_roots[clk_root_id].authen); + + return 0; +} + +int ccm_lpcg_on(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_lpcgs[lpcg].direct); + else + writel(0, &ccm_reg->clk_lpcgs[lpcg].direct); + + return 0; + +} + +int ccm_lpcg_lpm(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, + &ccm_reg->clk_lpcgs[lpcg].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), + &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (lpcg >= CCGR_NUM || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1); + } else { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0); + } + + return 0; +} + +bool ccm_lpcg_is_clk_on(u32 lpcg) +{ + return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1); +} + +int ccm_lpcg_tz_access(u32 lpcg, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_shared_gpr_set(u32 gpr, u32 val) +{ + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + +int ccm_shared_gpr_get(u32 gpr, u32 *val) +{ + if (gpr >= SHARED_GPR_NUM || !val) + return -EINVAL; + + *val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + + +int ccm_shared_gpr_tz_access(u32 gpr, + bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen); + + return 0; +} diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c new file mode 100644 index 0000000000..721e77193e --- /dev/null +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <asm/mach-imx/sys_proto.h> +#include <command.h> +#include <elf.h> +#include <imx_sip.h> +#include <linux/arm-smccc.h> +#include <linux/compiler.h> +#include <cpu_func.h> + +int arch_auxiliary_core_check_up(u32 core_id) +{ + struct arm_smccc_res res; + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, + 0, 0, 0, 0, &res); + + return res.a0; +} + +int arch_auxiliary_core_down(u32 core_id) +{ + struct arm_smccc_res res; + + printf("## Stopping auxiliary core\n"); + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0, + 0, 0, 0, 0, &res); + + return 0; +} + +int arch_auxiliary_core_up(u32 core_id, ulong addr) +{ + struct arm_smccc_res res; + u32 stack, pc; + + if (!addr) + return -EINVAL; + + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + + printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, + 0, 0, 0, 0, &res); + + return 0; +} + +/* + * To i.MX6SX and i.MX7D, the image supported by bootaux needs + * the reset vector at the head for the image, with SP and PC + * as the first two words. + * + * Per the cortex-M reference manual, the reset vector of M4/M7 needs + * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses + * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset + * vector with getting the PC and SP from image and filling them to + * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself. + * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4/M7 TCMUL/IDTCM. + */ +static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + int ret, up; + u32 core = 0; + u32 stop = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + if (argc > 3) + stop = simple_strtoul(argv[3], NULL, 10); + + up = arch_auxiliary_core_check_up(core); + if (up) { + printf("## Auxiliary core is already up\n"); + return CMD_RET_SUCCESS; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + if (!addr) + return CMD_RET_FAILURE; + + ret = arch_auxiliary_core_up(core, addr); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret, up; + + up = arch_auxiliary_core_check_up(0); + if (!up) { + printf("## Auxiliary core is already down\n"); + return CMD_RET_SUCCESS; + } + + ret = arch_auxiliary_core_down(0); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux, + "Start auxiliary core", + "<address> [<core>]\n" + " - start auxiliary core [<core>] (default 0),\n" + " at address <address>\n" +); + +U_BOOT_CMD( + bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, + "Start auxiliary core", + "<address> [<core>]\n" + " - start auxiliary core [<core>] (default 0),\n" + " at address <address>\n" +); diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S new file mode 100644 index 0000000000..1dc1dbfcdd --- /dev/null +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 256 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: +#ifndef CONFIG_SPL_BUILD + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 +#endif + /* Returns */ + b save_boot_params_ret diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c new file mode 100644 index 0000000000..02edced9aa --- /dev/null +++ b/arch/arm/mach-imx/imx9/soc.c @@ -0,0 +1,1186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/arch/imx-regs.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ccm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/syscounter.h> +#include <asm/armv8/mmu.h> +#include <dm/uclass.h> +#include <env.h> +#include <env_internal.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/bitops.h> +#include <asm/setup.h> +#include <asm/bootm.h> +#include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/optee.h> +#include <linux/delay.h> +#include <fuse.h> +#include <imx_thermal.h> +#include <thermal.h> +#include <imx_sip.h> +#include <linux/arm-smccc.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rom_api *g_rom_api = (struct rom_api *)0x1980; + +enum boot_device get_boot_device(void) +{ + volatile gd_t *pgd = gd; + int ret; + u32 boot; + u16 boot_type; + u8 boot_instance; + enum boot_device boot_dev = SD1_BOOT; + + ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, + ((uintptr_t)&boot) ^ QUERY_BT_DEV); + set_gd(pgd); + + if (ret != ROM_API_OKAY) { + puts("ROMAPI: failure at query_boot_info\n"); + return -1; + } + + boot_type = boot >> 16; + boot_instance = (boot >> 8) & 0xff; + + switch (boot_type) { + case BT_DEV_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BT_DEV_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BT_DEV_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BT_DEV_TYPE_FLEXSPINOR: + boot_dev = QSPI_BOOT; + break; + case BT_DEV_TYPE_USB: + boot_dev = boot_instance + USB_BOOT; + break; + default: + break; + } + + debug("boot dev %d\n", boot_dev); + + return boot_dev; +} + +bool is_usb_boot(void) +{ + enum boot_device bt_dev = get_boot_device(); + return (bt_dev == USB_BOOT || bt_dev == USB2_BOOT); +} + +void disconnect_from_pc(void) +{ + enum boot_device bt_dev = get_boot_device(); + + if (bt_dev == USB_BOOT) + writel(0x0, USB1_BASE_ADDR + 0x140); + else if (bt_dev == USB2_BOOT) + writel(0x0, USB2_BASE_ADDR + 0x140); + + return; +} + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_get_env_dev(void) +{ + volatile gd_t *pgd = gd; + int ret; + u32 boot; + u16 boot_type; + u8 boot_instance; + + ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, + ((uintptr_t)&boot) ^ QUERY_BT_DEV); + set_gd(pgd); + + if (ret != ROM_API_OKAY) { + puts("ROMAPI: failure at query_boot_info\n"); + return CONFIG_SYS_MMC_ENV_DEV; + } + + boot_type = boot >> 16; + boot_instance = (boot >> 8) & 0xff; + + debug("boot_type %d, instance %d\n", boot_type, boot_instance); + + /* If not boot from sd/mmc, use default value */ + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + + return board_mmc_get_env_dev(boot_instance); + +} +#endif + +#ifdef CONFIG_USB_PORT_AUTO +int board_usb_gadget_port_auto(void) +{ + enum boot_device bt_dev = get_boot_device(); + int usb_boot_index = 0; + + if (bt_dev == USB2_BOOT) + usb_boot_index = 1; + + printf("auto usb %d\n", usb_boot_index); + + return usb_boot_index; +} +#endif + +u32 get_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + u32 grade; + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + val >>= 6; + val &= 0xf; + + speed = 2300000000 - val * 100000000; + + if (is_imx93()) { + grade = get_cpu_temp_grade(NULL, NULL); + if (grade == TEMP_INDUSTRIAL) + max_speed = 1500000000; + else + max_speed = 1700000000; + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + } + + return speed; +} + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + + val >>= 4; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + +static void set_cpu_info(struct sentinel_get_info_data *info) +{ + gd->arch.soc_rev = info->soc; + gd->arch.lifecycle = info->lc; + memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); +} + +static u32 get_cpu_variant_type(u32 type) +{ + /* word 19 */ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + bool npu_disable = !!(val & BIT(13)); + bool core1_disable = !!(val & BIT(15)); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val2 & pack_9x9_fused) == pack_9x9_fused) + type = MXC_CPU_IMX9322; + + if (npu_disable && core1_disable) + return type + 3; + else if (npu_disable) + return type + 2; + else if (core1_disable) + return type + 1; + + return type; +} + +u32 get_cpu_rev(void) +{ + u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; + return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) | + (CHIP_REV_1_0 + rev); +} + +#define UNLOCK_WORD 0xD928C520 /* unlock word */ +#define REFRESH_WORD 0xB480A602 /* refresh word */ + +static void disable_wdog(void __iomem *wdog_base) +{ + u32 val_cs = readl(wdog_base + 0x00); + + if (!(val_cs & 0x80)) + return; + + /* default is 32bits cmd */ + writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */ + + if (!(val_cs & 0x800)) { + writel(UNLOCK_WORD, (wdog_base + 0x04)); + while (!(readl(wdog_base + 0x00) & 0x800)) + ; + } + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */ + + while (!(readl(wdog_base + 0x00) & 0x400)) + ; +} + +void init_wdog(void) +{ + u32 src_val; + + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + disable_wdog((void __iomem *)WDG5_BASE_ADDR); + + src_val = readl(0x54460018); /* reset mask */ + src_val &= ~0x1c; + writel(src_val, 0x54460018); +} + +static struct mm_region imx93_mem_map[] = { + { + /* ROM */ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* TCM */ + .virt = 0x201c0000UL, + .phys = 0x201c0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCRAM */ + .virt = 0x20480000UL, + .phys = 0x20480000UL, + .size = 0xA0000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Flexible Serial Peripheral Interface */ + .virt = 0x28000000UL, + .phys = 0x28000000UL, + .size = 0x30000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* empty entrie to split table entry 5 if needed when TEEs are used */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx93_mem_map; + +static unsigned int imx9_find_dram_entry_in_mem_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++) + if (imx93_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + return i; + + hang(); /* Entry not found, this must never happen. */ +} + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch + * If OPTEE does not run, still update the MMU table according to dram banks structure + * to set correct dram size from board_phys_sdram_size + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx93_mem_map for DRAM1 + */ + int entry = imx9_find_dram_entry_in_mem_map(); + u64 attrs = imx93_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && + entry < ARRAY_SIZE(imx93_mem_map)) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx93_mem_map[entry].phys, imx93_mem_map[entry].size); + i++; entry++; + } + + icache_enable(); + dcache_enable(); +} + +__weak int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = PHYS_SDRAM_SIZE; + +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + +int dram_init(void) +{ + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size, sdram_b2_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + sdram_b2_size = sdram_size - 0x80000000; + } else { + sdram_b1_size = sdram_size; + sdram_b2_size = 0; + } + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_b1_size; + } + + if (sdram_b2_size) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = 0x100000000UL; + gd->bd->bi_dram[bank].size = sdram_b2_size; + } + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size; + ret = board_phys_sdram_size(&sdram_size); + if (!ret) { + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + } else { + sdram_b1_size = sdram_size; + } + + if (rom_pointer[1]) { + /* We will relocate u-boot to Top of dram1. Tee position has two cases: + * 1. At the top of dram1, Then return the size removed optee size. + * 2. In the middle of dram1, return the size of dram1. + */ + if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size)) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + } + + return sdram_b1_size; + } else { + return PHYS_SDRAM_SIZE; + } +} + + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + u32 val[2] = {}; + int ret; + + if (dev_id == 0) { + ret = fuse_read(39, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 8; + mac[1] = val[1]; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + + } else { + ret = fuse_read(39, 5, &val[0]); + if (ret) + goto err; + + ret = fuse_read(39, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[1] >> 24; + mac[1] = val[1] >> 16; + mac[2] = val[0] >> 24; + mac[3] = val[0] >> 16; + mac[4] = val[0] >> 8; + mac[5] = val[0]; + } + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: + memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); +} + +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX93: + return "93(52)";/* iMX93 Dual core with NPU */ + case MXC_CPU_IMX9351: + return "93(51)";/* iMX93 Single core with NPU */ + case MXC_CPU_IMX9332: + return "93(32)";/* iMX93 Dual core without NPU */ + case MXC_CPU_IMX9331: + return "93(31)";/* iMX93 Single core without NPU */ + case MXC_CPU_IMX9322: + return "93(22)";/* iMX93 9x9 Dual core */ + case MXC_CPU_IMX9321: + return "93(21)";/* iMX93 9x9 Single core */ + case MXC_CPU_IMX9312: + return "93(12)";/* iMX93 9x9 Dual core without NPU */ + case MXC_CPU_IMX9311: + return "93(11)";/* iMX93 9x9 Single core without NPU */ + default: + return "??"; + } +} + +#define SRC_SRSR_RESET_CAUSE_NUM 16 +const char *reset_cause[SRC_SRSR_RESET_CAUSE_NUM] = { + "POR ", + "JTAG ", + "IPP USER ", + "WDOG1 ", + "WDOG2 ", + "WDOG3 ", + "WDOG4 ", + "WDOG5 ", + "TEMPSENSE ", + "CSU ", + "JTAG_SW ", + "M33_REQ ", + "M33_LOCKUP " + "UNK ", + "UNK ", + "UNK ", +}; + +static void save_reset_cause(void) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr = readl(&src->srsr); + writel(srsr, &src->srsr); /* clear srsr in sec mode */ + + /* Save value to GPR1 to pass to nonsecure */ + writel(srsr, &src->gpr[0]); +} + +static const char *get_reset_cause(u32 *srsr_ret) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr; + u32 i; + + srsr = readl(&src->gpr[0]); + if (srsr_ret) + *srsr_ret = srsr; + + for (i = SRC_SRSR_RESET_CAUSE_NUM; i > 0; i--) { + if (srsr & (1 << (i - 1))) + return reset_cause[i - 1]; + } + + return "unknown reset"; +} + +int print_cpuinfo(void) +{ + u32 cpurev, max_freq; + int minc, maxc; + u32 ssrs_ret; + + cpurev = get_cpu_rev(); + + printf("CPU: i.MX%s rev%d.%d", + get_imx_type((cpurev & 0x1FF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); + + max_freq = get_cpu_speed_grade_hz(); + if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { + printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + } else { + printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + } + + puts("CPU: "); + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + puts("Automotive temperature grade "); + break; + case TEMP_INDUSTRIAL: + puts("Industrial temperature grade "); + break; + case TEMP_EXTCOMMERCIAL: + puts("Extended Consumer temperature grade "); + break; + default: + puts("Consumer temperature grade "); + break; + } + printf("(%dC to %dC)", minc, maxc); + +#if defined(CONFIG_IMX_TMU) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + + if (!ret) + printf(" at %dC", temp); + else + debug(" - invalid sensor data\n"); + } else { + debug(" - invalid sensor device\n"); + } +#endif + puts("\n"); + + printf("Reset cause: %s", get_reset_cause(&ssrs_ret)); + printf("(0x%x)\n", ssrs_ret); + + return 0; +} + +void build_info(void) +{ + u32 fw_version, sha1, res, status; + int ret; + + printf("\nBuildInfo:\n"); + + ret = ahab_get_fw_status(&status, &res); + if (ret) { + printf(" - ELE firmware status failed %d, 0x%x\n", ret, res); + } else if ((status & 0xff) == 1) { + ret = ahab_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf(" - ELE firmware version failed %d, 0x%x\n", ret, res); + } else { + printf(" - ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000ff00)) >> 8, + (fw_version & (0x000000ff)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } + } else { + printf(" - ELE firmware not included\n"); + } + puts("\n"); +} + +int arch_misc_init(void) +{ + build_info(); + return 0; +} + +static int delete_fdt_nodes(void *blob, const char *const nodes_path[], int size_array) +{ + int i = 0; + int rc; + int nodeoff; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path[i]); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path[i], fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path[i]); + } + } + + return 0; +} + +static int disable_npu_nodes(void *blob) +{ + static const char * const nodes_path_npu[] = { + "/ethosu", + "/reserved-memory/ethosu_region@C0000000" + }; + + return delete_fdt_nodes(blob, nodes_path_npu, ARRAY_SIZE(nodes_path_npu)); +} + +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/cpu-thermal/cooling-maps/map0" + }; + + int nodeoff, cnt, i, ret, j; + u32 cooling_dev[6]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 6); + if (cnt < 0) + continue; + + if (cnt != 6) + printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt); + + for (j = 0; j < cnt; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (6 - disabled_cores * 3)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static int disable_cpu_nodes(void *blob, u32 disabled_cores) +{ + u32 i = 0; + int rc; + int nodeoff; + char nodes_path[32]; + + for (i = 1; i <= disabled_cores; i++) { + + sprintf(nodes_path, "/cpus/cpu@%u00", i); + + nodeoff = fdt_path_offset(blob, nodes_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path, fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path); + } + } + + disable_thermal_cpu_nodes(blob, disabled_cores); + + return 0; +} + +struct low_drive_freq_entry { + const char *node_path; + u32 clk; + u32 new_rate; +}; + +static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 new_rate) +{ +#define MAX_ASSIGNED_CLKS 8 + int cnt, j; + u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/ + + cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates", + assignedclks, MAX_ASSIGNED_CLKS); + if (cnt > 0) { + if (cnt <= clk_index) + return -ENOENT; + + if (assignedclks[clk_index] <= new_rate) + return 0; + + assignedclks[clk_index] = new_rate; + for (j = 0; j < cnt; j++) + assignedclks[j] = cpu_to_fdt32(assignedclks[j]); + + return fdt_setprop(fdt, node_off, "assigned-clock-rates", &assignedclks, cnt * sizeof(u32)); + } + + return -ENOENT; +} + +static int low_drive_freq_update(void *blob) +{ + int nodeoff, ret; + int i; + + /* Update kernel dtb clocks for low drive mode */ + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 2, 200000000}, + {"/soc@0/bus@42800000/camera/isi@4ae40000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(blob, table[i].node_path); + if (nodeoff >= 0) { + ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, table[i].new_rate); + if (!ret) + printf("%s freq updated\n", table[i].node_path); + } + } + + return 0; +} + +#ifdef CONFIG_OF_BOARD_FIXUP +#ifndef CONFIG_SPL_BUILD +int board_fix_fdt(void *fdt) +{ + /* Update u-boot dtb clocks for low drive mode */ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + int nodeoff; + int i; + + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(fdt, table[i].node_path); + if (nodeoff >= 0) + low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk, table[i].new_rate); + } + } + + return 0; +} +#endif +#endif + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311()) + disable_cpu_nodes(blob, 1); + + if (is_imx9332() || is_imx9331() || is_imx9312() || is_imx9311()) + disable_npu_nodes(blob); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + low_drive_freq_update(blob); + + return ft_add_optee_node(blob, bd); +} + +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +void get_board_serial(struct tag_serialnr *serialnr) +{ + printf("UID: 0x%x 0x%x 0x%x 0x%x\n", + gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]); + + serialnr->low = gd->arch.uid[0]; + serialnr->high = gd->arch.uid[3]; +} +#endif + +int arch_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Disable wdog */ + init_wdog(); + + clock_init(); + + trdc_early_init(); + + /* Save SRC SRSR to GPR1 and clear it */ + save_reset_cause(); + } + + return 0; +} + +int arch_cpu_init_dm(void) +{ + struct udevice *devp; + int node, ret; + u32 res; + struct sentinel_get_info_data info; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + if (ret) + return ret; + + ret = ahab_get_info(&info, &res); + if (ret) + return ret; + + set_cpu_info(&info); + + return 0; +} + +#ifdef CONFIG_ARCH_EARLY_INIT_R +int arch_early_init_r(void) +{ + struct udevice *devp; + int node, ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + if (ret) { + printf("could not get S400 mu %d\n", ret); + return ret; + } + + return 0; +} +#endif + +int timer_init(void) +{ +#ifdef CONFIG_SPL_BUILD + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; + unsigned long freq = readl(&sctr->cntfid0); + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, + SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_device dev = get_boot_device(); + enum env_location env_loc = ENVL_UNKNOWN; + + if (prio) + return env_loc; + + switch (dev) { +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH + case QSPI_BOOT: + env_loc = ENVL_SPI_FLASH; + break; +#endif +#ifdef CONFIG_ENV_IS_IN_MMC + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + env_loc = ENVL_MMC; + break; +#endif + default: +#if defined(CONFIG_ENV_IS_NOWHERE) + env_loc = ENVL_NOWHERE; +#endif + break; + } + + return env_loc; +} + +int mix_power_init(enum mix_power_domain pd) +{ + enum src_mix_slice_id mix_id; + enum src_mem_slice_id mem_id; + struct src_mix_slice_regs *mix_regs; + struct src_mem_slice_regs *mem_regs; + struct src_general_regs *global_regs; + u32 scr, val; + + switch (pd) { + case MIX_PD_MEDIAMIX: + mix_id = SRC_MIX_MEDIA; + mem_id = SRC_MEM_MEDIA; + scr = BIT(5); + + /* Enable S400 handshake */ + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + + setbits_le32(&s_regs->lp_handshake[0], BIT(13)); + break; + case MIX_PD_MLMIX: + mix_id = SRC_MIX_ML; + mem_id = SRC_MEM_ML; + scr = BIT(4); + break; + case MIX_PD_DDRMIX: + mix_id = SRC_MIX_DDRMIX; + mem_id = SRC_MEM_DDRMIX; + scr = BIT(6); + break; + default: + return -EINVAL; + } + + mix_regs = (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (mix_id + 1)); + mem_regs = (struct src_mem_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x3800 + 0x400 * mem_id); + global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + + /* Allow NS to set it */ + setbits_le32(&mix_regs->authen_ctrl, BIT(9)); + + clrsetbits_le32(&mix_regs->psw_ack_ctrl[0], BIT(28), BIT(29)); + + /* mix reset will be held until boot core write this bit to 1 */ + setbits_le32(&global_regs->scr, scr); + + /* Enable mem in Low power auto sequence */ + setbits_le32(&mem_regs->mem_ctrl, BIT(2)); + + /* Set the power down state */ + val = readl(&mix_regs->func_stat); + if (val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT) { + /* The mix is default power off, power down it to make PDN_SFT bit + * aligned with FUNC STAT + */ + setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + + /* Since PSW_STAT is 1, can't be used for power off status (SW_CTRL BIT31 set)) */ + /* Check the MEM STAT change to ensure SSAR is completed */ + while (!(val & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT)) { + val = readl(&mix_regs->func_stat); + } + + /* wait few ipg clock cycles to ensure FSM done and power off status is correct */ + /* About 5 cycles at 24Mhz, 1us is enough */ + udelay(1); + } else { + /* The mix is default power on, Do mix power cycle */ + setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + while (!(val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT)) { + val = readl(&mix_regs->func_stat); + } + } + + /* power on */ + clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31)); + val = readl(&mix_regs->func_stat); + while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT) { + val = readl(&mix_regs->func_stat); + } + + return 0; +} + +void disable_isolation(void) +{ + struct src_general_regs *global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + /* clear isolation for usbphy, dsi, csi*/ + writel(0x0, &global_regs->sp_iso_ctrl); +} + +void soc_power_init(void) +{ + mix_power_init(MIX_PD_MEDIAMIX); + mix_power_init(MIX_PD_MLMIX); + + disable_isolation(); +} + +bool m33_is_rom_kicked(void) +{ + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + + if (!(readl(&s_regs->m33_cfg) & BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK)) + return true; + + return false; +} + +int m33_prepare(void) +{ + struct src_mix_slice_regs *mix_regs = + (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1)); + struct src_general_regs *global_regs = + (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + u32 val; + + /* Allow NS to set it */ + setbits_le32(&mix_regs->authen_ctrl, BIT(9)); + + if (m33_is_rom_kicked()) + return -EPERM; + + /* Release reset of M33 */ + setbits_le32(&global_regs->scr, BIT(0)); + + /* Check the reset released in M33 MIX func stat */ + val = readl(&mix_regs->func_stat); + while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) { + val = readl(&mix_regs->func_stat); + } + + /* Because CPUWAIT is default set, so M33 won't run, Clear it when kick M33 */ + /* Release Sentinel TROUT */ + ahab_release_m33_trout(); + + /* Mask WDOG1 IRQ from A55, we use it for M33 reset */ + setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6)); + + /* Turn on WDOG1 clock */ + ccm_lpcg_on(CCGR_WDG1, 1); + + /* Set sentinel LP handshake for M33 reset */ + setbits_le32(&s_regs->lp_handshake[0], BIT(6)); + + /* Clear M33 TCM for ECC */ + memset((void *)(ulong)0x201e0000, 0, 0x40000); + + return 0; +} diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c new file mode 100644 index 0000000000..bb137a7912 --- /dev/null +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <div64.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/mu_hal.h> + +#define DID_NUM 16 +#define MBC_MAX_NUM 4 +#define MRC_MAX_NUM 2 +#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF) +#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F) + +struct mbc_mem_dom { + u32 mem_glbcfg[4]; + u32 nse_blk_index; + u32 nse_blk_set; + u32 nse_blk_clr; + u32 nsr_blk_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + u32 mem0_blk_cfg_w[64]; + u32 mem0_blk_nse_w[16]; + u32 mem1_blk_cfg_w[8]; + u32 mem1_blk_nse_w[2]; + u32 mem2_blk_cfg_w[8]; + u32 mem2_blk_nse_w[2]; + u32 mem3_blk_cfg_w[8]; + u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ + u32 reserved[2]; +}; + +struct mrc_rgn_dom { + u32 mrc_glbcfg[4]; + u32 nse_rgn_indirect; + u32 nse_rgn_set; + u32 nse_rgn_clr; + u32 nse_rgn_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + u32 rgn_nse; + u32 reserved2[15]; +}; + +struct mda_inst { + u32 mda_w[8]; +}; + +struct trdc_mgr { + u32 trdc_cr; + u32 res0[59]; + u32 trdc_hwcfg0; + u32 trdc_hwcfg1; + u32 res1[450]; + struct mda_inst mda[8]; + u32 res2[15808]; +}; + +struct trdc_mbc { + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc { + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + + +int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids, u8 did, u8 pe, u8 pidm, u8 pid) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + u32 val = readl(mda_w); + + if (val & BIT(29)) /* non-cpu */ + return -EINVAL; + + val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) | ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) | (did & 0xf); + + writel(val, mda_w); + + return 0; +} + +int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, bool did_bypass, u8 sa, u8 pa, u8 did) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg]; + u32 val = readl(mda_w); + + if (!(val & BIT(29))) /* cpu */ + return -EINVAL; + + val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf); + if (did_bypass) + val |= BIT(8); + + writel(val, mda_w); + + return 0; +} + +static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + + if (mbc_x >= mbc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_x; +} + +static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0); + + if (mrc_x >= mrc_num) + return 0; + + return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x; +} + +int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + debug("mbc 0x%lx\n", (ulong)mbc_dom); + + writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]); + + return 0; +} + +int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w, *nse_w; + u32 index, offset, val; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + debug("mbc 0x%lx\n", (ulong)mbc_dom); + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = readl((void __iomem *)cfg_w); + + val &= ~(0xFU << offset); + + /* MBC0-3 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MBC0_MEMN_GLBAC0 + */ + if (sec_access) { + val |= ((0x0 | (glbac_id & 0x7)) << offset); + writel(val, (void __iomem *)cfg_w); + } else { + val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */ + writel(val, (void __iomem *)cfg_w); + } + + return 0; +} + +int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + debug("mrc_dom 0x%lx\n", (ulong)mrc_dom); + + writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]); + + return 0; +} + +int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + u32 *desc_w; + u32 start, end; + u32 i, free = 8;; + bool vld, hit = false; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + mrc_dom = &mrc_base->mrc_dom[dom_x]; + + addr_start &= ~0x3fff; + addr_end &= ~0x3fff; + + debug("mrc_dom 0x%lx\n", (ulong)mrc_dom); + + for (i = 0; i < 8; i++) { + desc_w = &mrc_dom->rgn_desc_words[i][0]; + + debug("desc_w 0x%lx\n", (ulong)desc_w); + + start = readl((void __iomem *)desc_w) & (~0x3fff); + end = readl((void __iomem *)(desc_w + 1)); + vld = end & 0x1; + end = end & (~0x3fff); + + if (start == 0 && end == 0 && !vld && free >= 8) + free = i; + + /* Check all the region descriptors, even overlap */ + if (addr_start >= end || addr_end <= start || !vld) + continue; + + /* MRC0,1 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MRCx_MEMN_GLBAC0 + */ + if (sec_access) { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1)); + } + + if (addr_start >= start && addr_end <= end) + hit = true; + } + + if (!hit) { + if (free >= 8) + return -EFAULT; + + desc_w = &mrc_dom->rgn_desc_words[free][0]; + + debug("free desc_w 0x%lx\n", (ulong)desc_w); + debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1); + + if (sec_access) { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel(addr_end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w); + writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1)); + } + } + + return 0; +} + +bool trdc_mrc_enabled(ulong trdc_base) +{ + return (!!(readl((void __iomem *)trdc_base) & 0x8000)); +} + +bool trdc_mbc_enabled(ulong trdc_base) +{ + return (!!(readl((void __iomem *)trdc_base) & 0x4000)); +} + +int release_rdc(u8 xrdc) +{ + ulong s_mu_base = 0x47520000UL; + struct sentinel_msg msg; + int ret; + u32 rdc_id; + + switch (xrdc) { + case 0: + rdc_id = 0x74; + break; + case 1: + rdc_id = 0x78; + break; + case 2: + rdc_id = 0x82; + break; + case 3: + rdc_id = 0x86; + break; + default: + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = ELE_RELEASE_RDC_REQ; + msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */ + + mu_hal_init(s_mu_base); + mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); + mu_hal_sendmsg(s_mu_base, 1, msg.data[0]); + + ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); + if (!ret) { + ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); + if (!ret) { + if ((msg.data[0] & 0xff) == 0xd6) + return 0; + } + + return -EIO; + } + + return ret; +} + +void trdc_early_init(void) +{ + int ret = 0, i; + ret |= release_rdc(0); + ret |= release_rdc(2); + ret |= release_rdc(1); + ret |= release_rdc(3); + + if (!ret) { + /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */ + trdc_mbc_set_control(0x49010000, 3, 0, 0x7700); + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0); + } + + for (i = 0; i < 40; i++) { + trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0); + } + } +} + +void trdc_init(void) +{ + /* TRDC mega */ + if (trdc_mrc_enabled(0x49010000)) { + + /* DDR */ + trdc_mrc_set_control(0x49010000, 0, 0, 0x7777); + + /* S400*/ + trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0); + + /* MTR */ + trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0); + + /* M33 */ + trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0); + + /* A55*/ + trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0); + + /* For USDHC1 to DDR, USDHC1 is default force to non-secure */ + trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0); + + /* For USDHC2 to DDR, USDHC2 is default force to non-secure */ + trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0); + + /* eDMA */ + trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0); + + /*CoreSight, TestPort*/ + trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0); + + /* DAP */ + trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0); + + /*SoC masters */ + trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0); + + /*USB*/ + trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0); + + } +} + +#if DEBUG +int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + + if (mbc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + printf("mbc_dom %u glbac %u: 0x%x\n", mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id])); + + return 0; +} + +int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word) +{ + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w; + + if (mbc_base == 0) + return -EINVAL; + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[word]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[word]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[word]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[word]; + break; + default: + return -EINVAL; + }; + + printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n", mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w)); + + return 0; +} + +int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id) +{ + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + struct mrc_rgn_dom *mrc_dom; + + if (mrc_base == 0 || glbac_id >= 8) + return -EINVAL; + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + printf("mrc_dom %u glbac %u: 0x%x\n", mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id])); + + return 0; +} + +void trdc_dump(void) +{ + u32 i; + printf("TRDC AONMIX MBC\n"); + + trdc_mbc_control_dump(0x44270000, 0, 0); + trdc_mbc_control_dump(0x44270000, 1, 0); + + for (i = 0; i < 11; i++) { + trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i); + } + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i); + } + + for (i = 0; i < 4; i++) { + trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i); + } + for (i = 0; i < 4; i++) { + trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i); + } + + printf("TRDC WAKEUP MBC\n"); + + trdc_mbc_control_dump(0x42460000, 0, 0); + trdc_mbc_control_dump(0x42460000, 1, 0); + + for (i = 0; i < 15; i++) { + trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i); + } + trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0); + trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0); + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i); + } + trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0); + trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0); + trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0); + + printf("TRDC NICMIX MBC\n"); + + trdc_mbc_control_dump(0x49010000, 0, 0); + trdc_mbc_control_dump(0x49010000, 1, 0); + trdc_mbc_control_dump(0x49010000, 2, 0); + trdc_mbc_control_dump(0x49010000, 3, 0); + + for (i = 0; i < 7; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i); + } + + for (i = 0; i < 6; i++) { + trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i); + } + + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i); + } + + for (i = 0; i < 1; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i); + } + + for (i = 0; i < 3; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i); + } + + for (i = 0; i < 3; i++) { + trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i); + } + + for (i = 0; i < 2; i++) { + trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i); + } + + for (i = 0; i < 5; i++) { + trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i); + } +} +#endif diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 7012ae9d7b..0c2987dece 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -10,6 +10,10 @@ #include <asm/mach-imx/boot_mode.h> #include <env.h> +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + __weak int board_mmc_get_env_dev(int devno) { return devno; diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index c24d8279ed..a171e7b54d 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2022 NXP */ #include <common.h> @@ -10,6 +10,11 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/module_fuse.h> #include <linux/errno.h> +#include <command.h> +#include <hexdump.h> +#include <dm.h> +#include <malloc.h> +#include <rng.h> static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) @@ -300,6 +305,48 @@ add_status: } } + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) { + /*Random number generation through RNG driver*/ + struct udevice *dev; + void *buf; + char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; + int ret = 0; + int nodeoff = fdt_node_offset_by_compatible(blob, -1, "fsl,imx28-dcp"); + + if (nodeoff < 0) { + printf("node to update the SoC serial number is not found.\n"); + return nodeoff; + } + rc = uclass_get_device(UCLASS_RNG, 0, &dev); + if (rc || !dev) { + printf("No RNG device\n"); + return rc; + } + + buf = malloc(16); + if (!buf) { + printf("Out of memory\n"); + return -ENOMEM; + } + + for (int i = 0; i < 2; i++) { + ret = dm_rng_read(dev, buf, 16); + if (ret) { + printf("Reading RNG failed\n"); + goto err; + } + + ret = fdt_setprop(blob, nodeoff, keys[i], buf, 16); + if (ret < 0) { + printf("WARNING: could not set %s key handle %s.\n", keys[i], fdt_strerror(ret)); + goto err; + } + } +err: + free(buf); + return ret; + } + return 0; } #endif diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 3e538754d9..9bf16119c2 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -31,6 +31,8 @@ #include <hang.h> #include <cpu_func.h> #include <env.h> +#include<dm/device-internal.h> +#include<dm/lists.h> DECLARE_GLOBAL_DATA_PTR; @@ -1005,6 +1007,20 @@ int arch_misc_init(void) if (ret) printf("Failed to initialize caam_jr: %d\n", ret); } + + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) { + struct udevice *dev; + int ret; + + ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL); + if (ret) + printf("Couldn't bind dcp rng driver (%d)\n", ret); + + ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev); + if (ret) + printf("Failed to initialize dcp rng: %d\n", ret); + } + setup_serial_number(); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index ea709d15a5..fe33a7b611 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -21,6 +21,8 @@ #include <g_dnl.h> #include <linux/libfdt.h> #include <mmc.h> +#include <image.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -148,7 +150,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9) /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { @@ -184,7 +186,7 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_USB_GADGET int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { - put_unaligned(0x0151, &dev->idProduct); + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct); return 0; } @@ -314,7 +316,10 @@ ulong board_spl_fit_size_align(ulong size) */ size = ALIGN(size, 0x1000); - size += CONFIG_CSF_SIZE; + size += 2 * CONFIG_CSF_SIZE; + + if (size > CONFIG_SYS_BOOTM_LEN) + panic("spl: ERROR: image too big\n"); return size; } @@ -347,6 +352,42 @@ int dram_init_banksize(void) } #endif +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) && IS_ENABLED(CONFIG_IMX_HAB) && \ + !IS_ENABLED(CONFIG_SPL_FIT_SIGNATURE) +static int spl_verify_fit_hash(const void *fit) +{ + unsigned long size; + u8 value[SHA256_SUM_LEN]; + int value_len; + ulong fit_hash; + +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { + fit_hash = roundup((unsigned long)&_end + + fdt_totalsize(gd->fdt_blob), 4) + 0x18000; + } +#else + fit_hash = (unsigned long)&_end + 0x18000; +#endif + + size = fdt_totalsize(fit); + + if (calculate_hash(fit, size, "sha256", value, &value_len)) { + printf("Unsupported hash algorithm\n"); + return -1; + } + + if (value_len != SHA256_SUM_LEN) { + printf("Bad hash value len\n"); + return -1; + } else if (memcmp(value, (const void *)fit_hash, value_len) != 0) { + printf("Bad hash value\n"); + return -1; + } + + return 0; +} + /* * read the address where the IVT header must sit * from IVT image header, loaded from SPL into @@ -361,6 +402,30 @@ void *spl_load_simple_fit_fix_load(const void *fit) unsigned long size; u8 *tmp = (u8 *)fit; + if (IS_ENABLED(CONFIG_IMX_HAB)) { + if (IS_ENABLED(CONFIG_IMX_SPL_FIT_FDT_SIGNATURE)) { + u32 offset = ALIGN(fdt_totalsize(fit), 0x1000); + + if (imx_hab_authenticate_image((uintptr_t)fit, + offset + 2 * CSF_PAD_SIZE, + offset + CSF_PAD_SIZE)) { +#ifdef CONFIG_ANDROID_SUPPORT + printf("spl: ERROR: FIT FDT authentication unsuccessful\n"); + return NULL; +#else + panic("spl: ERROR: FIT FDT authentication unsuccessful\n"); +#endif + } + } else { + int ret = spl_verify_fit_hash(fit); + + if (ret && imx_hab_is_enabled()) + panic("spl: ERROR: FIT hash verify unsuccessful\n"); + + debug("spl_verify_fit_hash %d\n", ret); + } + } + offset = ALIGN(fdt_totalsize(fit), 0x1000); size = ALIGN(fdt_totalsize(fit), 4); size = board_spl_fit_size_align(size); @@ -379,6 +444,7 @@ void *spl_load_simple_fit_fix_load(const void *fit) return (void *)new; } +#endif #if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN) int board_handle_rdc_config(void *fdt_addr, const char *config_name, void *dst_addr) diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index ff4a87132b..c0e8bed958 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -263,7 +263,7 @@ static u32 img_header_size(void) static int img_info_size(void *img_hdr) { #ifdef CONFIG_SPL_LOAD_FIT - return fit_get_size(img_hdr); + return board_spl_fit_size_align(fit_get_size(img_hdr)); #elif defined CONFIG_SPL_LOAD_IMX_CONTAINER struct container_hdr *container = img_hdr; @@ -408,10 +408,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, { volatile gd_t *pgd = gd; int ret; - u32 boot; + u32 boot, bstage; ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, ((uintptr_t)&boot) ^ QUERY_BT_DEV); + ret |= g_rom_api->query_boot_infor(QUERY_BT_STAGE, &bstage, + ((uintptr_t)&bstage) ^ QUERY_BT_STAGE); set_gd(pgd); if (ret != ROM_API_OKAY) { @@ -419,6 +421,25 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, return -1; } + printf("Boot Stage: "); + + switch (bstage) { + case BT_STAGE_PRIMARY: + printf("Primary boot\n"); + break; + case BT_STAGE_SECONDARY: + printf("Secondary boot\n"); + break; + case BT_STAGE_RECOVERY: + printf("Recovery boot\n"); + break; + case BT_STAGE_USB: + printf("USB boot\n"); + break; + default: + printf("Unknow (0x%x)\n", bstage); + } + if (is_boot_from_stream_device(boot)) return spl_romapi_load_image_stream(spl_image, bootdev); |