diff options
Diffstat (limited to 'board/toradex/colibri_imx6/colibri_imx6.c')
| -rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 1fa0bf6252..8bf4046e7d 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1062,10 +1062,14 @@ static void spl_dram_init(void) case TEMP_COMMERCIAL: case TEMP_EXTCOMMERCIAL: if (is_cpu_type(MXC_CPU_MX6DL)) { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n"); +#endif ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); +#endif ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1073,9 +1077,14 @@ static void spl_dram_init(void) case TEMP_AUTOMOTIVE: default: if (is_cpu_type(MXC_CPU_MX6DL)) { +#ifndef CONFIG_SPL_SILENT_CONSOLE + puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n"); +#endif ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { +#ifndef CONFIG_SPL_SILENT_CONSOLE puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); +#endif ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; |