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path: root/board/toradex/verdin-imx8mp/lpddr4_timing.c
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Diffstat (limited to 'board/toradex/verdin-imx8mp/lpddr4_timing.c')
-rw-r--r--board/toradex/verdin-imx8mp/lpddr4_timing.c77
1 files changed, 39 insertions, 38 deletions
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index 4bccd800ff..39fcccfb41 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -21,9 +21,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
- { 0x3d400070, 0x61027f10 },
- { 0x3d400074, 0x7b0 },
+ { 0x3d400064, 0x7a017c },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
@@ -31,15 +31,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x807bf },
+ { 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x120 },
+ { 0x3d400138, 0x184 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
@@ -53,15 +53,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x9121c1c },
- { 0x3d400200, 0x18 },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
+ { 0x3d400200, 0x17 },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
- { 0x3d40021c, 0xf07 },
+ { 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -77,7 +78,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402020, 0x1001 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc001c },
+ { 0x3d402064, 0xc0026 },
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
@@ -89,20 +90,20 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
- { 0x3d402138, 0x1d },
+ { 0x3d402138, 0x27 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x30007 },
+ { 0x3d403064, 0x3000a },
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
@@ -114,16 +115,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x8 },
+ { 0x3d403138, 0xa },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -1702,15 +1703,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x7d },
+ { 0x2000b, 0x465 },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
{ 0x2000e, 0x2c },
- { 0x12000b, 0xc },
+ { 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
{ 0x12000d, 0xfa },
{ 0x12000e, 0x10 },
- { 0x22000b, 0x3 },
+ { 0x22000b, 0x1c },
{ 0x22000c, 0x6 },
{ 0x22000d, 0x3e },
{ 0x22000e, 0x10 },
@@ -1843,9 +1844,9 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
- { 0x3d400070, 0x61027f10 },
- { 0x3d400074, 0x7b0 },
+ { 0x3d400064, 0x7a017c },
+ { 0x3d400070, 0x7027f90 },
+ { 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
@@ -1853,15 +1854,15 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a },
- { 0x3d400104, 0x807bf },
+ { 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x120 },
+ { 0x3d400138, 0x184 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
@@ -1875,9 +1876,10 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x9121c1c },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
@@ -1899,7 +1901,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d402020, 0x1001 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc001c },
+ { 0x3d402064, 0xc0026 },
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
@@ -1911,20 +1913,20 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
- { 0x3d402138, 0x1d },
+ { 0x3d402138, 0x27 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x30007 },
+ { 0x3d403064, 0x3000a },
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
@@ -1936,16 +1938,16 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x8 },
+ { 0x3d403138, 0xa },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -2081,7 +2083,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-30 11:32:27 +0000