diff options
Diffstat (limited to 'drivers/net/fec_mxc.c')
| -rw-r--r-- | drivers/net/fec_mxc.c | 473 |
1 files changed, 318 insertions, 155 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 84021ea5be..3304fddc69 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -9,20 +9,22 @@ */ #include <common.h> +#include <dm.h> #include <malloc.h> #include <memalign.h> +#include <miiphy.h> #include <net.h> #include <netdev.h> -#include <miiphy.h> #include "fec_mxc.h" -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/imx-common/sys_proto.h> #include <asm/io.h> #include <linux/errno.h> #include <linux/compiler.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/sys_proto.h> + DECLARE_GLOBAL_DATA_PTR; /* @@ -79,11 +81,9 @@ static void swap_packet(uint32_t *packet, int length) } #endif -/* - * MII-interface related functions - */ -static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, - uint8_t regAddr) +/* MII-interface related functions */ +static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, + uint8_t regaddr) { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ @@ -95,15 +95,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, * programming the FEC's MII data register. */ writel(FEC_IEVENT_MII, ð->ievent); - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + reg = regaddr << FEC_MII_DATA_RA_SHIFT; + phy = phyaddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg, ð->mii_data); - /* - * wait for the related interrupt - */ + /* wait for the related interrupt */ start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { @@ -112,17 +110,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, } } - /* - * clear mii interrupt bit - */ + /* clear mii interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - /* - * it's now safe to read the PHY's register - */ + /* it's now safe to read the PHY's register */ val = (unsigned short)readl(ð->mii_data); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, - regAddr, val); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, + regaddr, val); return val; } @@ -153,22 +147,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } -static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, - uint8_t regAddr, uint16_t data) +static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, + uint8_t regaddr, uint16_t data) { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ uint32_t start; - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + reg = regaddr << FEC_MII_DATA_RA_SHIFT; + phy = phyaddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); - /* - * wait for the MII interrupt - */ + /* wait for the MII interrupt */ start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { @@ -177,26 +169,24 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, } } - /* - * clear MII interrupt bit - */ + /* clear MII interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, - regAddr, data); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, + regaddr, data); return 0; } -static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, - int regAddr) +static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, + int regaddr) { - return fec_mdio_read(bus->priv, phyAddr, regAddr); + return fec_mdio_read(bus->priv, phyaddr, regaddr); } -static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, - int regAddr, u16 data) +static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, + int regaddr, u16 data) { - return fec_mdio_write(bus->priv, phyAddr, regAddr, data); + return fec_mdio_write(bus->priv, phyaddr, regaddr, data); } #ifndef CONFIG_PHYLIB @@ -217,14 +207,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); - /* - * Set the auto-negotiation advertisement register bits - */ + /* Set the auto-negotiation advertisement register bits */ fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF | PHY_ANLPAR_PSB_802_3); + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); fec_mdio_write(eth, fec->phy_id, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); + BMCR_ANENABLE | BMCR_ANRESTART); if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id); @@ -241,9 +229,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) struct fec_priv *fec = (struct fec_priv *)dev->priv; struct ethernet_regs *eth = fec->bus->priv; - /* - * Wait for AN completion - */ + /* Wait for AN completion */ start = get_timer(0); do { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { @@ -254,7 +240,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); if (status < 0) { printf("%s: Autonegotiation failed. status: %d\n", - dev->name, status); + dev->name, status); return -1; } } while (!(status & BMSR_LSTATUS)); @@ -351,65 +337,63 @@ static void fec_tbd_init(struct fec_priv *fec) /** * Mark the given read buffer descriptor as free * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 - * @param[in] pRbd buffer descriptor to mark free again + * @param[in] prbd buffer descriptor to mark free again */ -static void fec_rbd_clean(int last, struct fec_bd *pRbd) +static void fec_rbd_clean(int last, struct fec_bd *prbd) { unsigned short flags = FEC_RBD_EMPTY; if (last) flags |= FEC_RBD_WRAP; - writew(flags, &pRbd->status); - writew(0, &pRbd->data_length); + writew(flags, &prbd->status); + writew(0, &prbd->data_length); } -static int fec_get_hwaddr(struct eth_device *dev, int dev_id, - unsigned char *mac) +static int fec_get_hwaddr(int dev_id, unsigned char *mac) { imx_get_mac_from_fuse(dev_id, mac); return !is_valid_ethaddr(mac); } +#ifdef CONFIG_DM_ETH +static int fecmxc_set_hwaddr(struct udevice *dev) +#else static int fec_set_hwaddr(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uchar *mac = pdata->enetaddr; +#else uchar *mac = dev->enetaddr; struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif writel(0, &fec->eth->iaddr1); writel(0, &fec->eth->iaddr2); writel(0, &fec->eth->gaddr1); writel(0, &fec->eth->gaddr2); - /* - * Set physical address - */ + /* Set physical address */ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], - &fec->eth->paddr1); + &fec->eth->paddr1); writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); return 0; } -/* - * Do initial configuration of the FEC registers - */ +/* Do initial configuration of the FEC registers */ static void fec_reg_setup(struct fec_priv *fec) { uint32_t rcntrl; - /* - * Set interrupt mask register - */ + /* Set interrupt mask register */ writel(0x00000000, &fec->eth->imask); - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ + /* Clear FEC-Lite interrupt event register(IEVENT) */ writel(0xffffffff, &fec->eth->ievent); - - /* - * Set FEC-Lite receive control register(R_CNTRL): - */ + /* Set FEC-Lite receive control register(R_CNTRL): */ /* Start with frame length = 1518, common for all modes. */ rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; @@ -427,9 +411,17 @@ static void fec_reg_setup(struct fec_priv *fec) * Start the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static int fec_open(struct udevice *dev) +#else static int fec_open(struct eth_device *edev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)edev->priv; +#endif int speed; uint32_t addr, size; int i; @@ -453,22 +445,19 @@ static int fec_open(struct eth_device *edev) #ifdef FEC_QUIRK_ENET_MAC /* Enable ENET HW endian SWAP */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, - &fec->eth->ecntrl); + &fec->eth->ecntrl); /* Enable ENET store and forward mode */ writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, - &fec->eth->x_wmrk); + &fec->eth->x_wmrk); #endif - /* - * Enable FEC-Lite controller - */ + /* Enable FEC-Lite controller */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, - &fec->eth->ecntrl); + &fec->eth->ecntrl); + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) udelay(100); - /* - * setup the MII gasket for RMII mode - */ + /* setup the MII gasket for RMII mode */ /* disable the gasket */ writew(0, &fec->eth->miigsk_enr); @@ -526,27 +515,35 @@ static int fec_open(struct eth_device *edev) #endif debug("%s:Speed=%i\n", __func__, speed); - /* - * Enable SmartDMA receive task - */ + /* Enable SmartDMA receive task */ fec_rx_task_enable(fec); udelay(100000); return 0; } -static int fec_init(struct eth_device *dev, bd_t* bd) +#ifdef CONFIG_DM_ETH +static int fecmxc_init(struct udevice *dev) +#else +static int fec_init(struct eth_device *dev, bd_t *bd) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; int i; /* Initialize MAC address */ +#ifdef CONFIG_DM_ETH + fecmxc_set_hwaddr(dev); +#else fec_set_hwaddr(dev); +#endif - /* - * Setup transmit descriptors, there are two in total. - */ + /* Setup transmit descriptors, there are two in total. */ fec_tbd_init(fec); /* Setup receive descriptors. */ @@ -557,18 +554,14 @@ static int fec_init(struct eth_device *dev, bd_t* bd) if (fec->xcv_type != SEVENWIRE) fec_mii_setspeed(fec->bus->priv); - /* - * Set Opcode/Pause Duration Register - */ + /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ writel(0x2, &fec->eth->x_wmrk); - /* - * Set multicast address filter - */ + + /* Set multicast address filter */ writel(0x00000000, &fec->eth->gaddr1); writel(0x00000000, &fec->eth->gaddr2); - /* Do not access reserved register for i.MX6UL */ if (!is_mx6ul()) { /* clear MIB RAM */ @@ -596,27 +589,29 @@ static int fec_init(struct eth_device *dev, bd_t* bd) * Halt the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static void fecmxc_halt(struct udevice *dev) +#else static void fec_halt(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif int counter = 0xffff; - /* - * issue graceful stop command to the FEC transmitter if necessary - */ + /* issue graceful stop command to the FEC transmitter if necessary */ writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); debug("eth_halt: wait for stop regs\n"); - /* - * wait for graceful stop to register - */ + /* wait for graceful stop to register */ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) udelay(1); - /* - * Disable SmartDMA tasks - */ + /* Disable SmartDMA tasks */ fec_tx_task_disable(fec); fec_rx_task_disable(fec); @@ -625,7 +620,7 @@ static void fec_halt(struct eth_device *dev) * Note: this will also reset the BD index counter! */ writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, - &fec->eth->ecntrl); + &fec->eth->ecntrl); fec->rbd_index = 0; fec->tbd_index = 0; debug("eth_halt: done\n"); @@ -638,7 +633,11 @@ static void fec_halt(struct eth_device *dev) * @param[in] length Data count in bytes * @return 0 on success */ +#ifdef CONFIG_DM_ETH +static int fecmxc_send(struct udevice *dev, void *packet, int length) +#else static int fec_send(struct eth_device *dev, void *packet, int length) +#endif { unsigned int status; uint32_t size, end; @@ -650,7 +649,11 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * This routine transmits one frame. This routine only accepts * 6-byte Ethernet addresses. */ +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif /* * Check for valid length of data. @@ -720,9 +723,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) */ readl(addr + size - 4); - /* - * Enable SmartDMA transmit task - */ + /* Enable SmartDMA transmit task */ fec_tx_task_enable(fec); /* @@ -767,8 +768,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length) out: debug("fec_send: status 0x%x index %d ret %i\n", - readw(&fec->tbd_base[fec->tbd_index].status), - fec->tbd_index, ret); + readw(&fec->tbd_base[fec->tbd_index].status), + fec->tbd_index, ret); /* for next transmission use the other buffer */ if (fec->tbd_index) fec->tbd_index = 0; @@ -783,9 +784,17 @@ out: * @param[in] dev Our ethernet device to handle * @return Length of packet read */ +#ifdef CONFIG_DM_ETH +static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) +#else static int fec_recv(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; unsigned long ievent; int frame_length, len = 0; @@ -794,30 +803,41 @@ static int fec_recv(struct eth_device *dev) int i; ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); - /* - * Check if any critical events have happened - */ + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); + fecmxc_init(dev); +#else fec_halt(dev); fec_init(dev, fec->bd); +#endif printf("some error: 0x%08lx\n", ievent); return 0; } if (ievent & FEC_IEVENT_HBERR) { /* Heartbeat error */ writel(0x00000001 | readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); } if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ if (readl(&fec->eth->x_cntrl) & 0x00000001) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); +#else fec_halt(dev); +#endif writel(~0x00000001 & readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); +#ifdef CONFIG_DM_ETH + fecmxc_init(dev); +#else fec_init(dev, fec->bd); +#endif } } @@ -844,22 +864,16 @@ static int fec_recv(struct eth_device *dev) if (!(bd_status & FEC_RBD_EMPTY)) { if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && - ((readw(&rbd->data_length) - 4) > 14)) { - /* - * Get buffer address and size - */ + ((readw(&rbd->data_length) - 4) > 14)) { + /* Get buffer address and size */ addr = readl(&rbd->data_pointer); frame_length = readw(&rbd->data_length) - 4; - /* - * Invalidate data cache over the buffer - */ + /* Invalidate data cache over the buffer */ end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); addr &= ~(ARCH_DMA_MINALIGN - 1); invalidate_dcache_range(addr, end); - /* - * Fill the buffer and pass it to upper layers - */ + /* Fill the buffer and pass it to upper layers */ #ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)addr, frame_length); #endif @@ -887,7 +901,7 @@ static int fec_recv(struct eth_device *dev) &fec->rbd_base[i]); } flush_dcache_range(addr, - addr + ARCH_DMA_MINALIGN); + addr + ARCH_DMA_MINALIGN); } fec_rx_task_enable(fec); @@ -971,6 +985,33 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) +{ + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return NULL; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + bus->priv = eth; + fec_set_dev_name(bus->name, dev_id); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return NULL; + } + fec_mii_setspeed(eth); + return bus; +} + +#ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -1045,7 +1086,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, #endif eth_register(edev); - if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { + if (fec_get_hwaddr(dev_id, ethaddr) == 0) { debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); if (!getenv("ethaddr")) @@ -1062,32 +1103,6 @@ err1: return ret; } -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) -{ - struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; - struct mii_dev *bus; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return NULL; - } - bus->read = fec_phy_read; - bus->write = fec_phy_write; - bus->priv = eth; - fec_set_dev_name(bus->name, dev_id); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return NULL; - } - fec_mii_setspeed(eth); - return bus; -} - int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) { uint32_t base_mii; @@ -1147,3 +1162,151 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) return 0; } #endif + +#else + +static int fecmxc_read_rom_hwaddr(struct udevice *dev) +{ + struct fec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); +} + +static const struct eth_ops fecmxc_ops = { + .start = fecmxc_init, + .send = fecmxc_send, + .recv = fecmxc_recv, + .stop = fecmxc_halt, + .write_hwaddr = fecmxc_set_hwaddr, + .read_rom_hwaddr = fecmxc_read_rom_hwaddr, +}; + +static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff; + +#ifdef CONFIG_PHYLIB + mask = 1 << CONFIG_FEC_MXC_PHYADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static int fecmxc_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + struct mii_dev *bus = NULL; + int dev_id = -1; + uint32_t start; + int ret; + + ret = fec_alloc_descs(priv); + if (ret) + return ret; + + bus = fec_get_miibus((uint32_t)priv->eth, dev_id); + if (!bus) + goto err_mii; + + priv->bus = bus; + priv->xcv_type = CONFIG_FEC_XCV_TYPE; + priv->interface = pdata->phy_interface; + ret = fec_phy_init(priv, dev); + if (ret) + goto err_phy; + + /* Reset chip. */ + writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, + &priv->eth->ecntrl); + start = get_timer(0); + while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("FEC MXC: Timeout reseting chip\n"); + goto err_timeout; + } + udelay(10); + } + + fec_reg_setup(priv); + fec_set_dev_name((char *)dev->name, dev_id); + priv->dev_id = (dev_id == -1) ? 0 : dev_id; + + return 0; + +err_timeout: + free(priv->phydev); +err_phy: + mdio_unregister(bus); + free(bus); +err_mii: + fec_free_descs(priv); + return ret; +} + +static int fecmxc_remove(struct udevice *dev) +{ + struct fec_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + fec_free_descs(priv); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static int fecmxc_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->eth = (struct ethernet_regs *)pdata->iobase; + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + /* TODO + * Need to get the reset-gpio and related properties from DT + * and implemet the enet reset code on .probe call + */ + + return 0; +} + +static const struct udevice_id fecmxc_ids[] = { + { .compatible = "fsl,imx6q-fec" }, + { } +}; + +U_BOOT_DRIVER(fecmxc_gem) = { + .name = "fecmxc", + .id = UCLASS_ETH, + .of_match = fecmxc_ids, + .ofdata_to_platdata = fecmxc_ofdata_to_platdata, + .probe = fecmxc_probe, + .remove = fecmxc_remove, + .ops = &fecmxc_ops, + .priv_auto_alloc_size = sizeof(struct fec_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; +#endif |