diff options
Diffstat (limited to 'drivers/video')
-rw-r--r-- | drivers/video/cfb_console.c | 2 | ||||
-rw-r--r-- | drivers/video/da8xx-fb.c | 5 | ||||
-rw-r--r-- | drivers/video/exynos/exynos_dp.c | 12 | ||||
-rw-r--r-- | drivers/video/rockchip/rk3288_mipi.c | 2 | ||||
-rw-r--r-- | drivers/video/rockchip/rk3399_mipi.c | 2 | ||||
-rw-r--r-- | drivers/video/stb_truetype.h | 2 | ||||
-rw-r--r-- | drivers/video/stm32/stm32_ltdc.c | 117 |
7 files changed, 95 insertions, 47 deletions
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 0b258970620..5b7795dd44d 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -768,7 +768,7 @@ static void parse_putc(const char c) break; case '\n': /* next line */ - if (console_col || (!console_col && nl)) + if (console_col || nl) console_newline(1); nl = 1; break; diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 6ec4f89e346..26db73b1388 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -853,9 +853,10 @@ static u32 wait_for_event(u32 event) do { ret = lcdc_irq_handler(); udelay(1000); - } while (!(ret & event)); + --timeout; + } while (!(ret & event) && timeout); - if (timeout <= 0) { + if (!(ret & event)) { printf("%s: event %d not hit\n", __func__, event); return -1; } diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index 30e4020686a..3a6ef62890c 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -321,7 +321,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *regs, static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs) { - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; exynos_dp_set_training_pattern(regs, DP_NONE); @@ -339,7 +339,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode( struct exynos_dp *regs, unsigned char enable) { unsigned char data; - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET, &data); @@ -366,7 +366,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode( static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs, unsigned char enhance_mode) { - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode); if (ret != EXYNOS_DP_SUCCESS) { @@ -416,7 +416,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs, static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs, unsigned char lane_num, unsigned char *sw, unsigned char *em) { - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; unsigned char buf; unsigned int dpcd_addr; unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; @@ -484,7 +484,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *regs, static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs, struct exynos_dp_priv *priv) { - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; unsigned char lane_stat; unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; unsigned int i; @@ -594,7 +594,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs, static unsigned int exynos_dp_process_equalizer_training( struct exynos_dp *regs, struct exynos_dp_priv *priv) { - unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned int ret; unsigned char lane_stat, adj_req_sw, adj_req_em, i; unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; unsigned char interlane_aligned = 0; diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 953b47fb8c8..a7fa9c5110e 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -136,7 +136,7 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) struct rk_mipi_priv *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(priv->grf)) { + if (IS_ERR_OR_NULL(priv->grf)) { debug("%s: Get syscon grf failed (ret=%p)\n", __func__, priv->grf); return -ENXIO; diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 9ef202bf090..b936fcec9ba 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -128,7 +128,7 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) struct rk_mipi_priv *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (priv->grf <= 0) { + if (IS_ERR_OR_NULL(priv->grf)) { debug("%s: Get syscon grf failed (ret=%p)\n", __func__, priv->grf); return -ENXIO; diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h index 26e483cf566..5d00bff9fd0 100644 --- a/drivers/video/stb_truetype.h +++ b/drivers/video/stb_truetype.h @@ -1993,7 +1993,7 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill, STBTT_assert(fabs(area) <= 1.01f); - scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing); + scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing); scanline_fill[x2] += sign * (sy1-sy0); } diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index b417ac260a5..e160c77e075 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -1,8 +1,7 @@ /* - * Copyright (C) STMicroelectronics SA 2017 - * - * Authors: Philippe Cornu <philippe.cornu@st.com> - * Yannick Fertre <yannick.fertre@st.com> + * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved + * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics. + * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,6 +10,7 @@ #include <clk.h> #include <dm.h> #include <panel.h> +#include <reset.h> #include <video.h> #include <asm/io.h> #include <asm/arch/gpio.h> @@ -138,7 +138,9 @@ struct stm32_ltdc_priv { #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ +#define BF1_CA 0x400 /* Constant Alpha */ #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ +#define BF2_1CA 0x005 /* 1 - Constant Alpha */ enum stm32_ltdc_pix_fmt { PF_ARGB8888 = 0, @@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp) pf = PF_RGB565; break; + case VIDEO_BPP32: + pf = PF_ARGB8888; + break; + + case VIDEO_BPP8: + pf = PF_L8; + break; + case VIDEO_BPP1: case VIDEO_BPP2: case VIDEO_BPP4: - case VIDEO_BPP8: - case VIDEO_BPP32: default: debug("%s: warning %dbpp not supported yet, %dbpp instead\n", __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16)); @@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp) return (u32)pf; } +static bool has_alpha(u32 fmt) +{ + switch (fmt) { + case PF_ARGB8888: + case PF_ARGB1555: + case PF_ARGB4444: + case PF_AL44: + case PF_AL88: + return true; + case PF_RGB888: + case PF_RGB565: + case PF_L8: + default: + return false; + } +} + static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv) { /* Reload configuration immediately & enable LTDC */ @@ -219,6 +244,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv) val = (total_w << 16) | total_h; clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); + setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1); + /* Signal polarities */ val = 0; debug("%s: timing->flags 0x%08x\n", __func__, timing->flags); @@ -245,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) u32 line_length; u32 bus_width; u32 val, tmp, bpp; + u32 format; x0 = priv->crop_x; x1 = priv->crop_x + priv->crop_w - 1; @@ -275,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); /* Pixel format */ - val = stm32_ltdc_get_pixel_format(priv->l2bpp); - clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val); + format = stm32_ltdc_get_pixel_format(priv->l2bpp); + clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format); /* Constant alpha value */ clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); + /* Specifies the blending factors : with or without pixel alpha */ + /* Manage hw-specific capabilities */ + val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA; + /* Blending factors */ - clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, - BF1_PAXCA | BF2_1PAXCA); + clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val); /* Frame buffer line number */ clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h); @@ -301,8 +332,9 @@ static int stm32_ltdc_probe(struct udevice *dev) struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct stm32_ltdc_priv *priv = dev_get_priv(dev); struct udevice *panel; - struct clk pclk, pxclk; - int ret; + struct clk pclk; + struct reset_ctl rst; + int rate, ret; priv->regs = (void *)dev_read_addr(dev); if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { @@ -310,45 +342,60 @@ static int stm32_ltdc_probe(struct udevice *dev) return -EINVAL; } - ret = uclass_first_device(UCLASS_PANEL, &panel); + ret = clk_get_by_index(dev, 0, &pclk); if (ret) { - debug("%s: panel device error %d\n", __func__, ret); + debug("%s: peripheral clock get error %d\n", __func__, ret); return ret; } - ret = panel_enable_backlight(panel); + ret = clk_enable(&pclk); if (ret) { - debug("%s: panel %s enable backlight error %d\n", - __func__, panel->name, ret); + debug("%s: peripheral clock enable error %d\n", + __func__, ret); return ret; } - ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), - 0, &priv->timing); + ret = reset_get_by_index(dev, 0, &rst); if (ret) { - debug("%s: decode display timing error %d\n", __func__, ret); - return -EINVAL; + debug("%s: missing ltdc hardware reset\n", __func__); + return -ENODEV; } - ret = clk_get_by_name(dev, "pclk", &pclk); + /* Reset */ + reset_deassert(&rst); + + ret = uclass_first_device(UCLASS_PANEL, &panel); if (ret) { - debug("%s: peripheral clock get error %d\n", __func__, ret); + debug("%s: panel device error %d\n", __func__, ret); return ret; } - ret = clk_enable(&pclk); + ret = panel_enable_backlight(panel); if (ret) { - debug("%s: peripheral clock enable error %d\n", __func__, ret); + debug("%s: panel %s enable backlight error %d\n", + __func__, panel->name, ret); return ret; } - /* Verify pixel clock value if any & inform user accordingly */ - ret = clk_get_by_name(dev, "pxclk", &pxclk); - if (!ret) { - if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ) - printf("Warning: please adjust ltdc pixel clock\n"); + ret = fdtdec_decode_display_timing(gd->fdt_blob, + dev_of_offset(dev), 0, + &priv->timing); + if (ret) { + debug("%s: decode display timing error %d\n", + __func__, ret); + return -EINVAL; + } + + rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ); + if (rate < 0) { + debug("%s: fail to set pixel clock %d hz %d hz\n", + __func__, priv->timing.pixelclock.typ, rate); + return rate; } + debug("%s: Set pixel clock req %d hz get %d hz\n", __func__, + priv->timing.pixelclock.typ, rate); + /* TODO Below parameters are hard-coded for the moment... */ priv->l2bpp = VIDEO_BPP16; priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */ @@ -397,10 +444,10 @@ static const struct udevice_id stm32_ltdc_ids[] = { }; U_BOOT_DRIVER(stm32_ltdc) = { - .name = "stm32_ltdc", - .id = UCLASS_VIDEO, - .of_match = stm32_ltdc_ids, - .probe = stm32_ltdc_probe, - .bind = stm32_ltdc_bind, + .name = "stm32_display", + .id = UCLASS_VIDEO, + .of_match = stm32_ltdc_ids, + .probe = stm32_ltdc_probe, + .bind = stm32_ltdc_bind, .priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv), }; |