diff options
Diffstat (limited to 'nand_spl/board/ads5125')
| -rw-r--r-- | nand_spl/board/ads5125/Makefile | 93 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/config.mk | 233 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/dram.h | 101 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/nandload.h | 16 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/nandload.mtc | bin | 0 -> 5924 bytes | |||
| -rw-r--r-- | nand_spl/board/ads5125/nandstart.S | 299 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/nfc.h | 122 | ||||
| -rw-r--r-- | nand_spl/board/ads5125/u-boot.lds | 52 |
8 files changed, 916 insertions, 0 deletions
diff --git a/nand_spl/board/ads5125/Makefile b/nand_spl/board/ads5125/Makefile new file mode 100644 index 0000000000..7e349665fc --- /dev/null +++ b/nand_spl/board/ads5125/Makefile @@ -0,0 +1,93 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff00800 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = nandstart.o +COBJS = + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) $(OBJTREE)/nand_spl/board/$(BOARDDIR)/nandload.mtc +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-2k.bin $(nandobj)loader-script-5125.txt + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-2k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)loader-script-5125.txt:$(nandobj)u-boot-spl-2k.bin + $(TOPDIR)/nand_load_program $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +$(ELF): +$(obj)%: $(obj)%.o $(LIB) + $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ + -L$(gcclibdir) -lgcc + +$(SREC): +$(obj)%.srec: $(obj)% + $(OBJCOPY) -O srec $< $@ 2>/dev/null + +$(BIN): +$(obj)%.bin: $(obj)% + $(OBJCOPY) -O binary $< $@ 2>/dev/null + + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/ads5125/config.mk b/nand_spl/board/ads5125/config.mk new file mode 100644 index 0000000000..5a9334c6f6 --- /dev/null +++ b/nand_spl/board/ads5125/config.mk @@ -0,0 +1,233 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +ifneq ($(OBJTREE),$(SRCTREE)) +ifeq ($(CURDIR),$(SRCTREE)) +dir := +else +dir := $(subst $(SRCTREE)/,,$(CURDIR)) +endif + +obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) +src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) + +$(shell mkdir -p $(obj)) +else +obj := +src := +endif + +# clean the slate ... +PLATFORM_RELFLAGS = +PLATFORM_CPPFLAGS = +PLATFORM_LDFLAGS = + +######################################################################### + +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOSTCC = cc +else +HOSTCC = gcc +endif +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTSTRIP = strip + +######################################################################### +# +# Option checker (courtesy linux kernel) to ensure +# only supported compiler options are used +# +cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +######################################################################### + +# Load generated board configuration +sinclude $(OBJTREE)/include/autoconf.mk + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef SOC +sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + +######################################################################### + +ifneq (,$(findstring s,$(MAKEFLAGS))) +ARFLAGS = cr +else +ARFLAGS = crv +endif +RELFLAGS= $(PLATFORM_RELFLAGS) +DBGFLAGS= -g # -DDEBUG +OPTFLAGS= -Os #-fomit-frame-pointer +ifndef LDSCRIPT +#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +else +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds +endif +endif +OBJCFLAGS += --gap-fill=0xff + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ +ifneq ($(TEXT_BASE),) +CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +endif + +ifneq ($(OBJTREE),$(SRCTREE)) +CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include +endif + +CPPFLAGS += -I$(TOPDIR)/include +CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ + -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +endif + +CFLAGS += $(call cc-option,-fno-stack-protector) + +# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) +# this option have to be placed behind -Wall -- that's why it is here +ifeq ($(ARCH),nios) +ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9) +CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs +endif +endif + +# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format> +# option to the assembler. +AFLAGS_DEBUG := + +# turn jbsr into jsr for m68k +ifeq ($(ARCH),m68k) +ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) +AFLAGS_DEBUG := -Wa,-gstabs,-S +endif +endif + +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) + +LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS) +ifneq ($(TEXT_BASE),) +LDFLAGS += -Ttext $(TEXT_BASE) +endif + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +ifeq ($(PCI_CLOCK),PCI_66M) +CFLAGS := $(CFLAGS) -DPCI_66M +endif + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +######################################################################### + +ifndef REMOTE_BUILD + +%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +else + +$(obj)%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +$(obj)%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +$(obj)%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< +endif + +######################################################################### diff --git a/nand_spl/board/ads5125/dram.h b/nand_spl/board/ads5125/dram.h new file mode 100644 index 0000000000..cd26646a08 --- /dev/null +++ b/nand_spl/board/ads5125/dram.h @@ -0,0 +1,101 @@ +/* + * + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* these were originally in mpc512x.h */ +#define MDDRC_BASE_OFFSET 0x09000 +#define DDR_LAW_BAR 0x00a0 +#define DDR_LAW_AR 0x00a4 +#define IOCTL_BASE_ADDR 0x0a000 + +/* DRAM Controller Register Offsets */ +#define DDR_SYS_CONFIG 0x00 +#define DDR_TIME_CONFIG0 0x04 +#define DDR_TIME_CONFIG1 0x08 +#define DDR_TIME_CONFIG2 0x0C +#define DDR_COMMAND 0x10 +#define DDR_COMPACT_COMMAND 0x14 +#define DDR_SELF_REFRESH_CMD_0 0x18 +#define DDR_SELF_REFRESH_CMD_1 0x1C +#define DDR_SELF_REFRESH_CMD_2 0x20 +#define DDR_SELF_REFRESH_CMD_3 0x24 +#define DDR_SELF_REFRESH_CMD_4 0x28 +#define DDR_SELF_REFRESH_CMD_5 0x2C +#define DDR_SELF_REFRESH_CMD_6 0x30 +#define DDR_SELF_REFRESH_CMD_7 0x34 +#define DDR_DQS_CONFIG_COUNT 0x38 +#define DDR_DQS_CONFIG_TIME 0x3C +#define DDR_DQS_DELAY_STATUS 0x40 + +/* DRAM Controller Priority Manager Register Offsets */ +#define DRAMPRIOM_PRIOMAN_CONFIG1 0x080 +#define DRAMPRIOM_PRIOMAN_CONFIG2 0x084 +#define DRAMPRIOM_HIPRIO_CONFIG 0x088 +#define DRAMPRIOM_LUT_TABLE0_MAIN_UP 0x08C +#define DRAMPRIOM_LUT_TABLE1_MAIN_UP 0x090 +#define DRAMPRIOM_LUT_TABLE2_MAIN_UP 0x094 +#define DRAMPRIOM_LUT_TABLE3_MAIN_UP 0x098 +#define DRAMPRIOM_LUT_TABLE4_MAIN_UP 0x09C +#define DRAMPRIOM_LUT_TABLE0_MAIN_LOW 0x0A0 +#define DRAMPRIOM_LUT_TABLE1_MAIN_LOW 0x0A4 +#define DRAMPRIOM_LUT_TABLE2_MAIN_LOW 0x0A8 +#define DRAMPRIOM_LUT_TABLE3_MAIN_LOW 0x0AC +#define DRAMPRIOM_LUT_TABLE4_MAIN_LOW 0x0B0 +#define DRAMPRIOM_LUT_TABLE0_ALT_UP 0x0B4 +#define DRAMPRIOM_LUT_TABLE1_ALT_UP 0x0B8 +#define DRAMPRIOM_LUT_TABLE2_ALT_UP 0x0BC +#define DRAMPRIOM_LUT_TABLE3_ALT_UP 0x0C0 +#define DRAMPRIOM_LUT_TABLE4_ALT_UP 0x0C4 +#define DRAMPRIOM_LUT_TABLE0_ALT_LOW 0x0C8 +#define DRAMPRIOM_LUT_TABLE1_ALT_LOW 0x0CC +#define DRAMPRIOM_LUT_TABLE2_ALT_LOW 0x0D0 +#define DRAMPRIOM_LUT_TABLE3_ALT_LOW 0x0D4 +#define DRAMPRIOM_LUT_TABLE4_ALT_LOW 0x0D8 +#define DRAMPRIOM_PERF_MONITOR_CONFIG 0x0DC +#define DRAMPRIOM_EVENT_TIME_COUNTER 0x0E0 +#define DRAMPRIOM_EVENT_TIME_PRESET 0x0E4 +#define DRAMPRIOM_PERF_MNTR1_ADDR_LOW 0x0E8 +#define DRAMPRIOM_PERF_MNTR2_ADDR_LOW 0x0EC +#define DRAMPRIOM_PERF_MNTR1_ADDR_HI 0x0F0 +#define DRAMPRIOM_PERF_MNTR2_ADDR_HI 0x0F4 +#define DRAMPRIOM_PERF_MNTR1_READ_CNTR 0x100 +#define DRAMPRIOM_PERF_MNTR2_READ_CNTR 0x104 +#define DRAMPRIOM_PERF_MNTR1_WRITE_CNTR 0x108 +#define DRAMPRIOM_PERF_MNTR2_WRITE_CNTR 0x10C +#define DRAMPRIOM_GRANTED_ACK_CNTR0 0x110 +#define DRAMPRIOM_GRANTED_ACK_CNTR1 0x114 +#define DRAMPRIOM_GRANTED_ACK_CNTR2 0x118 +#define DRAMPRIOM_GRANTED_ACK_CNTR3 0x11C +#define DRAMPRIOM_GRANTED_ACK_CNTR4 0x120 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR0 0x124 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR1 0x128 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR2 0x12C +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR3 0x130 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR4 0x134 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR0 0x138 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR1 0x13C +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR2 0x140 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR3 0x144 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR4 0x148 + + diff --git a/nand_spl/board/ads5125/nandload.h b/nand_spl/board/ads5125/nandload.h new file mode 100644 index 0000000000..ec5a76e91a --- /dev/null +++ b/nand_spl/board/ads5125/nandload.h @@ -0,0 +1,16 @@ +/* + Provider: LimePC Multimedia Technologies Co., Limited + Date:01/14/2010 + Copyright note: without provider's written consensus by the provider, any release + of provider's code could result in infrigement of provider's intellectural properties. + Autor:Cloudy Chen <chen_yunsong@mtcera.com> +*/ +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/bitops.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <mpc5125_nfc.h> +void sram_to_ddr(void); +void nandload(void);
\ No newline at end of file diff --git a/nand_spl/board/ads5125/nandload.mtc b/nand_spl/board/ads5125/nandload.mtc Binary files differnew file mode 100644 index 0000000000..182d8a032b --- /dev/null +++ b/nand_spl/board/ads5125/nandload.mtc diff --git a/nand_spl/board/ads5125/nandstart.S b/nand_spl/board/ads5125/nandstart.S new file mode 100644 index 0000000000..c61d99cf9b --- /dev/null +++ b/nand_spl/board/ads5125/nandstart.S @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * Based on original start.S done by + * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> + * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de> + * start.S for mpc512x was originally based on the MPC83xx code. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - NAND Boot Startup Code for MPC5121 Embedded Boards + */ +#define DEBUG + +#include <config.h> +#include <mpc512x.h> +#include <version.h> +#include "dram.h" +//#include "nfc.h" + +#define CONFIG_521X 1 /* needed for Linux kernel header files*/ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#undef MSR_KERNEL +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* Macros for manipulating CSx_START/STOP */ +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) +#define SET_MEM_BASE(r, b) \ + lis r,(b)@h; \ + ori r,r,(b)@l; \ + +#define SET_REG32(r, v, offset, mr) \ + lis r, v@h; \ + ori r, r, v@l; \ + stw r, offset(mr); \ + +#define SET_REG16(r, v, offset, mr) \ + li r, v; \ + sth r, offset(mr); \ + + + .text + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, " " + .ascii "2K NAND BOOT ","\0" + . = EXC_OFF_SYS_RESET + + .globl _start + /* Start from here after reset/power on */ +_start: +boot_cold: + /* Save msr contents */ + mfmsr r5 + lis r4, CONFIG_DEFAULT_IMMR@h + + /* Set IMMR area to our preferred location */ + mfspr r6, MBAR + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + + cmpw r3, r6 + beq 1f /* it has already been set to what we want it to be */ + /* -- nice to chk if coming out of the BDI */ + + + stw r3, IMMRBAR(r4) + mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + isync +1: lis r4, START_REG(CFG_FLASH_BASE) + ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + stw r4, LPBAW(r3) + stw r4, LPCS0AW(r3) + isync + /* Initialise the machine */ + bl cpu_early_init + isync + + /* + * The SRAM window has a fixed size (256K), + * so only the start addressis necessary + */ + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + stw r4, SRAMBAR(r3) + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lwz r4, SRAMBAR(r3) + isync + +#if 0 +#ifdef CONFIG_ADS5125 /* CS2 FUNC MUX must be done before CS is enabled */ + lis r4, (CONFIG_SYS_IOCTRL_ADDR)@h + ori r4, r4, (CONFIG_SYS_IOCTRL_ADDR)@l + li r5, IOCTRL_MUX_CS2 + stb r5, IO_CTRL_LPC_AX03(r4) +/* change the pin muxing on PSC9 here in case it is being used as console*/ + li r5, IOCTRL_MUX_PSC9 + stb r5, IO_CTRL_I2C1_SCL(r4) + stb r5, IO_CTRL_I2C1_SDA(r4) + +#endif +#endif + + /* r3: BOOTFLAG */ + mr r3, r21 + + bl dram_init + + + /* r3: BOOTFLAG */ + mr r3, r21 + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + /*copy sram to ddr*/ + bl sram_to_ddr + /* copy the full U-Boot into DDR */ + /* and jump to it */ +jump_uboot: + SET_MEM_BASE(r10, nandload-CONFIG_SYS_NAND_BASE+CFG_LOADER_DDR_START) + mtlr r10 + isync + blr + + /* NOTREACHED - nand_boot() does not return */ +/* + * This code initialises the machine, + * it expects original MSR contents to be in r5 + */ +cpu_early_init: + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ +#endif + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ + + lis r3, CFG_IMMR@h + + /* Disable the watchdog */ + /*----------------------*/ + lwz r4, SWCRR(r3) + /* + * Check to see if it's enabled for disabling: once disabled by s/w + * it's not possible to re-enable it + */ + andi. r4, r4, 0x4 + beq 1f + xor r4, r4, r4 + stw r4, SWCRR(r3) +1: + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + blr + +dram_init: + + SET_MEM_BASE(r3, CFG_IMMR + IOCTL_BASE_ADDR) + SET_REG32(r4, (IOCTRL_MUX_DDR<<24), IOCTL_MEM , r3) + + SET_MEM_BASE(r3, CFG_IMMR) + SET_REG32(r4, CFG_DDR_BASE & 0xFFFFF000, DDR_LAW_BAR, r3) + SET_REG32(r4, 0x0000001b, DDR_LAW_AR, r3) + lwz r0, DDR_LAW_AR(r3) + isync + + SET_MEM_BASE(r3, CFG_IMMR + MDDRC_BASE_OFFSET) + SET_REG32(r4, CFG_MDDRC_SYS_CFG_EN, DDR_SYS_CONFIG, r3) + + SET_REG32(r4, CFG_MDDRCGRP_PM_CFG1, DRAMPRIOM_PRIOMAN_CONFIG1, r3) + SET_REG32(r4, CFG_MDDRCGRP_PM_CFG2, DRAMPRIOM_PRIOMAN_CONFIG2, r3) + SET_REG32(r4, CFG_MDDRCGRP_HIPRIO_CFG, DRAMPRIOM_HIPRIO_CONFIG, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_MU, DRAMPRIOM_LUT_TABLE0_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_ML, DRAMPRIOM_LUT_TABLE0_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_MU, DRAMPRIOM_LUT_TABLE1_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_ML, DRAMPRIOM_LUT_TABLE1_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_MU, DRAMPRIOM_LUT_TABLE2_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_ML, DRAMPRIOM_LUT_TABLE2_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_MU, DRAMPRIOM_LUT_TABLE3_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_ML, DRAMPRIOM_LUT_TABLE3_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_MU, DRAMPRIOM_LUT_TABLE4_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_ML, DRAMPRIOM_LUT_TABLE4_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_AU, DRAMPRIOM_LUT_TABLE0_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_AL, DRAMPRIOM_LUT_TABLE0_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_AU, DRAMPRIOM_LUT_TABLE1_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_AL, DRAMPRIOM_LUT_TABLE1_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_AU, DRAMPRIOM_LUT_TABLE2_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_AL, DRAMPRIOM_LUT_TABLE2_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_AU, DRAMPRIOM_LUT_TABLE3_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_AL, DRAMPRIOM_LUT_TABLE3_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_AU, DRAMPRIOM_LUT_TABLE4_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_AL, DRAMPRIOM_LUT_TABLE4_ALT_LOW, r3) + + /* Initialize MDDRC */ + SET_REG32(r4, CFG_MDDRC_SYS_CFG_EN, DDR_SYS_CONFIG, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG0, DDR_TIME_CONFIG0, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG1, DDR_TIME_CONFIG1, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG2, DDR_TIME_CONFIG2, r3) + + + /* Initialize DDR */ + SET_REG32(r4, CFG_MICRON_NOP, DDR_COMMAND, r3) + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r5, CFG_MICRON_NOP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_EM2, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EM2, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EM3, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EN_DLL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_OCD_DEFAULT, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + + /* Start MDDRC */ + SET_REG32(r4, CFG_MDDRC_TIME_CFG0_RUN, DDR_TIME_CONFIG0, r3) + SET_REG32(r4, CFG_MDDRC_SYS_CFG_RUN, DDR_SYS_CONFIG, r3) + isync + blr + diff --git a/nand_spl/board/ads5125/nfc.h b/nand_spl/board/ads5125/nfc.h new file mode 100644 index 0000000000..1406118eba --- /dev/null +++ b/nand_spl/board/ads5125/nfc.h @@ -0,0 +1,122 @@ +/* + * + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define TWO_K 0x800 +#define NUMPAGES 137 /* if u-boot grows .. extend this */ + +/* NAND Flash Controller Register Offsets */ +#define NFC_BUF_MAIN1 0x0000 +#define NFC_BUF_MAIN2 0x0200 +#define NFC_BUF_MAIN3 0x0400 +#define NFC_BUF_MAIN4 0x0600 +#define NFC_BUF_MAIN5 0x0800 +#define NFC_BUF_MAIN6 0x0A00 +#define NFC_BUF_MAIN7 0x0C00 +#define NFC_BUF_MAIN8 0x0E00 +#define NFC_BUF_SPARE1 0x1000 +#define NFC_BUF_SPARE2 0x1040 +#define NFC_BUF_SPARE3 0x1080 +#define NFC_BUF_SPARE4 0x10c0 +#define NFC_BUF_SPARE5 0x1100 +#define NFC_BUF_SPARE6 0x1140 +#define NFC_BUF_SPARE7 0x1180 +#define NFC_BUF_SPARE8 0x11c0 + +#define NFC_RAM_BUF_ADDR 0x1e04 +#define NFC_FLASH_ADDR 0x1e06 +#define NFC_FLASH_CMD 0x1e08 +#define NFC_NFC_CFG 0x1e0a +#define NFC_ECC_STATUS1 0x1e0c +#define NFC_ECC_STATUS2 0x1e0e +#define NFC_SPAS 0x1e10 +#define NFC_NF_WR_PROT 0x1e12 +#define NFC_FL_WP_STAT 0x1e18 +#define NFC_NF_CFG1 0x1e1a +#define NFC_NF_CFG2 0x1e1c +#define NFC_UNLOCKSTART_BLKADDR0 0x1E20 +#define NFC_UNLOCKEND_BLKADDR0 0x1E22 +#define NFC_UNLOCKSTART_BLKADDR1 0x1E24 +#define NFC_UNLOCKEND_BLKADDR1 0x1E26 +#define NFC_UNLOCKSTART_BLKADDR2 0x1E28 +#define NFC_UNLOCKEND_BLKADDR2 0x1E2A +#define NFC_UNLOCKSTART_BLKADDR3 0x1E2C +#define NFC_UNLOCKEND_BLKADDR3 0x1E2E + +#define RAM_BUFFER_ADDRESS_RBA_4 0x4 +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 + +/* Bit Definitions */ +#define NFC_INT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLOCKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + + + +#define NAND_CMD_RESET 0xff +#define NFC_ECC_MODE_4 1 +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 +#define NAND_CMD_READ0 0 +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_READCACHE 0x31 +#define NAND_CMD_READCACHEND 0x34 + diff --git a/nand_spl/board/ads5125/u-boot.lds b/nand_spl/board/ads5125/u-boot.lds new file mode 100644 index 0000000000..832a7c6004 --- /dev/null +++ b/nand_spl/board/ads5125/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(.rodata*) + *(.eh_frame) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff00800, "NAND bootstrap too big"); |