Age | Commit message (Collapse) | Author |
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implement get f/w version api
print ele f/w version in spl.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
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Add configs to support imx8/imx8m/imx8ulp reference boards, each platform
has specific header files include.
Test: sanity test on imx8/imx8m/imx8ulp platforms.
Change-Id: I05708fbc108a78ac9b3415cb782bf1013e2f7012
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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Add RDC config functions so we can config the RDC on
i.MX 8MQ in SPL.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I0cf4b7a11438afa460b9eb486ad865b74df28125
(cherry picked from commit f3033e7d3ecaf15f9026d72c7642b6fd9aff919d)
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Setting the CSU configs to enhance the imx8mq security. And as
the ocram space reserved for TF-A is very limited (64 KB), the
code size would overflow the limit if setting csu configs in TF-A,
so this commit will set it in spl.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If9d2c20401cb256174aa2e9a72cae2686e58c7bd
(cherry picked from commit 9f08e16a291e4d42b6ccb7386b506f6317931bb5)
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Make change to support trusty on imx8ulp.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: Ie3da6f6b1203d1b85a41609600613bdd8baa55c7
(cherry picked from commit 99e3b70f570db66a4228238f3192de57651c03a3)
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Add board level implementation to get the ON-OFF button
status for imx8q/imx8m.
Test: Get ON-OFF button status on imx7ulp/imx8m/imx8q.
Change-Id: I8e4ea61ec1c52ab7cfa20b5498756a25f3cd2f8d
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 44c6edfbd2607f1458220031467fc7de20dc46be)
(cherry picked from commit f7584f25285b94e2ea0f312399d1aef9671673b2)
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Porting the scu api 'sc_misc_get_button_status()' to get the
ON-OFF button status.
Test: Get the ON-OFF button status.
Change-Id: I8e06ef4dc170750fe2dfbeeba7850b5e0dcfc774
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 130747618d813ea64611ed111e5d80487aa154b6)
(cherry picked from commit 562eefcbddf3b6f186fc7e26b5bce2ca32000eb8)
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To avoid both A/B slots are marked as unbootable because
of some random failures, we will need to reset at spl stage
when current slot load/verify fail but already with flag
"successful_boot" set.
imx8q can't be reset via the psci driver because the atf
is not avaiable at spl stage, porting the sc_pm_reboot()
scu api so we can do reset at spl stage for imx8qm/imx8qxp
mek boards.
Test: reset on imx8qm_mek and imx8qxp_mek.
Change-Id: Ifa0bdea9393e413942a8a0188a4f937fa0aa9ab8
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from a5c5748101c383bc3afb424a3ef2689ab2664846)
(cherry picked from c9f8d7c19a7fc20c99e061beabbb094b6bd50f52)
(cherry picked from e42f06dbc70934ff9f535104f7322b9ac36491ce)
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Update the mx6sx SDB and AUTO ARD board codes and DTS to support
DM video splash screen.
Both have two video path:
1. LCDIF1 -> LCD panel
2. LCDIF2 -> LVDS channel 0
Signed-off-by: Ye Li <ye.li@nxp.com>
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When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 998cde6f8f15906f18c3c84cbf5745b40f5af5b7)
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Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960M for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 34710728a869d43224058f19572c05b6d6fc2332)
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The D-PHY ref clock source is configurable. We need to know the reference
clock rate for D-PHY PLL calculation.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 2560cd096e54d21d5b68fd3cb70e4d3140854bc3)
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Enable to measure die temperature using the PMC Temperature Sensor on
i.MX8ULP.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1551d5ac1fe6447f5f9ae2eccd838a63f14a56c2)
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Beside the fused modules on iMX8MP Lite, this part has also fused
GPU3D/2D, LVDS and MIPI DSI.
So we have to disable them for kernel and also disable MIPI DSI
in u-boot DTS for splash screen at runtime.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 8de08ed09c0853ec5bf74f52db29b90f9f619ead)
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JRO is reserved in ATF for use by HAB(secure boot)
and not released to non secure(NS).
CAAM crypto operation are failing when use JR0 in uboot.
when DM is enabled
set the status of JR0 as disabled in device tree,
so JR0 is not initialized.
JR1 is initialized in SPL and Uboot.
when DM is not enabled
SEC job ring address is defined with JR1 offset(0x2000).
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit ed618ce6a95b51ec30f37311d374f9178e0cc44c)
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Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d1fec2211c09d5cb6830b72dbab7adb22c4d44d5)
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Add ahab_dump_buffer API to dump AHAB buffer for debug purpose
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fcf98912a3ce9beb9423f2768d1b5eda24b56fcf)
(cherry picked from commit b7a95fae425db7cc7766b2b0429e56f0f2699ba8)
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Message "release CAAM" to be sent to S400 before CAAM be
accessed for initialization.
CAAM job ring one(JR1) is available.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Varun Sethi <V.Sethi@nxp.com>
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
(cherry picked from commit c62ca64678dc7ad2f52f22957b6755d9bf9418ce)
(cherry picked from commit 210f84da453bbd1bece77902172feaa4333bc2dc)
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Add ahab_release_caam() function to the S400 API.
Release the CAAM for the A35 from the SPL.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
(cherry picked from commit 7f8f924c4a08d339da43ca5d0d90b232178f8b28)
(cherry picked from commit 29407a880ba064219c8d9f60343a7d9214f878d7)
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Add the pinmux settings for flexspi0 relevant pins
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c6c3025d3fec1c7318eb9e86be57cd00b2be0558)
(cherry picked from commit 832fe03097a488be32a4e74e5b88ae73bab01069)
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Using ROM API to get boot device and checks it for MMC ENV device
and USB boot device
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d3c6167fb9def3cbdf89d8c93cbc8f1b2f1d2c41)
(cherry picked from commit e85dab751d7c9459276840823df0c63acf8e3272)
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To support two PHY instances, we have to adjust the common USB PLL
function used for iMX8ULP and iMX7ULP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 84abd9c8dcbb06bce5041cf808b8360f6fae3e28)
(cherry picked from commit db40a9d56389974e28e750991131292473df6630)
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Abstract common interfaces for AHAB authentication operations.
Then share some common codes for AHAB and SPL container authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c668e8e3222e234b80aceb23b18482f427ff51e1)
(cherry picked from commit 423c6933ba55b848c3e2b43e6524ea804ccaebbe)
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Support iMX8DXL in mxsfb driver by below changes:
1. Enable iMX8 in lcdif registers file
2. Add u-boot clock driver support for iMX8
3. Change the FB buffer alignment to align it at allocation. So
it won't overlay with other memory at mmu_set_region_dcache_behaviour
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6f02d6894509e0aa79df9d1bdf5029136e1493b5)
(cherry picked from commit 9df950e79963c328b1b04d6eb42f43f41217e752)
(cherry picked from commit 082b8d3c6e17691edf902781d4bb5d978bcecaa5)
(cherry picked from commit 3367dd0c8e9a8a6b868a40e3b4b16523a078289e)
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Enable LPSPI2-3 clock enable and get functions.
Please note that the lpspi's alias should only be set as same as its
module number.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 132ea95f15f3dcf3408d70eb7879533b412cd521)
(cherry picked from commit a0a365025d16694dcce4fc0a5980067bbd389803)
(cherry picked from commit a6f09651f67587c096b9d3983b7ca8c6aac9929b)
(cherry picked from commit 2c4364d93a8132306a67adeb0b03bd1f2cabc7bc)
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i.MX 6 and i.MX 7 do not have the same offset from IOMUXC_BASE_ADDR
for the IOMUX GRP.
Try to align both structure.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 3d80f811dad882d8fe950dabee934bd3a1bf86b5)
(cherry picked from commit 19b2fbbba43d6f339f32a81d47659835f65ee4e6)
(cherry picked from commit 50e2d3698a2ab1a0029bf15da0b0256fad054d99)
(cherry picked from commit edc419f140812f6f84ba192b1f73a4b05a0d5f29)
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8DXL A1 revision uses same id register value with revision B,
so A1 chip is recognized as RevB. Add new dummy chip revision for
8DXL A1 and A2 to distinguish with of RevB and RevC
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 687f605630e0b87e963419aa59dec06d0f7b9cb1)
(cherry picked from commit 3a23f967592100b0c4a5bef2a57930882ffef0d6)
(cherry picked from commit 295b9157cc8d0cb73058d06069e927195b258122)
(cherry picked from commit 5448a1e353e00dcf43bf3ecc19bdb5ac5352920d)
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Update SCFW API to add sc_seco_v2x_build_info API which can
get the version and commit of V2X firmware on 8DXL
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 655e05e6751ebbd94dd9ab1b77ed1020a661a115)
(cherry picked from commit 057dc774a4c2873160f470eca22201394ad3c6ac)
(cherry picked from commit 0483b4742ff73985b00ddd16960a3bca6f1ae843)
(cherry picked from commit 919999573a388efc9d8e6e311e225192ea865a40)
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Update i.mx8mp pinfunc.h according to RM REV C.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6bc25e394d404386315382992d1380a36a45cf6f)
(cherry picked from commit 8966725177cddd216c2d37d3fc5a80ca62d03da1)
(cherry picked from commit f3a28efac6ec561b6d116728eb9f7f6d5e812a03)
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Update DTS for LCDIF, MIPI DSI and panel relevant nodes.
Enable the video drivers and splash screen in board codse
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 52d4c7c3e98d573f1c3e4e67e02dd4b08be6bee7)
(cherry picked from commit 6a4a992f81ffd75f0c9ec78703009000d8045a5c)
(cherry picked from commit d963dfd9fca5e28db01b6faa03c0d8f8821ed69e)
(cherry picked from commit 2036e8dbe9edee25d132e47cb828f32fd79e7968)
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Add video driver for DPU, display driver for LVDS and bridge driver
for it6263 LVDS to HDMI convertor
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 65f54f7a7562a005177281a8bb397774b676ad2b)
(cherry picked from commit 21d02f540bb48e386d4a800e797e97f33ae37355)
(cherry picked from commit d4fbd9dd6bbd79d67f36b8c930b3b4747449cceb)
(cherry picked from commit e2514c78da0687bfed42d90b92d4d740ba2440f6)
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SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.
Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21).
old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com>
(cherry picked from commit e84fb02056fe50146856320b96de909dad4c0058)
(cherry picked from commit 63c9e1b0b2a7f45b76d95624503bed377a3dd226)
(cherry picked from commit ac5836e3adee8d1b0046b6f48e47e690adcd0968)
(cherry picked from commit 31debe5cc3ba090df5162edb287d85d67dd11b91)
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As it is done in ATF for i.MX 8 SoC.
Enable and set region 0 attribute to be allow secure
and non-secure transaction.
Add this function to each SOC arch init.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b81e528dd232b8c2f4d10e89c6bf20c65263b14e)
(cherry picked from commit 7c8809d90ed336550906e3108fe8dc99c6bea3e7)
(cherry picked from commit 3332ea64bc70cbe415028026f5e2896856749a9c)
(cherry picked from commit c1bd7f881e75aad7ca69c970c2a4978a14b55bad)
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USB OH clock is default enabled by SCFW because it shared
between two USB controller.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
(cherry picked from commit 7a8ec829d4410c51550ad7a589645595042ba541)
(cherry picked from commit c0041c43f554a778c27d7574b3d58fb76ace6d48)
(cherry picked from commit a4fdd6210a081fd391ae574efe94cacef6c1ddcd)
(cherry picked from commit ea3731bf3d99bbcaa95c25775d7dfb651a8a8cb6)
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Add soc id in cpu codes and conditionals.
Also add support for v2x container on 8DXL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit 35691a6b85c3240b0e3b9f9a8da9fc6328bf92d8)
(cherry picked from commit f1f546d03dec535774f0583ae95b02875dfcf72c)
(cherry picked from commit 09800a15fd8573ace396346f0f615300785b686e)
(cherry picked from commit e8439682e7c9feb53fd16dea0dc2ab9f03d2b6d3)
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Add clocks required for new i.MX8DXL SoC. Since most of clocks are
same as iMX8QXP, share the same driver but with iMX8DXL new clocks added.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit f9c23b2df504c5db5f8f4567ee4c92f2439308fc)
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit dc7b8a6b97258e7a46a014e5b866cac55ad617f7)
(cherry picked from commit f4ce88dfe557dc87f3a107b32b9b6126f58160f7)
(cherry picked from commit eddd8eb01a307fa840a5a7a22bf6bd4e52330450)
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Add pads for i.MX8DXL SoC
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit eccdb0d167e10dc8f179c00cbb1ebee72d93225b)
(cherry picked from commit e6953f3167af25961c7f02adcba8f0ace335567d)
(cherry picked from commit 5e81803ff75c14f4471b6df00e305c58883ee842)
(cherry picked from commit a60bb798d9afbad27557c6f3e23a2ec883e408ff)
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Upgrade SCFW API to 1.16 to align with commit
8f2a1e1(SSI-87: imx8: Configure SNVS) in imx_v2020.04 u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 96f68c478549990c2c79e9afc3bf691e1fa90438)
(cherry picked from commit acb7c1c6527d542109d16ad81d2ecc97f191c4f7)
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If inline ECC is enabled on imx8mp, then the ECC region should be
reserved. Since the limit of the ddr address map when use inline ecc
and 6G memory, ECC region have to be divided into three parts. So these
three parts ECC region should be set as reserved-memory with no-map.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
(cherry picked from commit 0ea77fc9364e46e897cfa554d93895595aaf2a20)
(cherry picked from commit db36f389921293abbd2824e95867650ae290bad5)
(cherry picked from commit 95c9950c65251dc2748519660598920c3048a24c)
(cherry picked from commit a6fe82733f9c4c7b8b3f5ca552e4e9ccd7db1555)
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- Remove code duplication betwee imx8 and imx8m support
- add reserved memory node to prevent Linux accessing optee reserved memory
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8beac7ef22c16b72ad337b44a0516436a4a0d00c)
(cherry picked from commit 07be6f855bdcbca200e4685ea557b2529187e29f)
(cherry picked from commit 1bfbbac316e3d7ac051f81264b66425a86d95c4d)
(cherry picked from commit 6a27dd9792900a6512b05eca85d22aab120c74a6)
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To share some common optee codes for iMX8 and iMX8M, we need same
name for parameters passed from ATF. Currently iMX8 uses boot_pointer
but iMX8M use rom_pointer. So rename boot_pointer to rom_pointer.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 47a04423cb09d84ba7558ba9570515901f124c0f)
(cherry picked from commit 7d1fe0e66e9537c05a2abff6f16c555ddff63bad)
(cherry picked from commit d49149dba994f75675c674770d0c0f54e3f56bbf)
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add the missing bch register debug0
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 0883946855f7e1eabe26787fbc8529ac412047e7)
(cherry picked from commit 56235ef0fd596ab9d1d0b15db3cf708d058da703)
(cherry picked from commit 554d3ebe2854e12095939ba7960717d1d93c03f3)
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Convert the ci_udc driver to driver model by using the uclass
UCLASS_USB_GADGET_GENERIC. The clk and power of USB controller and USB
PHY both are initialized by parsing the device tree nodes.
If CONFIG_DM_USB_GADGET is defined, we use the ci_udc driver in DM way,
if it does not defined, we can use ci_udc driver in its original Non-DM
way.
Move some USB PHY register definitions from ehci-mx6.c to
asm/mach-imx/regs-usbphy.h in order to share with DM usb gadget driver.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5c50d6bd6fda34827a27387e42c9a803da40b1e5)
(cherry picked from commit 24c896d4d2fab51abd287f1a991c68fc709d2458)
(cherry picked from commit 455bed086f7f264a9abbb778218c095dff332300)
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We use a glue layer to link the low level MU driver and virtual drivers.
This glue layer is named to virtual service (iMX VService). Virtual service
provides unified interfaces for setup connection with M4, get message buffer
and send/receive message, etc.
Multiple virtual drivers (i2c, gpio, etc)
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iMX Vservice
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imx_mu_m4 driver
For each virtual device, by default, the Vservice uses the device node property
"fsl,vservice-mu" to specify the MU node handler. A override function is also provided,
so te ARCH level can define its rule. We will use the override function for dynamically
select MU on 8QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 7537b3c0fbe4e2c355bc4ff20613958bdd178bcd)
(cherry picked from commit 3caa81795c16a7644f60ed3b9c77030446b49484)
(cherry picked from commit 07ebb7da77f39aba02da46979f0516d44c9a6973)
(cherry picked from commit ff47f79b9c5950e73af615169136b453529ec82b)
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Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e1b5acafb549eb8c09379e466151ddd358b48ad7)
(cherry picked from commit d7e21ae132cecb7fee8fa0d30e92024a0d10241c)
(cherry picked from commit cd54b2bcf65508cde41adae071fcd22615ea076b)
(cherry picked from commit 3f3fb51f56174088e6a9612c1e23b4729d1b9803)
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Add CPU type, Kconfig for iMX8QM and update SoC codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3512fc146095df33882ae45a62174924b7aac58c)
(cherry picked from commit 1d5b77f78c09e572975e722b3ed908e6becdf337)
(cherry picked from commit f73c232781239c5f54148b5da2061a173eb6a583)
(cherry picked from commit 8e1aa344a731d47fc12dc5be3105b0fa0ceecf5a)
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1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download
M4 image to any DDR address first. Then use the
"bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0
or CM4_1, the default core id is 0 for CM4_0.
Since current M4 only supports running in TCM. The bootaux will copy
the M4 image from DDR to its TCML.
2. Implment bootaux for HIFI on QXP
command: bootaux 0x81000000 1
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 778606204b84ce6646fe58d752e2abda67600cf2)
(cherry picked from commit e4a3fcc6fd357502d61687659b9cd7d2808b3fd4)
(cherry picked from commit 13eafa71a6cad662af16e7997ec75b785753bb66)
(cherry picked from commit 50e421d39a5c6913838794996fc98d01da42de3f)
(cherry picked from commit c8c5630dc5efd6887fe70a56cd20fcd8eff730ea)
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SION bit needs to be set when the pin are used for I2C.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e74561bcaa67e11ed5889959ab22afb5a9885c82)
(cherry picked from commit 192016dc33d2ab3a8e1e7c8348ce02d69416e290)
(cherry picked from commit 09232bc102fe55abab5a0ffd1395c31ef4bb723b)
(cherry picked from commit c2f58391959e77e0cf4790c817a0bc2d4832d5cb)
(cherry picked from commit 304f6058134f36fcba1518247c133c2b7d0ebd6c)
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Add new u-boot command "imx_tamper" to configure and check the tamper pins.
The codes are used for reference and test. So command is disabled at default,
user can enable it by adding CONFIG_IMX_TAMPER=y to defconfig
The iMX7D has 10 tamper pins those can be used for SNVS tamper detection.
Tamper 9 pin is NVCC_DRAM power switch for LPSR by default.
It must be fused to tamper function by command
=> fuse prog -y 1 3 0x80000000
Otherwise, SNVS power consumption would be high
When tamper is detected, CPU can't enter/stay in SNVS mode,
the tamper must be cleared and disabled before enter SNVS.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Shaojun Wang <shaojun.wang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d520e1c6067c08103a020b0bc19feb620473e543)
(cherry picked from commit 4333529337a554352e1f9fb7486287dea31aeb79)
(cherry picked from commit c8ca53e9891371c292d4e88a92dd52498ba1c1a2)
(cherry picked from commit 259dd95c3eda643761b0b273d2ad4dc0f9cf228b)
(cherry picked from commit cecb952928c03abd23b2195767271723146b5beb)
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The get_boot_device will return USB type from ROM info if booting from
serial download, so change the is_boot_from_usb to use this function.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 306fca12fb21829be552a6262e310a90664a8cc2)
(cherry picked from commit 4880a6a4c93fd7141d4cc1de5b987c8efdf2cc2a)
(cherry picked from commit cc216825ff95cd2b7326b66aef2bb512f6d1824e)
(cherry picked from commit b86b2ec0f76d9ccc99baa33aab958511b6b844e5)
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