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2018-09-27mx6: ddr: use consistent debug outputMax Krummenacher
Print all ddr calibration output in the same style. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-09-20ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson
The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com> (cherry picked from commit a425bf72816abbc3996540e42c33a386e8b8a221)
2018-09-20mx6: ddr: add routine to return DDR calibration dataEric Nelson
Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com> (cherry picked from commit 48c7d4379bcf70ce331e441b135cfbf3546dd574)
2018-09-20mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson
The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de> (cherry picked from commit 7f17fb7400ff091dd48f86977655c6a57d06b17c)
2018-09-20mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de> (cherry picked from commit b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3)
2018-09-13imx: imx-common: do not zero out outside of regionsStefan Agner
There are two issues with the zeroing out code currently: The cache flush does not take the zeroed out section into account! The M4 firmware is started right after copying the firmware, and might use the memory area. Since the M4 and the A7 (where U-Boot is running) are not cache coherent, flushing cache could overwrite the M4's variable at any point in time, leading to crashes of the M4 firmware... Secondly, the program header of a Cortex-M4 firmware might look like this: LOAD off 0x00007240 vaddr 0x20000240 paddr 0x1fffdcdc align 2**12 filesz 0x000001d0 memsz 0x000055c4 flags rw- The code uses paddr as base, and zeros out everything which is beyond file size. This might overlap into the next section! It seems that memsz is in vaddr space and not paddr... Since zeroing out is not strictly necessary (the firmwares C initialization code should do that anyway) better play safe and don't initialize the empty bytes... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-07-27apalis-tk1: remove non-esential power rails on bootDominik Sliwa
When mainline kernels reboot TK1 they use SW_RESET, that reset mode does not reset PMIC. Some rails need to be off for RAM Re-repair to work correctly. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-19apalis-tk1: apalis_t30: colibri_t30: display reset reasonColibri-iMX7_LXDE-Image_2.8b3.111-20180627Colibri-iMX6_LXDE-Image_2.8b3.111-20180627Colibri-iMX6ULL_LXDE-Image_2.8b3.111-20180627Colibri-VF_LXDE-Image_2.8b3.111-20180626Colibri-T30_LXDE-Image_2.8b3.111-20180627Colibri-T20_LXDE-Image_2.8b3.111-20180626Apalis-iMX6_LXDE-Image_2.8b3.111-20180626Apalis-TK1_LXDE-Image_2.8b3.111-20180626Apalis-TK1-Mainline_LXDE-Image_2.8b3.111-20180627Apalis-T30_LXDE-Image_2.8b3.111-20180626Dominik Sliwa
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-19apalis-tk1: invoking ram_repair before powerup_cpus()Dominik Sliwa
Invoking tegra124_ram_repair() before powerup_cpus() is being invoked to avoid race-conditions if arises further. (based on downstream: fe1c9e4d523d6727afb62f03ef9fa5c0f04e7859) Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-06ARM: vf610: ddrmc: do not write CR79 by defaultStefan Agner
The current value CTLUPD_AREF(0) is the reset value of the register, so there is no need to write a value. If needed, the register can be written using board specific CR settings. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-06ARM: vf610: ddrmc: fix CR138 preprocessor defineStefan Agner
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask to allow setting PHYDRAM_CK_EN correctly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-06ARM: vf610: fix initialization completion detectionStefan Agner
The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-06arm: vf610: add UART2 pinmux/clock supportStefan Agner
Add support for Vybrid's UART2 (Colibri UART_B). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-21arm: dts: imx7: add UART2/UART3Stefan Agner
This allows to change U-Boots default UART by simply changing stdout-path in the device tree. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-21imx: initialize and use generic timer on i.MX 6UL/ULLStefan Agner
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM generic timer. This change makes use of the ARM generic timer in U-Boot. This is crucial to make the ARM generic timers usable in Linux since timer_init() initalizes the system counter module, which is necessary to use the generic timers CP15 registers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-21imx: introduce CONFIG_GPT_TIMERStefan Agner
Introduce a new config symbol to select the i.MX General Purpose Timer (GPT). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-21imx: move CONFIG_SYSCOUNTER_TIMER to KconfigStefan Agner
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-11-27imx: imx6ull: correct get_cpu_speed_grade_hzMax Krummenacher
backport commit 0c7c6fb7641646c45630235ea906200981f4fe80: i.MX6ULL has different speed grades than i.MX6UL. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-11-22MLK-14839-2 imx: clean up print info for thermal and reset causeYe Li
Clean up the print info, so that the reset cause print can display in a new line. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f84b9d512f92b66076357820b1003a1006ff619d)
2017-11-22MLK-14839-1 mx6: Fix wrong CPU frequencyYe Li
Fix incorrect value for 696MHz CPU frequency on i.MX6UL. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 0b70df1d0e888d046cec4bd030c78eb746270ec0)
2017-10-03apalis-tk1: support v1.2 hardware revisionColibri-iMX7_LXDE-Image_2.7b4-20171005Colibri-iMX6_LXDE-Image_2.7b4-20171005Colibri-VF_LXDE-Image_2.7b4-20171005Colibri-T30_LXDE-Image_2.7b4-20171005Colibri-T20_LXDE-Image_2.7b4-20171005Apalis-iMX6_LXDE-Image_2.7b4-20171005Apalis-TK1_LXDE-Image_2.7b4-20171007Apalis-TK1-Mainline_LXDE-Image_2.7b4-20171005Apalis-T30_LXDE-Image_2.7b4-20171005Marcel Ziswiler
Support the V1.2 hardware revision with the following pin muxing changes: Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 are now used as DDC pins. Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are now used as USB power enable signals. Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power enable signals are now used as GPIO3 and GPIO4. Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is loaded on V1.2 and later modules and resp. USB power enable signals activated. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-08-31colibri-imx6ull: add initialMax Krummenacher
The resulting U-Boot boots at least from serial downloader mode. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse settingBai Ping
On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be) (cherry picked from commit 30ce7adebd443ef777e820c4a891cbb3b28ac671)
2017-08-31MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping
Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 911fcf93bad8c0a595c350b92f107b626029559b) Conflicts: arch/arm/cpu/armv7/mx6/soc.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31imx6ull: cherry-pick remaining stuff from 05922b0Max Krummenacher
Not all of the following commit from the nxp vendor tree made it into 2016.11. http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=05922b0abf848949df778c19312cb1cf7fdfbe6a commit 05922b0abf848949df778c19312cb1cf7fdfbe6a Author: Peng Fan <peng.fan@nxp.com> Date: Mon May 9 17:31:34 2016 +0800 MLK-12767 imx6ull: fix runtime checking for i.MX6ULL Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31MLK-12486-1: switch to use setup_gpmi_io_clk for i.MX6ULPeng Fan
Add i.MX6UL support in setup_gpmi_io_clk and change mx6ul_14x14_evk to use it. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit f39d809ef99c3727e17285c52df9cd01020bee65) Conflicts: board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31imx_common: detect USB serial downloader reliablyStefan Agner
The current mechanism using SCR/GPR registers work well when the serial downloader boot mode has been selected explicitly (either via boot mode pins or using bmode command). However, in case the system entered boot ROM due to unbootable primary boot devices (e.g. empty eMMC), the SPL fails to detect that it has been downloaded through serial loader and tries to continue booting from eMMC: Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### The only known way to reliably detect USB serial downloader is by checking the USB PHY receiver block power state... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31imx: add macro to detect whether USB has been initializedStefan Agner
This macro allows to detect whether the boot ROM initialized USB already (serial downloader). This is helpful to reliably detect if the system has been recovered via USB serial downloader. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31imx: imx7: detect USB serial download protocol boot modeStefan Agner
The i.MX 7 boot ROM provides a structure with boot information. The reference manual (chapter 6.6.14 Boot Information for Software in the RM) only lists 6 boot devices, but tests have shown that the boot device type is consistently 0xf in case the SoC has been booted through USB Serial Downloader. Create a new boot mode for the USB Serial Download Protocol (SDP). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31imx: imx7: make get_boot_device available for board filesStefan Agner
The function get_boot_device might be useful in board files, add it to the sys_proto.h header file. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-08-31apalis_t30: describe pcie portsMarcel Ziswiler
Add some more comments describing the various PCIe ports available. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-09-01apalis-tk1: add missing as3722 gpio0 configurationMarcel Ziswiler
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-09-01apalis_t30/tk1, colibri_t20/t30: fix i2c bus frequenciesMarcel Ziswiler
Use a slower speed of 10 kbit/s for DDC to improve reliability. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-08-28apalis-tk1: remove duplicate hdmi_ddc device tree nodeMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-06-05imx: imx-common: add missing memory mapping for OCRAM_SStefan Agner
The OCRAM_S alias for Cortex-M4's system bus is missing. Add the alias so that firmwares which have code linked in that area can be loaded successfully. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Brandon Shibley <brandon.shibley@toradex.com>
2017-05-29apalis/colibri_t30: improve vdd core pmic handlingMarcel Ziswiler
Make sure TPS62362 set 0 defaults to 1.200V as the Linux kernel may switch to set 0 using TPS65911 GPIO1 (EN_CORE_DVFS_N) connected to TPS62362 VSEL1 prior to actually setting it to a sane value dependent on the current CPU frequency. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2017-03-30ARM: vf610: add auxiliary core boot supportStefan Agner
Use i.MX bootaux support introduced for i.MX 6SoloX/i.MX 7 for Vybrid too. Starting the Cortex-M4 core on Vybrid works a bit differently, namely it uses a GPR register to define the initial PC. There is no way to define the initial stack (the stack is set up in a boot ROM). This is not a problem for most firmwares since the firmwares startup code reinitialize the stack as part of the firmware startup code anyway. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-03-30ARM: vf610: move to standard arch/board approachStefan Agner
Move Freescale/NXP Vybrid to a standard arch/board approach, similar to what has been done to i.MX 6 earlier in commit 89ebc82137be ("ARM: mx6: move to a standard arch/board approach"). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-03-30imx: imx-common: add elf firmware supportStefan Agner
Support elf firmware files for the auxiliary Cortex-M4 core. This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (U-Boot is typically running on the A7/A9 core). This allows to boot firmwares from any location with just using bootaux, e.g.: tftp ${loadaddr} low_power_demo.elf && bootaux ${loadaddr} Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-03-30imx: imx-common: move aux core image parsing to common codeStefan Agner
For i.MX 6SoloX/i.MX 7 simple binary files are used to boot the auxiliary CPU core (Cortex-M4). This patch moves the "parsing" of this binary firmwares to the SoC independent code. This allows to add different binary formats more easily. While at it, also move the comment about the inner workings how to boot the Cortex-M4 core to a more appropriate location. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2017-01-18imx_common: check for bmode Serial DownloaderStefan Agner
Before commit 81c4eccb55cc ("imx: mx6: fix USB bmode to use reserved value") a non-reserved value has been used to trigger Serial Downloader using bmode. On some boards this value lead to unreliable bmode command. With the above mentioned commit, U-boot switched to use [7:4] b0001, which translates to GPR9 0x10 for Serial Downloader mode. Check for this new bmode and classify it as Serial Downloader. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-01-18imx_common: introduce serial download protocol boot modeStefan Agner
When starting i.MX SoC's with BOOT_MODE b01, the boot ROM enteres Serial Downloader mode. However, serial download does not necessarily means booting from UART. The boot ROM also supports booting from USB. Create a technology neutral boot mode called SDP (serial download protocol). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-01-11colibri_t20: fix l4t boot hang/errors due to clock initialisationMarcel Ziswiler
Fix the following boot hang observed when booting our downstream L4T R16.5 based BSP: [ 0.900129] kernel BUG at /build/linuxdev/oe-core_V2.7/build/tmp- glibc/work-shared/colibri-t20/kernel-source/drivers/spi/spi-tegra.c:258! [ 0.912478] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP [ 0.919525] Modules linked in: [ 0.922586] CPU: 0 Not tainted (3.1.10-v2.7b1+g7e628fd #1) [ 0.928428] PC is at spi_tegra_isr.part.0+0x14/0x18 [ 0.933310] LR is at spi_tegra_isr+0x38/0x7c [ 0.937580] pc : [<c05c25e8>] lr : [<c0334d4c>] psr: 60000193 [ 0.937585] sp : c8075c40 ip : c8075c50 fp : c8075c4c [ 0.949062] r10: c08a2f20 r9 : c08a2f74 r8 : 00000000 [ 0.954285] r7 : c8074000 r6 : c81545c0 r5 : c08a2f74 r4 : c81545b0 [ 0.960810] r3 : 00000000 r2 : 00000001 r1 : 60000193 r0 : 60000193 [ 0.967336] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel [ 0.974734] Control: 10c5387d Table: 0000404a DAC: 00000015 While at it also fix the following clock initialisation related errors: [ 0.000000] tegra_dvfs: rate 216000000 too high for dvfs on sdmmc1 [ 0.000000] Unable to set clock sdmmc1 to rate 48000000: -22 [ 0.000000] tegra_dvfs: rate 216000000 too high for dvfs on sdmmc3 [ 0.000000] Unable to set clock sdmmc3 to rate 48000000: -22 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2017-01-11apalis/colibri_t30: vdd core pmic handlingMarcel Ziswiler
Just release TPS65911 GPIO1 (EN_CORE_DVFS_N) connected to TPS62362 VSEL1 to switch VDD_CORE back to boot set 1 defaulting to 1.200V. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 622d408fea7af6d2ed778b546de346e90ea1a21f)
2017-01-11colibri_t20: implement early pmic rail configurationMarcel Ziswiler
Implement early TPS6586X PMIC rail configuration setting SM0 being VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts. While those are PMIC power-up defaults the SoC might have been reset separately with certain rails being left at lower DVFS states which is e.g. the case upon watchdog reset while otherwise nearly idling. (cherry picked from commit f7c3186985ebb244d075b04ed7c055f39f485670)
2017-01-11apalis_t30: enable display driverMarcel Ziswiler
Enable the display driver on Apalis T30. Unfortunately the PWM pin muxing wasn't any good neither which made that display stay dark. (cherry picked from commit 2da21c1d130fa11a5bd9876c8e72fa0d57585106)
2017-01-11colibri_t30: enable display driverMarcel Ziswiler
On popular request enable the display driver on Colibri T30. A few notes about some things encountered during porting: While analogue VGA (e.g. via the on-carrier RAMDAC) worked just fine from the beginning the EDT display flickered like crazy which turned out to be a pin muxing issue. Unfortunately the PWM pin muxing wasn't any good neither which made that display stay dark. Enjoy. (cherry picked from commit 201cc6d4e4c8213fbd103e74b0f2f2ca591edf54)
2017-01-11tegra: lcd: video: integrate display driver for t30Marcel Ziswiler
On popular request make the display driver from T20 work on T30 as well. Turned out to be quite straight forward. However a few notes about some things encountered during porting: Of course the T30 device tree was completely missing host1x as well as PWM support but it turns out this can simply be copied from T20. The only trouble compiling the Tegra video driver for T30 had to do with some hard-coded PWM pin muxing for T20 which is quite ugly anyway. On T30 this gets handled by a board specific complete pin muxing table. The older Chromium U-Boot 2011.06 which to my knowledge was the only prior attempt at enabling a display driver for T30 for whatever reason got some clocking stuff mixed up. Turns out at least for a single display controller T20 and T30 can be clocked quite similar. Enjoy. (cherry picked from commit 5a472ddd7a2a017747d6c05c65eba2cd3804c02f)
2017-01-11apalis_t30: comment about disabled pcie nodesMarcel Ziswiler
Add a comment about the disabled PCIe port nodes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit f0adaf95b3edd1e8e23ebb0feab1f86eb77c9d84)
2017-01-11colibri_t20: fix ulpi reset polarityMarcel Ziswiler
Fix ULPI reset polarity which caused a hard hang on Colibri T20 upon attempting to start the USB subsystem: This fixes my late commit d5a24d8b53d350364bd429b7104ec369b817e4b8 (colibri_t20: fix usb operation and controller order) inadvertently having overwritten Stephen's previous commit 2f6a7e8ce5df8b99d84bfd486c6f99d92322ce04 (ARM: tegra: fix USB ULPI PHY reset signal inversion confusion). While at it also fix comment about on-module USB port. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 3f33bd299fd438a04d37c3c25af1ab02a9b0d2f9)
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