Age | Commit message (Collapse) | Author |
|
Introduce weak function board_mem_get_layout() which allows overriding
the memory layout from board code e.g. handy to do our SKU handling.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Clean-up device tree syncing with Linux one as well.
Delete nodes not used by U-Boot.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Change the top-level compatible to use common toradex,apalis-imx8 notation.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Adjust copyright/licensing headers e.g. universally using SPDX license
identifier.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Fix Ethernet functionality. The FEC clock on i.MX 8X really has an
additional by 2 divider plus our design requires the ENET0_RCLK50M_OUT
on the ENET0_RGMII_TXC pin to be turned on for the Micrel PHY.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Fix USB device aka UMS as well as USB host functionality.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Clean-up device tree syncing with Linux one as well.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Fix top-level compatible to use common toradex,colibri-imx8qxp notation.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Adjust copyright/licensing headers e.g. universally using SPDX license
identifier.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
This also enables pullups on the uart forceoff pins.
The UART transceivers on an Iris carrier board can be disabled by
controlling SODIMM pins 102 and/or 104. Make sure that the pins by
default have pullups to have the debug UART working.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 6c2303c6419943e7c81f8ec385c60050a090c7ac)
(cherry picked from commit 7e0886f0a114bf3e81294a5b392855548a3081e8)
Conflicts:
arch/arm/include/asm/mach-imx/sci/types.h
|
|
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 969f430f983d602afd83b6dd75b299e51463eae9)
(cherry picked from commit 2963361493e0f3df76f3a25202a56a76e69fd63f)
|
|
Initial board support for Colibri iMX8QXP using a copy of Apalis iMX8.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 62f0f03e1acb4bb6b0fcca8d4e9bd4d2df04ad33)
(cherry picked from commit be14c3ea1850e2614883c86b62fd1c3a1828eac2)
|
|
NXP LPUART1 is used as Apalis UART1, which is the main console
on our Linux BSP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 360629c1fd6187de19d0f50feb85c725995e49cc)
(cherry picked from commit 63030dac6afc51d17b04d23ce41af4788f03717e)
(cherry picked from commit 7bbe1708e0cebf3432c234ea74f8d6fb632a023b)
(cherry picked from commit d58fa8f3247edc18bdbf716fa9a45bcf5fce9cb8)
|
|
Make sure we return the clock of UART1 when building for
Apalis iMX8. NXP LPUART1 is used as Apalis UART1, which
is typically the main console on our Linux BSP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit f62ce2a12e69b30c4ac6d533b6eef247916bf968)
(cherry picked from commit 53afce50e18bfb12d4a1cdef9e8a8b9272893df3)
(cherry picked from commit d248c3d4c39c24b6f66972f4076cf72b2a5ece1f)
Conflicts:
arch/arm/cpu/armv8/imx8/clock.c, file moved
(cherry picked from commit 4bae89e54bfc8ecda93fac50d2112dc9d762b6fd)
|
|
The Apalis iMX8 module does not have PCA9557 GPIO controllers
on the module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit c80b3bfbe693d5a8851129f4878d0cd3a7325d13)
(cherry picked from commit 898ae105703cd0019a542bc0a17649339c934fa6)
(cherry picked from commit 69d385444efa79d2909f772c4a4b404d1bd7274d)
(cherry picked from commit 0f5887d5b80f8535a7f422b73d7a0bf4a4e445af)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 6c6ac6c8a0107947a9c0952eee65a015c66043a0)
(cherry picked from commit 41602d51fd56396a2647734c530a389d099ee47b)
(cherry picked from commit 73fe13597170f39d943d5dbc67c2416506cf7997)
(cherry picked from commit b8fbd7377cc6e38a90793b01c2a085f85d54a6fa)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit fa3d4f980a515b135778a74ce1b7476f61ef20d0)
(cherry picked from commit 2ee92bc1dd56b44343079a5474d0fc4e79f28f4a)
(cherry picked from commit 649afbe0aec4089112772a49a7e6f7d34c3741a7)
(cherry picked from commit 81591346d11ffdf9a2442ad976390ffe0e61abda)
|
|
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit aa830cb6a7c953ce85232b2ae951543ab1060948)
(cherry picked from commit f6c37cdf31633a541078d0813ab4f59f6b80babb)
(cherry picked from commit ae70d02213beabcd60853f655e2ff9849375c45c)
(cherry picked from commit ba629689c627a571d5902a1c50fe9927424b45c6)
|
|
Initial board support for Apalis iMX8 using a copy of NXP
iMX8QM ARM2 LPDDR4 board.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
(cherry picked from commit 68e401998ba0654292b7914b85433d8453202ec8)
(cherry picked from commit 6b9234fa1f5889f0eeecc6147afffbc859933c99)
(cherry picked from commit 0b7feded806717b4292615373ed6c018324b8ef5)
Conflicts:
arch/arm/cpu/armv8/imx8/Kconfig, file moved
(cherry picked from commit 393dd8dd4061833fcc3cfd85886d49160b515ce0)
|
|
FEC has some clock settings inside DSC GPR. Kernel configures them,
but u-boot not. So when doing partition reset, the GPR keeps the value
from kernel, and cause clock issue to u-boot FEC: kernel enables the
divclk in GPR and set the clock slice to 250Mhz, u-boot configures the
clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz.
Fix the issue by aligning the GPR and clock slice settings with kernel
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit ab6b18bcf3cade15586839274bfde2030726ad37)
|
|
Change the the GIC clock source to sys_pll2_200m.
Improve the IRQ response latency.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit f4c76d52da9c272b275adf26145d033099cd1974)
|
|
The previous LPCG register addresses seem wrong. By checking the LPCG with
JTAG, the ipg_clk, ipg_s_clk, and perclk uses one register as the standard
implementation method, not use 3 registers.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 10f8f616d50f0f13f32a75ed390245d902ae0d9b)
|
|
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 484104758d3c2f98d3c9ae493f778b1427e2630c)
|
|
Each module may have one or more lpcg registers for SW/HW enabling its
clocks. Add lpcg register address and its driver for accessing lpcg.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 19f234266e07c18ab8364336779bf2d3d1f51c81)
|
|
In case ocotp error bit is set, clear it.
This is a workaround to ocotp error bit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 781f2d8febe954b2ef3e51b6a2eebcfbf24b08eb)
|
|
compile waring info is as below:
arch/arm/mach-imx/imx8/parser.c: In function ‘mmc_load_image_parse_container’:
arch/arm/mach-imx/imx8/parser.c:244:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
previouse patch change ID:
I40a791d5b5b1eba6a0170d6853626fb546be4b2c
Change-Id: Ia605df11beab42e720fff6442a11b1e4b25ac209
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
|
|
The SPL loads the FIT image FDT part to an address related with the device
block length. This length is 512 for SD/MMC and is 1 for other devices
like SDP, NOR, NAND, SPI, etc.
When signing FIT image, we use fixed address caculated by SD/MMC block length
to sign FDT part. Thus, when booting through uuu, this causes mismatch and
gets authentication failed.
Fix the issue by providing a override function for this FIT buffer address.
When secure boot is enabled, adjust the addresses of other devices to be same
with SD/MMC.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 710efd3ccb99e144bd30af8e1ee46459b4a54dd6)
|
|
If OP-TEE is loaded by ATF, u-boot will add
optee device tree node in th edtb so that
Linux can loads OP-TEE driver.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 441c23698ffd5c90c6421113da55fae420072473)
|
|
u-boot currently needs information from ATF to know if
OP-TEE os has been loaded.
this information is transmitted via bootargs.
this patch enables saving those bootargs into a structure.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 697cfe9dbdc079b68d8b5685b728a7283c837607)
|
|
To enable SPL+CONTAINER format on android auto with tee, after SPL load
container, SPL need to check rpmb keyblob and copy it to secure memory
for latter use.
Change-Id: I40a791d5b5b1eba6a0170d6853626fb546be4b2c
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
|
|
Some platforms don't have alias for usb1 device, so when initialize the
second controller, its seq is allocated by u-boot automatically.
This introduces a problem if the initialization of first controller is failed,
for example nothing connect to first controller, then the seq allocated
for second controller is 0 not 1. EHCI driver uses the seq as index for
USB controller and phy, so it will cause initialization problem for second
controller.
Fix the issue by adding the usb1 alias for second USB controller.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit fe21a1ab93d0788017ec58905e3273c9ab0f5a67)
|
|
Enable dm usb using the base board otg usb port for fastboot usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
|
|
Enable dm serial for xen uboot.
Log as below:
#xl console 1
MMC: FSL_SDHC: 0
Loading Environment from <NULL>... *** Warning - bad CRC, using default environment
Failed (-5)
In: serial@5a060000
Out: serial@5a060000
Err: serial@5a060000
flash target is MMC:0
Fastboot: Normal
Normal Boot
=>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Update mem map table for xen uboot.
xen console and some magic pages needs to be mappe as normal memory.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Introduce new hypercalls
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Introduce xen header files from Linux Kernel commit
e2b623fbe6a3("Merge tag 's390-4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
|
|
Current flexspi clock root is set to 25Mhz OSC, but the flash can support
to 166Mhz clock, so change the flexspi clock root to system PLL1 100Mhz
clock to increase speed.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Add support for fastboot variable 'at-vboot-state', it's composed
by 6 sub-variable: 'bootloader-locked', 'bootloader-min-versions',
'avb-perm-attr-set', 'avb-locked', 'avb-unlock-disabled' and
'avb-min-versions'.
Test: All 'at-vboot-state' variables are returned
correctly on imx7d_pico and AIY.
Change-Id: Ibb855cbcc7c41657af62dafb98a96c4dfb96ef22
Signed-off-by: Ji Luo <ji.luo@nxp.com>
|
|
Align the callback to ARM64 environment for
Trusty OS.
TEST: AIY-3G & AIY-1G board's TIPC and AVB handler
works.
Change-Id: I65806f56267a4a9278db04a462e351da181618cc
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
|
|
Before parsing the image header, try to check if there is a container and
validate it first. If no (valid) container then as a fall-through parse
the image as before.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
|
|
The check for CONFIG_SPL_SPI_LOAD is fixed, get rid of ret local variable
(that's actually a bug) and fix the length for the spi_flash_read call.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
|
|
According to SCFW API requirement, when setting the clock parent,
the clock must be disabled. Otherwise it will return ERR_BUSY.
When using SPL booting on iMX8QXP, both SPL and regular u-boot will
init the USDHC clock. So the second one in regular u-boot will fail
if we don't disable the clock before setting the parent.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
This intends to replace the FIT image support since that cannot be
authenticated. Instead, we append another container at the end of
flash.bin, this new one containing a new container with two
images representing the ATF and uboot proper.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
|
|
Since from B0 TO, there is a Mirror of JTAG ID register added in
SIM. We can read the part revision from this register.
Update codes to use this register.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|