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2013-01-11colibri_t30: fix MMC/SD card detect GPIOT30_LinuxImageV2.0Beta1_20130314T30_LinuxImageV2.0Alpha1_20130122T20_LinuxImageV2.0_20130305T20_LinuxImageV2.0Beta2_20130129Apalis_T30_LinuxImageV2.0Alpha1_20130315Marcel Ziswiler
The Colibri T30 V1.1 modules actually use a different card detect GPIO.
2013-01-11colibri_t30: migrate to proper machine typeMarcel Ziswiler
After having registered the following proper machine type migrate to actually using it. http://www.arm.linux.org.uk/developer/machines/list.php?id=4493 While at it clean-out some obsolete Cardhu specific device-tree nodes resp. properties and clean-up the mach-types header file as well.
2012-12-19toradex: common: clean-up board fileMarcel Ziswiler
This is a purely cosmetic clean-up of the common Toradex board file.
2012-12-13colibri_t20: add optional 800x480 timingMarcel Ziswiler
Add optional aka commented out 800x480@60 timing suitable for EDT ET070080DH6.
2012-12-04colibri_t30: USB: fix Ethernet detection faultMarcel Ziswiler
Turns out our simplistic approach of just blindly enabling LAN_V_BUS and releasing LAN_RESET_N does not prove very reliable. Properly resetting the chip for 5 microseconds after VBUS is stable just like we do on the Colibri T20 seems to fix the issue.
2012-12-04colibri_t20/colibri_t30: device tree compatibility matchingMarcel Ziswiler
Include "colibri_" prefix in our board compatibility tables in preparation to properly distinguish future e.g. Apalis modules. While at it bring the device tree matching more in par with Linux kernel 3.1.10 from NVIDIA's L4T R16-R2.
2012-11-28T30:Max Krummenacher
- board.c: changes required by different PMIC variant
2012-11-28T30: - exclude T20 RAM sizeMax Krummenacher
2012-11-09colibri_t20: USB: fix Ethernet detection faultMarcel Ziswiler
Turns out we completely missed properly resetting the ASIX USB to FastEthernet chip which from time-to-time on certain modules caused severe Ethernet detection faults only a complete hardware reset or power-cycle could eliminate. Properly resetting the chip for 5 microseconds after VBUS is stable seems to fix the issue.
2012-10-31colibri_t20: nand: fix NVIDIA partition table parsingMarcel Ziswiler
If the USR partition we usually mount as root file system could not be found which is e.g. the case for Android make sure mtdparts does not start with a spurious coma separator the kernel would interpret as an empty partition entry.
2012-10-30Merge branch 'chromeos-v2011.06' into colibriMarcel Ziswiler
Conflicts: arch/arm/cpu/armv7/tegra3/warmboot_avp.c arch/arm/include/asm/arch-tegra/clk_rst.h
2012-10-24colibri_t30: fix buildMarcel Ziswiler
Fix build issues introduced with NVIDIA partition table parsing integration.
2012-10-18colibri_t20: fix SD bootT20_LinuxImageV2.0Alpha2_20121019Marcel Ziswiler
If booting from SD card BCT contains information specific to SD card partition layout which is bogus if used for NAND partition parsing. Simply fall back to default offset just like in recovery BCT case. Note: in the future we could parse SD partition table as well to more generically support SD booting from various card densities.
2012-10-18colibri_t20: nand: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2012-10-18colibri_t20: nand: integrate NVIDIA partition table parsingMarcel Ziswiler
NVIDIA's NAND layout includes a partition table that can be used to generically construct the mtdparts kernel boot argument. As an added benefit this is completely independent of the underlying NAND part used which differs with various module versions. It further allows our customer easy adoption to their own custom partition layout. Initial partition table parsing courtesy of Mitja Špes from LXNAV.
2012-09-26colibri_t20: activate backlight gpioMarcel Ziswiler
Activate BL_ON backlight GPIO PT4 on SODIMM pin 71. While at it add commented out XGA 1024x768 display timing values as well.
2012-08-22Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808Marcel Ziswiler
2012-07-18tegra: fdt: Change load entry to 0x1080000Jimmy Zhang
Change tegra2's entry address to its default address 0x108000. BUG=none TEST=flashed with local built u-boot. Kernel boots up fine. Change-Id: I6ff4ed1f2901df73b21d033fbd191550108e96b5 Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/22171 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-04-25Provide alternative config for netbootingVadim Bendebury
This change allows to build a customized u-boot image, which includes networking capabilities, provides diagnostic commands and supports command line editing. These features are necessary to facilitate the factory flow. This image needs to be clearly distinguishable by ChromeOS. This is achieved by modifying the value presented by the BINF.3 ACPI object. To build this modified image one needs to add BUILD_FACTORY_IMAGE=1 to the make invocation line. BUG=chrome-os-partner:7952 TEST=manual . build the new firmware image as follows: USE='pcserial factory-mode' emerge-link chromeos-u-boot \ chromeos-coreboot chromeos-bootimage . program the new image on the Link target with ChromeOS installed on the SSD and restart it . observe the target stop at u-boot command prompt (boot >) . connect the target to an Ethernet network with a DHCP server using a USB Ethernet dongle . run the following commands at the u-boot prompt boot > usb start (Re)start USB... USB: Register 203007 NbrPorts 7 USB EHCI 1.00 Register 20400b NbrPorts 11 USB EHCI 1.00 8 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found scanning bus for ethernet devices... 1 Ethernet Device(s) found boot > dhcp Waiting for Ethernet connection... done. BOOTP broadcast 1 BOOTP broadcast 2 [a few warnings of unsupported DHCP options] DHCP client bound to address 172.22.75.25 Using asx0 device TFTP from server 172.16.255.7; our IP address is 172.22.75.25; sending through gateway 172.22.75.254 Filename 'pxelinux.0'. Load address: 0x100000 Loading: ## done Bytes transferred = 15840 (3de0 hex) boot > . start ChromeOS on the target by issuing vboot_twostop . once ChromeOS boots check the mainfw_type crossystem reported value localhost ~ # echo $(crossystem mainfw_type) netboot localhost ~ # Change-Id: I1c50517754b6b5f773e432b9adec4b290f303e6f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/21071 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-03-21Increase size of MRC cache on LinkStefan Reinauer
Link's MRC produces significantly more training data than the one used on Stumpy/Lumpy. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none TEST=boot tested on Link Change-Id: I9310c3bcc77fb4318db0635b97b115ab0eb7e5ec Reviewed-on: https://gerrit.chromium.org/gerrit/18748 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-03-19x86: Make RW unused section labels uniqueDuncan Laurie
BUG=none TEST=check fmap on generated binary for unique names Change-Id: Id1ac5cf223ec6a333fc8f4c587e972afd087f90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18435 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-16Reduce RW BIOS data sections to 512K from 976KDuncan Laurie
This saves 500ms in the RW BIOS path and still leaves 130K overhead from the current U-boot size (372K) which should be more than enough for any future updates on stumpy/lumpy. This should be re-visited if/when vboot is smart enough to just read+validate the actual binary within the section. BUG=chrome-os-partner:8518 TEST=boot lumpy/stumpy through RW BIOS path and gather timestamps to see 500ms improvement. Change-Id: Ia714b4b95245f02f6e781247f820ca915bb403f5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18372 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-15Use keyboard controller for hard reset instead of CF9Vadim Bendebury
For some still unknown reason writes to localtion 0xcf9 do not cause the Link to reboot, they cause it to shut down instead. While this will have to be investigated and fixed, this change modifies the code to use the keyboard controller (implemented by the EC on Link) to restart the system. Once the 0xcf9 problem is resolved, this change could be reverted. BUG=chrome-os-partner:8397 TEST=manual . when u-boot tires restarting the system it now reboots. before this change it would just shut down. Change-Id: I8076f897304f705e20ec8f2e30cce17d7fdd31c4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18332 Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2012-03-15arm: Tegra3: pass board id through the dts filesVarun Wadekar
BUG=chromium-os:23496 TEST=build on Waluigi, Seaboard, Cardhu Change-Id: I9ccd3085fb551e9887815592e9b518b6944beda7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14474 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-03-13x86: Add an emeraldlake2 device treeGabe Black
BUG=chrome-os-partner:8180 TEST=Built u-boot for emeraldlake2. Change-Id: Iae62f047ddc102fbf530e1f8f9af34939971a6a3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18057 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-03-08tegra: Remove keyboard support from fdtSimon Glass
This uses a format which is not supported by the upstream dtc, so remove this. BUG=chromium-os:23249 TEST=emerge-tegra2_kaen chromeos-u-boot with new dtc Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I18b9420dbee20c2d115cc5ff1b13425faffe2a3e Reviewed-on: https://gerrit.chromium.org/gerrit/17630
2012-02-28Don't ever return from cold_reboot() functionStefan Reinauer
cold_reboot() should wait until the reset kicks in, instead of returning and continuing in an undefined code path. Without this patch, vboot_twostop will return, and secure_boot() will start printing an error message, which results in a sporadic # on the screen when pressing space or ESC on the dev screen in order to go to recovery mode. BUG=chrome-os-partner:7683 TEST=boot to dev screen on lumpy, press ESC or space. Observe there is no # character printed before going to recovery mode. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic2ee570032686e48603f0fb3b1ec9cbfae9451bc Reviewed-on: https://gerrit.chromium.org/gerrit/17007 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
2012-02-27Add flag fast-developer-mode to make default developer mode time on x86 2sStefan Reinauer
This will trigger setting gbb.flags to 1 in cros_bundle_firmware so the factory time is reduced. GBB.flags will be changed in the factory process. Also needs https://gerrit.chromium.org/gerrit/#change,16845 BUG=chrome-os-partner:7671 TEST=manual emerge-stumpy chromeos-bootimage gbb_utility -g --flags /build/stumpy/firmware/image.bin Should report "flags: 0x00000001" Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie05433ad737005bd5dcca2f88232b0a5bbd00df9 Reviewed-on: https://gerrit.chromium.org/gerrit/16113 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
2012-02-14arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Ie04bf9ac17482a37afd0f4515dc3aafeb4f48ae7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15883
2012-02-08Revert "arm: tegra2: split LP0 code to help future chips"Brian Harring
This reverts commit 4c7502242627f64d91432cb4958be5f93f65fbff Don't think this is the cause of http://code.google.com/p/chromium-os/issues/detail?id=26116, but it was in the same batch so I'm reverting in the process. Change-Id: Icc013ced6c22e29d569ee4ca8ef73522154ec1a8 Reviewed-on: https://gerrit.chromium.org/gerrit/15561 Reviewed-by: Brian Harring <ferringb@chromium.org> Tested-by: Brian Harring <ferringb@chromium.org>
2012-02-08arm: tegra2: split LP0 code to help future chipsVarun Wadekar
split the LP0 code for tegra2 into common LP0 code and chip specific warm boot code BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13799
2012-02-07tegra3: fdt: change lcd frame buffer addressPuneet Saxena
For Waluigi, existing frame buffer address does not fall under external memory map. Setting it to the location set as per the default initialization. BUG=chromium-os:23496 TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi. Change-Id: I2284d43c11f4d6622344429508b1f99e30929f19 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14698
2012-02-07tegra: Rename "CONFIG_VIDEO_TEGRA2" to "CONFIG_VIDEO_TEGRA"Puneet Saxena
Enables common LCD support for Tegra2 and Tegra3 BUG=chromium-os:23496 TEST=Built ok for Cardhu, Waluigi and Seaboard. Change-Id: I938824045440cc4964c2ac6bf727a90ee5f129b4 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14692
2012-02-06tegra3: fdt: Add Waluigi keyboard mapPuneet Saxena
Add Waluigi keyboard map in Waluigi fdt BUG=chromium-os:23496 TEST=Build and tested on Waluigi. Change-Id: Iaf39dabc2bef2f12c2f0b875cc3c397386dbb446 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13929 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-06tegra3: fdt: Add Tegra30 keyboard controller definitionPuneet Saxena
Add Keyboard controller option in tegra30 fdt. BUG=chromium-os:23496 TEST=Build ok for Waluigi, Seaboard and Cardhu. Change-Id: I20fe7feed42a96edea138dc32c532e0d1d535226 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14546 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-06tegra: change Keyboard config namePuneet Saxena
Rename CONFIG_TEGRA2_KEYBOARD to common CONFIG_TEGRA_KEYBOARD BUG=chromium-os:23496 TEST=Build OK for Waluigi, Cardhu and Seaboard. Change-Id: Ice2741622fe6434ba25ece8fe7fbe2ca989c44ef Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13930 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-02-06Arm: tegra3: Add 16x8 keyboard supportPuneet Saxena
Expand existing 4x6 keyboard support to 16x8 keyboard. Add Tegra2 specific changes under Tegra2 config "CONFIG_TEGRA2". BUG=chromium-os:23496 TEST=Tested on Waluigi.key press echoes the key on console. Built ok for Cardhu and Seaboard. Change-Id: Iab291a636d41b721d914014a5fe9ecc8775bf260 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13928 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-19Enable frequency selection in VbExBeep().Bill Richardson
BUG=none TEST=manual In dev-mode, press "Ctrl-U" with no USB stick inserted. If "crossystem dev_boot_usb" is 0, you'll hear two 400Hz beeps. If "crossystem dev_boot_usb" is 1, you'll hear one 200Hz beep. Signed-off-by: Bill Richardson <wfrichar@google.com> Change-Id: Ifd45a067ec8b922863331f13f3f4525ef40f7346 Reviewed-on: https://gerrit.chromium.org/gerrit/14529 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Bill Richardson <wfrichar@chromium.org>
2012-01-12CHROMIUM: x86: Align the header for the MRC data cache.Duncan Laurie
This is to match a change made in coreboot to align both the header and the data to 16 bytes. BUG=none TEST=several cold boots to ensure that the MRC data cache is not written out on every boot. Change-Id: I6c9a01933264d6bd65958ddb93e8944c35e853c6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/14096 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-09[x86]: Add environment section to flash map.Stefan Reinauer
dev_cfg is used by vboot_reference, hence we can't store our u-boot environment there anymore. So create a section rw-environment for that purpose. Signed-off-by: Stefan Reinauer <reinauer@google.com> BUG=chrome-os-partner:7264 TEST=boot tested on Stumpy Change-Id: I15479f0f1a2aa111b742d2792052f48d660d122c Reviewed-on: https://gerrit.chromium.org/gerrit/13022 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
2012-01-05tegra: Use board_late_init() to finalize LCD initSimon Glass
We need to make sure that the LCD is ready before we complete booting, so put this code into board_late_init(). BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I97bd1fce6ac93d0639dd8fdb17bf83e8a78d2645 Reviewed-on: https://gerrit.chromium.org/gerrit/13213 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-05tegra: Tidy up LCD init code to use a state machineSimon Glass
The LCD init takes place over five stages. We want to hide this init behind other operations, so turn it into a state machine which we can call at any time. For now, call it in lcd_enable(). BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Ia0b50ec74108ac4e015de12b7a9628426ea17656 Reviewed-on: https://gerrit.chromium.org/gerrit/13211 Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2012-01-03CHROMIUMOS: Issue SMI to finalize Coreboot in final stageDuncan Laurie
This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. BUG=chrome-os-partner:6609 TEST=boot on stumpy+celeron and lumpy+i5 and ensure the system still boots and that registers are locked Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ib30ea83044f5123205531a5e8ee88ee37de2dd86 Reviewed-on: https://gerrit.chromium.org/gerrit/13604 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-01-03CHROMIUMOS: Add U-boot support for wear-leveling the MRC dataDuncan Laurie
- Depends on related Coreboot changes - There is a 64k region allocated so use it all - Write each data blob in a 4K aligned container - Find the last entry in the region to compare against coreboot copy - Detect a full region and erase it all and start over at zero BUG=chrome-os-partner:6962 TEST=manual I started writing an autotest for this, but it was taking more time than just doing a thorough manual test. I will finish the autotest but for now I relied on manual testing and using /sys/firmware/log to tell what happened in Coreboot/U-boot on each boot. TEST CASE 1 - newly flashed image: 1) Install the new bios with flashrom and reboot 2) Check that no MRC data was found by Coreboot in firmware log: "prepare_mrc_cache: invalid MRC data" 3) Check that U-boot wrote training data in firmware log: "handle_mrc_cache: cached storage mismatch (-1/2895)" "firmware_storage_spi: before adjustment" "firmware_storage_spi: offset: 0x1ec000" "firmware_storage_spi: length: 0xb58" "firmware_storage_spi: after adjustment" "firmware_storage_spi: offset: 0x1ec000" "firmware_storage_spi: length: 0x1000" "firmware_storage_spi: offset: 0x001ec000" "firmware_storage_spi: adjusted offset: 0x001ec000" 4) Check the flash to see if it has data in first slot > flashrom -r /tmp/bios.now > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now TEST CASE 2 - ensure that it uses the saved training data: 1) Reboot 2) Check that Coreboot used the training data in firmware log: "prepare_mrc_cache: at ff9ec009, entry 0 size b4f checksum 9c" 3) Check that U-boot did not have to update the data in firmware log: "handle_mrc_cache: cached storage match" 4) Check the flash to see if it still only has data in first slot: > flashrom -r /tmp/bios.now > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now TEST CASE 3 - ensure that it fills the next slot with new data: 1) Corrupt the seed checksum in CMOS: > io_write8 0x70 0x78 > io_write8 0x71 0x00 2) Reboot 3) Check that Coreboot did not use cached data in firmware log: "prepare_mrc_cache: invalid seed checksum" 4) Check that U-boot wrote new training data at new offset in firmware log: "handle_mrc_cache: cached storage mismatch (2895/2895)" "firmware_storage_spi: before adjustment" "firmware_storage_spi: offset: 0x1ed000" "firmware_storage_spi: length: 0xb58" "firmware_storage_spi: after adjustment" "firmware_storage_spi: offset: 0x1ed000" "firmware_storage_spi: length: 0x1000" "firmware_storage_spi: offset: 0x001ed000" "firmware_storage_spi: adjusted offset: 0x001ed000" Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifffce29c5f9324f110c047a44a3f66d2e21cd6a4 Reviewed-on: https://gerrit.chromium.org/gerrit/13589 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
2011-12-31CHROMIUMOS: x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie
Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. BUG=chrome-os-partner:7350 TEST=boot 4GB stumpy with coreboot MTRR fixes and verify that U-boot does not clear MTRR 7 but does clear MTRR 9. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id6927325131b0b88043daa320a17847764626c0d Reviewed-on: https://gerrit.chromium.org/gerrit/13477 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2011-12-21tegra: Implement CONFIG_DELAY_CONSOLESimon Glass
Add plumbing to support this option to delay console init until after relocation. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: Iee3be9e2d0b51e6cf2f45a4408bfdde494c97d8b Reviewed-on: https://gerrit.chromium.org/gerrit/13210 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org>
2011-12-21tegra: Refactor serial init codeSimon Glass
Move the serial init code into its own function to collect this all in one place. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I70162d836fddfabedd9cfbc07d8f0dc920602af8 Reviewed-on: https://gerrit.chromium.org/gerrit/13204 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20CHROMIUM: config: Switch Kaen to 8-bit eMMCSimon Glass
We can support 8-bit eMMC and it is faster, so turn it on. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I1509594832d317a086fa066d1a37c78a1a52c7c3 Reviewed-on: https://gerrit.chromium.org/gerrit/13201 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2011-12-20tegra: mmc: Support 8-bit wide interface for eMMCSimon Glass
The Tegra2 can support this faster interface, so use it. It can reduce data transfer time by about 40%. BUG=chromium-os:22938 TEST=build and boot on Kaen Change-Id: I656773c83083cd53d3ee52433e324e73fbcdc999 Reviewed-on: https://gerrit.chromium.org/gerrit/13200 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2011-12-19tegra: Skip NAND init if fdt indicates it is not activeSimon Glass
This allows NAND to be disabled from the fdt easily. BUG=chromium-os:22938 TEST=build and boot on Kaen Signed-off-by: Fred Signed-off-by: John Change-Id: Ibf9259f8621e73fcf943f54a20327513288fef06 Reviewed-on: https://gerrit.chromium.org/gerrit/12913 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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