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path: root/drivers/pinctrl
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2022-04-06MLK-21847 pinctrl: imx8/imx8m: Remove DEVRES selectingYe Li
The CONFIG_DEVRES is not a necessary config for pinctrl. We decouple the dependence from the kconfig. So the DEVRES is not default enabled. When using USB gadget driver like CDNS3 or DWC3, without enabling gadget DM driver, the calling to devm_kzalloc will cause crash if CONFIG_DEVRES is set. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit baeed1c2a36c07126e35a3cdb34f4f392e88c939) (cherry picked from commit 09ca00f7870374658f98ffc1952a2c617e4403e2) (cherry picked from commit 3a724d7fb23a36dd7ed02701df2cda822bdef075)
2022-03-15pinctrl: k210: Fix bias-pull-upNiklas Cassel
Using bias-pull-up would actually cause the pin to have its pull-down enabled. Fix this. Original Linux patch by Sean Anderson: https://lore.kernel.org/linux-gpio/20220209182822.640905-1-seanga2@gmail.com/ Fixes: 7224d5ccf8e1 ("pinctrl: Add support for Kendryte K210 FPIOA") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15pinctrl: k210: Fix loop in k210_pc_get_drive()Niklas Cassel
The loop exited too early so the k210_pc_drive_strength[0] array element was never used. Original Linux patch by Dan Carpenter: https://lore.kernel.org/linux-gpio/20220209180804.GA18385@kili/ Fixes: 7224d5ccf8e1 ("pinctrl: Add support for Kendryte K210 FPIOA") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: dts: align fpioa node with LinuxDamien Le Moal
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the power bit offset of the fpioa device to be specified as a single property "canaan,k210-sysctl-power". Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset" properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel requirements. This new property is parsed using the existing function dev_read_phandle_with_args(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: use the board vendor name rather than the marketing nameDamien Le Moal
"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-04arm64: a37xx: pinctrl: Fix PWM pins indexesMarek Behún
Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins definitions") introduced bogus definitions os PWM pins: all 4 pins have index 11, instead of having indexes 11, 12, 13, 14. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-19doc: replace @return by Return:Heinrich Schuchardt
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-18pinctrl: single: add support for pinctrl-single, pins when #pinctrl-cells = 2AJ Bagwell
Changes to the am33xx device (33e9021a) trees have been merged in from the upstream linux kernel which now means the device tree uses the new pins format (as of 5.10) where the confinguration can be stores as a separate configuration value and pin mux mode which are then OR'd together. This patch adds support for the new format to u-boot so that pinctrl-cells is now respected when reading in pinctrl-single,pins Signed-off-by: Anthony Bagwell <anthony.bagwell@hivehome.com>
2021-11-30pinctrl: stmfx: define LOG_CATEGORYPatrick Delaunay
Define LOG_CATEGORY to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-29Merge tag 'v2022.01-rc3' into nextTom Rini
Prepare v2022.01-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-19pinctrl: meson: Correct the driver GPIO declarationSimon Glass
This should use the provided U_BOOT_DRIVER() macro so that the driver gets added to the appropriate linker list. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 7c9dcfed50f ("pinctrl: meson: rework gx pmx function") Reported-by: Tom Rini <trini@konsulko.com> Tested-by: Tom Rini <trini@konsulko.com> on libretech-cc Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-17pinctrl: Add Apple pinctrl driverMark Kettenis
This driver supports both pin muxing and GPIO support for the pin control logic found on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17aspeed: AST2600 Pinctrl DriverRyan Chen
This driver uses Pinctrl framework and is compatible with the Linux driver for AST2600. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-09exynos78x0: pinctrl: set const to structsMinkyu Kang
to fix following checkpatch warings. WARNING: struct should normally be const Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-31SoC: exynos: add support for exynos 78x0Dzmitry Sankouski
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31pinctrl: exynos: add support for multiple pin banksDzmitry Sankouski
Iterate all pin banks to find a pin Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-05pinctrl: single: Add request() apiBharat Gooty
Add pinctrl_ops->request api to configure pctrl pad register in gpio mode. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05pinctrl: single: Parse gpio details from dtBharat Gooty
Parse different gpio properties from dt as part of probe function. This detail is required to enable pinctrl pad later when gpio lines are requested. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-14pinctrl: fix typoYuan Fang
fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
2021-08-09pinctrl: Add pinctrl driver for imx8ulpYe Li
Add pinctrl driver for i.MX8ULP Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-02global: Convert simple_strtoul() with decimal to dectoul()Simon Glass
It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-31arm64: a37xx: pinctrl: Correct PWM pins definitionsMarek Behún
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-28Rename GPIO_SUPPORT to GPIOSimon Glass
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-15pinctrl: Avoid coverity warning when checking widthSimon Glass
The width is set up in single_of_to_plat() and can only have three values, all of which result in a non-zero divisor. Add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 331154)
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini
various minor sandbox improvements
2021-07-07pinctrl: mscc: Fix multiple definition errorTom Rini
With gcc-11 we get a multiple errors here as the declarations for mscc_pinctrl_ops and mscc_gpio_ops are missing an extern. CC: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Lars Povlsen <lars.povlsen@microchip.com> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-24pinctrl: renesas: Import R8A779A0 V3U PFC tablesMarek Vasut
Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Add parts of PFC table integration from pinctrl: renesas: Add R8A779A0 V3U PFC tables by Hai Pham <hai.pham.ud@renesas.com>" . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-07pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.12Marek Vasut
Synchronize R-Car Gen2/Gen3 pinctrl tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . This is a rather large commit, since the macros in sh-pfc.h also got updated, so all the PFC tables must be updated in lockstep. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-26pinctrl: single: Fix probe failure getting register area sizeVignesh Raghavendra
If reg property of pinctrl-single node requires address translation then probe fails with following message: single-pinctrl pinctrl@4301c000: failed to get base register size This is because driver uses dev_read_addr_size() to get size which also tries to fetch untranslated addr and fails. Fix this by using dev_read_addr_size_index() which takes care of address translation and also makes following dev_read_addr() call redundant. This fixes Ethernet failures on TI's AM654 based EVMs due to lack of pinmux configuration. Fixes: 9fd8a430f3 ("pinctrl: single: get register area size by device API") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-21pinctrl: renesas: Implement unlock register masksMarek Vasut
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21pinctrl: renesas: Fix R-Car Gen2 help textMarek Vasut
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21pinctrl: renesas: Deduplicate KconfigMarek Vasut
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-27pinctrl: single: fix a never true comparisonDario Binacchi
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero' comparison of an unsigned value is never true. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-27pinctrl: single: check function mask to be non-zeroDario Binacchi
Otherwise it can generate a division by zero, which has an undefined behavior. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-18Merge tag 'ti-v2021.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Support for pinmux status command on beaglebone - Updates for MMC speed modes for J721e-evm - Fix MMC booting on omap35_logic_somlv board
2021-04-12test: pinmux: add test for 'pinctrl-single' driverDario Binacchi
The test adds two pinmux nodes to the device tree, one to test when a register changes only one pin's mux (pinctrl-single,pins), and the other to test when more than one pin's mux is changed (pinctrl-single,bits). This required replacing the controller's register access functions when the driver is used on sandbox. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: add get_pin_muxing operationDario Binacchi
It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: add get_pin_name operationDario Binacchi
It returns the name of the requested pin. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: add get_pins_count operationDario Binacchi
It returns the number of selectable pins. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: add register access functionsDario Binacchi
The configuration of pinmux registers was implemented with duplicate code which can be removed by adding two functions for read/write access. Access to 8-bit registers has also been added. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: change function mask default valueDario Binacchi
The patch is inspired by more recent versions of the Linux driver. Replacing the default value 0xffffffff of the function mask with 0 is certainly more conservative in case the "pinctrl-single,function-mask" DT property is missing. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12pinctrl: single: check "register-width" DT propertyDario Binacchi
In more recent versions of the Linux kernel the driver's probe function returns an error if the "pinctrl-single,register-width" DT property is missing. The lack of this information, in fact, does not allow to know whether to access the registers of the controller at 8, 16, ... bits. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
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