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path: root/drivers/spi
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2018-11-02MLK-20157 spi: mxc_spi: Fix build warning on ARM64 platformsYe Li
When building mxc_spi driver on ARM64 platforms like iMX8MM, get such build warnings below. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-10-29MLK-20107 fspi: Keep the module enabled after probeYe Li
In flexspi driver, each sf command will disable the module in release bus function. So reading from flexspi memory-map address using "md" command can't work. When iMX8MM kicks M4 image to run flexspi NOR XIP, this causes problem. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-05-31MLK-18455 mxc_spi: Fix issue for DM driverYe Li
Since the fdt API is changed, update to use devfdt_get_addr. Otherwise, build the DM SPI will fail. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-05-23MLK-18243-15 spi: fspi: Fix 3bytes accessYe Li
The address size is 3 bytes when using BAR mode, but the driver supposes the 4bytes mode is enabled and uses 4 bytes address. This cause address issue. Also the mask needs set to 23bits for 3 bytes address. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 2e9a9e0fe379306f7c1065f9afa9e67386be2503)
2018-05-23MLK-18243-14 spi: fspi: init unused LUT to 0Peng Fan
If not initialize unused LUT to 0, the value is random which might cause qspi command failure. On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on i.MX8MM, ROM not initialize them, so let's do it here. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318)
2018-04-27MLK-16118-7 spi: flexspi: Add init_clk_fspi function to setup clockYe Li
When the power domain driver is enabled, we need to enable clocks after power domain on. The clock settings in board level codes must be removed, needs to set them when the device is probed. Add this weak function in flexspi driver, that SoC codes can implement the clock settings. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a4d334e70839021a50dca2ad4ad98ecee16081f9)
2018-04-27MLK-16186: spi: flexspi: reset the flexspi DLL register to default valueHan Xu
i.MX8QM ROM didn't calculate the DLL correctly in some cases, to avoid the wrong DLL setting impact the following functions, reset them to the default value when probe. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit da3c2a9f09afa45a428809b7bf3f981a1ccb7f2e)
2018-04-27MLK-15958-2 spi: fsl_fspi: Add support for 4bytes address modeYe Li
Update the LUT settings, spi_xfer to use the 4bytes address read/write/erase commands. Also add a function to enter the 4bytes mode for flash device. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 704c1c357d5566e6b3a72c57427d90ba08f9ef0f)
2018-04-27MLK-14938-19 spi: Add FlexSPI Driver for i.MX8QMYe Li
Add fsl_fspi driver for flexspi controller. This driver supports: 1. DDR Quad output 2. Prefetch function for improve read performance. 3. Fast read and Quad read for one line read mode. 4. Read flash FSR register. 5. DM. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
2018-04-27MLK-18159-2 fsl_qspi: Add support for i.MX8MYe Li
The i.MX8M reuses the QSPI controller from i.MX7D. Add the CONFIG_IMX8M define to the driver. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-04-27MLK-12483-4 mx6: Modify drivers to disable fused modulesYe Li
Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF and EPDC. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e) (cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
2018-04-27MLK-17656: mtd: qspi: support read the flag status in fspi driverHan Xu
support to read the flag status in driver to avoid the spi-nor framework wait_for_ready hang issue. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d)
2018-04-27MLK-14878 qspi: Fix issue when enabling DDR modeYe Li
There are two problems in enabling DDR mode in this new driver: 1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't cause explicit problem. 2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift. So these operations will fail. The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error after using DDR mode QSPI boot on 6UL/ULL EVK boards. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 16270556212e6c7422e87f69572c90f1afe6998b)
2018-04-27MLK-13450-16 fsl_qspi: Update changes for mx7ulpYe Li
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes) than other i.MX. Change some parameters for it. Also found when the DDR_EN bit is set, sometime the page programming will fail during large data programming. The 64 bytes data is not programmed into flash. But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue. We have disable the DDR_EN for mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5a69ddb7e9886e082da42ddf673415702975ee60)
2018-02-13spi: Migrate CONFIG_CF_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_KIRKWOOD_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_LPC32XX_SSP to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MPC8XXX_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXC_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXS_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_QSPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-07atcspi200: avoid possible NULL dereferenceHeinrich Schuchardt
Check if ns before and not after dereferencing it. Indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini
2018-01-26DW SPI: Get clock value from Device TreeEugeniy Paltsev
Add option to set spi controller clock frequency via device tree using standard clock bindings. Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API and implement dw_spi_get_clk their own way in their clock manager. Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead) Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_qspi_apb: Make flash writes 32 bit alignedVignesh R
Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 bit aligned buffers. This is required because as per TI K2G TRM[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer. Otherwise indirect writes is known to fail sometimes. [1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when ↵Vignesh R
possible" This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. Using bounce_buf.c to handle non-DMA alignment problems is bad as bounce_buf.c does cache manipulations which is not required. Therefore revert this patch in favour of local bounce buffer solution in the next patch. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when ↵Goldschmidt Simon
possible" This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates the data cache after reading. This is meant for dma transfers only and breaks the cadence_qspi driver which copies via cpu only: data that is copied by the cpu is in cache only and the cache invalidation at the end throws away this data. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_spi: Sync DT bindings with LinuxJason Rush
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24spi: kirkwood_spi: implement workaround for FE-9144572Chris Packham
Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: spi-uclass: Fix style violationsMario Six
Remove a superfluous newline, and reduce the scope of a variable. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove spi_setup_slave_fdtMario Six
A previous patch removed the spi_flash_probe_fdt function, which contained the last call of the spi_setup_slave_fdt function, which is now equally obsolete. This patch removes the function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove obsolete spi_base_setup_slave_fdtMario Six
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node") added a helper function spi_base_setup_slave_fdt to to set up a SPI slave from a given FDT blob. The only user was the exynos SPI driver. But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed the use of this function, hence rendering it obsolete. Remove this function, as well as the CONFIG_OF_SPI option, which guarded only this function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Fix style violation and improve codeMario Six
This patch fixes a printf specifier style violation, reduces the scope of a variable, and turns a void pointer that is used with pointer arithmetic into a u8 pointer. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx HSSPI driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx SPI driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-22Convert CONFIG_DAVINCI_SPI to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_DAVINCI_SPI Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-12spi: fsl_qspi: support i.MX6UL/6ULLL/7DPeng Fan
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-11-30cosmetic: atcspi200: Rename function name as atcspi200Rick Chen
Integrate function and struct name from ae3xx to atcspi200 will be more reasonable. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spiRick Chen
atcspi200 is Andestech spi ip which is embedded in AE3XX and AE250 platforms. So rename as atcspi200 will be more reasonable to be used in different platforms. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-21rockchip: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-20omap3: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-27spi: ich: Lock down controller settings if requiredBin Meng
Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's bootloader's responsibility to configure the SPI controller's opcode registers properly otherwise SPI controller driver doesn't know how to communicate with the SPI flash device. Rather than passively doing the opcode configuration, let's add a simple DTS property "intel,spi-lock-down" and let the driver call the opcode configuration function if required by such FSP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-16spi: Drop CONFIG_ATMEL_DATAFLASH_SPITuomas Tynkkynen
Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29spi: davinci_spi: Add da830-spi support for DMAdam Ford
The DM support is already in the driver, so add da830-spi to the compatible list. Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-25spi: fsl_qspi: Copy 16 byte aligned data in TX FIFOSuresh Gupta
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: fsl_qspi: Add controller busy check before new spi operationSuresh Gupta
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: mxc_spi: support driver modelPeng Fan
Add driver model support for mxc spi driver. Most functions are restructured to be reused by DM and non-DM. Tested on mx6slevk/mx6qsabresd board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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