Age | Commit message (Collapse) | Author |
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Conflicts:
arch/arm/cpu/armv7/tegra3/warmboot_avp.c
arch/arm/include/asm/arch-tegra/clk_rst.h
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- Fix bug in traversal of vendor name list.
- Sending "command ready" needs additional logic to handle
TPMs that need that bit set twice: once to empty the read
FIFOs and once to actualy set command ready.
- Certain TPMs need a small delay between requesting locality
and attempting to set command ready or they will hang the bus.
BUG=chrome-os-partner:8558
TEST=manual
Successful boot and suspend/resume with all TPMs listed
in the driver vendor/device list.
Change-Id: I22021b24f9498c3cafe0e1d5f1c6562ea0be5aad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18480
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
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Cardhu boards can use Atmel and Winbond SPI flash
parts - support both in one binary.
BUG=chromium-os:23496
TEST=build all OK, test on Cardhu.
'sf probe 0' returns:
SF: Detected AT25DF321A with page size 256, total 4 MiB.
sf read/write/erase all work OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I7df3abb030a49b572e1172ca77227cd4d63e0c21
Reviewed-on: https://gerrit.chromium.org/gerrit/18539
Reviewed-by: Mike Frysinger <vapier@chromium.org>
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In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs,
the small value is the only value with the correct size. If it supports more,
if the number of sectors is small enough to fit into 28 bits, both fields
reflect the correct value. If it's too large, the smaller field has 28 bits of
1s, 0xfffffff, and the other field has the correct value.
The AHCI driver is implemented by attaching to the generic SCSI code and
translating on the fly between SCSI binary data structures and AHCI data
structures. It responds to requests to execute specific SCSI commands by
executing the equivalent AHCI commands and then crafting a response which
matches what a SCSI disk would send.
The AHCI driver now considers both fields and chooses the correct one when
implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands.
BUG=chrome-os-partner:8180
TEST=Built and booted to ChromeOS with this code on a CRB with a 250 GB drive
and a Stumpy with a 16 GB drive. Checked the serial output to make sure U-Boot
reported the correct size. Forced the READ CAPACITY (10) command to saturate
so that the READ CAPACITY (16) command would be used and verified that that
also booted correctly on a CRB.
Change-Id: I31b662498f4c9657d70bb90400032c83e9d9c8da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/18061
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We were not searching on the last PCI bus.
Fix the loop to go up to pci_last_busno() included.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Link with only one PCI bus active, see we can detect the
EHCI controllers.
Change-Id: Icdcd19df0c622039f56e7403c2616348b5d8b7d6
Reviewed-on: https://gerrit.chromium.org/gerrit/16481
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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Make Ctrl-Enter act like LF (Line Feed) such that u-boot can differentiate
it from pure Enter key. There are other Ctrl-(numeric keypad key)'s,
like Ctrl-[ for ESC (Escape) key, but they are not useful yet in current
u-boot. So keep the Ctrl-(key) and non-Ctrl-(key) tables the same except Enter.
This change is together with https://gerrit.chromium.org/gerrit/15749
BUG=chrome-os-partner:6759
TEST=compile the firmware and update it to Lumpy; during the dev screen,
press Ctrl-Enter to trigger USB boot.
Change-Id: Ie3197f7ba93ed63c851bdfb918c8e384c90977dd
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/15750
Reviewed-by: Simon Glass <sjg@chromium.org>
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As clock source for graphics related clocks is different
for Tegra2 and Tegra3, define it under platform specific
directories.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Original work by -
Mayuresh Kulkarni <mkulkarni@nvidia.com>
Change-Id: I6cee11df5e75eaf3836565c4fa4f3ab3e45d8cac
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14700
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Assert occurs due to LCD max height was bigger than default
Maximum LCD height, causing 'panel_info' is not initialized.
Increase default Max LCD height as Waluigi has LCD height in
pixel more than 768.
Initialize global variable 'lcd_line_length' correctly.
'lcd_line_length' was not initialized before use, causing
initialization of dependent variables wrongly.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I24a9fc54541c861c48fd885e2d58d32786c31bf8
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14699
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For Tegra2, pinmuxing is done in each driver, For Tegra3
it is done at boot up time.
Handling it conditionally for Tegra2 and Tegra3.
BUG=chromium-os:23496
TEST=Build ok for Cardhu, Waluigi and Seaboard. Tested on Waluigi.
Change-Id: I95e2dc4d46c0c47037611ff9177f2d8823c11d1f
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14695
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Enables common LCD support for Tegra2 and Tegra3
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard.
Change-Id: I39af6a01956a3f1545e7cccfa9c23a3f81d3dc0c
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14693
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Enables common LCD support for Tegra2 and Tegra3
BUG=chromium-os:23496
TEST=Built ok for Cardhu, Waluigi and Seaboard.
Change-Id: I938824045440cc4964c2ac6bf727a90ee5f129b4
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14692
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Replace Tegra2 specific tag "CONFIG_TEGRA2_KEYBOARD" by
common tag "CONFIG_TEGRA_KEYBOARD" to include tegra keyboard
driver.
BUG=chromium-os:23496
TEST=Build ok for Cardhu,Seaboard and Waluigi.
Change-Id: Idd16990ba525b8391c3c14e37efd5587f09a25c8
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13860
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Expand existing 4x6 keyboard support to 16x8 keyboard.
Add Tegra2 specific changes under Tegra2 config "CONFIG_TEGRA2".
BUG=chromium-os:23496
TEST=Tested on Waluigi.key press echoes the key on console.
Built ok for Cardhu and Seaboard.
Change-Id: Iab291a636d41b721d914014a5fe9ecc8775bf260
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13928
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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This command doesn't really do anything when talking to a SATA device, and
sending it confuses some of them. This change makes sending the command
optional, and defaults to not. The situations where it should be sent are not
the common case.
With the standard SSD in the machine, here are some times with the option
turned off:
1. 8277
2. 8273
3. 8050
And turned on:
1. 8303
2. 8155
3. 8276
Sending that command seems to have no meaningful effect on performance.
BUG=chrome-os-partner:7714
TEST=Booted off an SSD that hadn't worked with U-Boot previously. This SSD
was lent to us by Grant, and has chips labelled as Toshiba NV6424,
Taiwan 11159AE P, and TC58NVG5D2FTA10.
Change-Id: I750a6c7931a95a1529e0b99ee98528a549824ee4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/14916
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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- remove unused ssleep macro
- add some useful debugging information
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=none
TEST=boot latest firmware on stumpy, no functional change.
Change-Id: Ieef3c199225b8c1aa979dfebf8a6f2178d5aa316
Reviewed-on: https://gerrit.chromium.org/gerrit/14836
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
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- print the correct speed
- print all the AHCI capability flags
(information taken from Linux kernel driver)
- clean up some comments
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=chrome-os-partner:7714
TEST=See the following string in bios_log:
AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
Change-Id: Ib32dbeddd0714359948e2bec033b2ec7aabbdb10
Reviewed-on: https://gerrit.chromium.org/gerrit/14754
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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BUG=chromium-os:23496
TEST=Built ok for Cardhu Walgui and Seaboard. Tested on Waluigi.
Change-Id: I86d029e09713b0d8f885b97d7ec34119266dfe11
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13699
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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This adds support for generation of ANSI 3.64 escape sequences to the
PS/2 keyboard driver.
This change significantly refactors the code:
o It adds an FSA to support 0xE0 and 0xE1 multibyte PS/2
scan code sequences.
o It converts the PS/2 scan codes to USB scan code values
to facilitate sharing upper level code in future changes.
Reasons to use USB scan codes:
o Standard
o Simple conversion to ASCII / ANSI 3.64
o Ability to share complex processing / state code
o Shared international keymaps in higher level code
o It adds an ANSI 3.64 escape sequence generator for USB
special keys; the intent of doing this is to allow the
transparent use of PS/2, USB, and network or serial
devices using the same upper level u-boot clients.
o It adds an input FIFO which is an almost verbatim copy
of the Tegra matrix keyboard driver; future changes are
expected to share the FIFOcode among all keyboard drivers.
International keyboard support is expected to be handled at a higher
layer in the future, using a much smaller NRCS (National Replacement
Character Set) table instead of a duplicat table.
Combined, the changes reduce the overall source file size by about
5K, and removes about 4K from the data segment as well.
Note: Use of typedef for FSA states allows compiler to prohibit
switch statement without default case from omitting states.
BUG=chrome-os-partner:6580
TEST=Removed backslash from generated 3.64 sequences, stopped boot at
command line, verified character sequence generation.
Signed-off-by: tlambert@chromium.org
Change-Id: I00200c5ccefd44679335fb643b21794e5d77663a
modified: drivers/input/i8042.c
modified: include/i8042.h
Change-Id: I22c692f7bd65da5848908fc71c6cd7d04753f135
Reviewed-on: https://gerrit.chromium.org/gerrit/14218
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Gabe Black (Do Not Use) <gabeblack@google.com>
Tested-by: Terry Lambert <tlambert@chromium.org>
Commit-Ready: Terry Lambert <tlambert@chromium.org>
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ensure we cannot get stuck in the keyboard scanning if something wrong
happens (USB device unplugged or fatal I/O error)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:7188 chrome-os-partner:7430 chrome-os-partner:7432
chrome-os-partner:7559
TEST=On lumpy with usb keyboard configured, stress the USB stack and
check the keyboard traces.
Change-Id: I019ddefa073852ae1abfd4f223ba4c2d6a7bc054
Reviewed-on: https://gerrit.chromium.org/gerrit/14187
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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Rather than requesting the burst length on every transaction, just do it
at the start.
This saves 30ms on Kaen (TPM time now 325ms).
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I8a1b028882c28cd6089c2f7514bee285ef349f24
Reviewed-on: https://gerrit.chromium.org/gerrit/13374
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Add debugging options around most transactions.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I71dd48b59a4eefd39eccc29b61bfcd512d63aa56
Reviewed-on: https://gerrit.chromium.org/gerrit/13376
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The TPM fails every second transaction because it goes to sleep and fails
to wake up in time. Add stats for how many transactions are performed
and the number of retries required for each.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I079da55e71e637e3afdacfe38c27b8742da09dc5
Reviewed-on: https://gerrit.chromium.org/gerrit/13373
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Since burst_length is now set up at init time, it can never be < 0, and
we don't need to write the last byte in a separate I2C transaction.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I0050dd49ba151ee267f2790b550c0ffea4cd976f
Reviewed-on: https://gerrit.chromium.org/gerrit/13375
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The intent is for LCD init to happen such that we never need to call
udelay(). Add tracking that this is indeed the case, and report it
with the boot time report.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I78e458a6b878a4237e4e059525bae4fa47844ed9
Reviewed-on: https://gerrit.chromium.org/gerrit/13377
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Indent all but the top-level messages which indicate a new transaction.
This makes it much easier to follow the debug trace.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I3259c4e266f87ce4da8ce590f837542e5b219539
Reviewed-on: https://gerrit.chromium.org/gerrit/13372
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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We need to make sure that the LCD is ready before we complete booting, so
put this code into board_late_init().
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I97bd1fce6ac93d0639dd8fdb17bf83e8a78d2645
Reviewed-on: https://gerrit.chromium.org/gerrit/13213
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Prior to relocation it is expensive to find out the LCD dimensions. Instead
we select the maximum possible size and allow lcd_ctrl_init() to correct
this later.
This works since the only purpose of this early init is to set the LCD
frame buffer size. So long as we set it to the largest value that could
possible be requested, all will be well.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I850ee5cb2b6bf051e32c6a52c42c368a940ea045
Reviewed-on: https://gerrit.chromium.org/gerrit/13212
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The LCD init takes place over five stages. We want to hide this init
behind other operations, so turn it into a state machine which we can
call at any time.
For now, call it in lcd_enable().
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: Ia0b50ec74108ac4e015de12b7a9628426ea17656
Reviewed-on: https://gerrit.chromium.org/gerrit/13211
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The interrupt endpoint handling code stores the buffer pointer in the QH
padding field. We need to make it the size of a pointer to avoid strict
aliasing issue with the compiler.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:24760
TEST=emerge-lumpy chromeos-u-boot ; emerge-tegra2_kaen chromeos-u-boot
Change-Id: Iecbfa0610591d24452106b79de61abb033c36f2e
Reviewed-on: https://gerrit.chromium.org/gerrit/13732
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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Interrupt transfers aren't meant to be used from the async list
(the EHCI spec indicates trouble with low/full-speed intr on async).
Build a periodic list instead, and provide an API to make use of it.
Then, use that API from the existing interrupt transfer API.
BUG=chrome-os-partner:5752
TEST=Use USB keyboard in u-boot (recovery mode) when later
commits make use of this code
Change-Id: I9bf0ef838af1076f8060c39bd942d95271cf0035
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://gerrit.chromium.org/gerrit/13489
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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Until we bring in the newer MMC code from upstream, this enables 8-bit
support with a minimum of changes.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I5c3f5e6f4003ae63e08208d9afba66aef8d97ccf
Reviewed-on: https://gerrit.chromium.org/gerrit/13202
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Timeouts should use get_timer() where possible, and avoid looping
with fixed delays. This improves performance.
BUG=chromium-os:22938
TEST=build and boot on Kaen
Change-Id: I7e11151ddc0ac2faf14e05593181470558a52ab2
Reviewed-on: https://gerrit.chromium.org/gerrit/13199
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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BUG=none
TEST=emerge-tegra_kaen chromeos-u-boot
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
CQ-DEPEND=Ibb8f42116812dba74e726129ea92a941e15c272b
Change-Id: Iba58e415e7cd6deafa5744c1ff501a8ea5730d1e
Reviewed-on: https://gerrit.chromium.org/gerrit/13227
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
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BUG=none
TEST=emerge-tegra_kaen chromeos-u-boot
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Change-Id: Ibb8f42116812dba74e726129ea92a941e15c272b
Reviewed-on: https://gerrit.chromium.org/gerrit/13226
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
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BUG=chromium-os:23496
TEST=built Seaboard and Waluigi OK
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I52fcccc1627d1e9b6e0270e5ba9ab81c5d7fa9b7
Reviewed-on: https://gerrit.chromium.org/gerrit/12444
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New device ID range is included to allow the SPI driver to use the
Panther Point based controller and a new device ID is checked when
attaching the AHCI controller.
BUG=chrome-os-partner:7112
TEST=manual
After this change the top of the tree ChromeOS can be booted on IVB
reworked Stumpy platforms.
Change-Id: Ia41c17b58337cde2d041990b3d1c9da37c0cd92c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/12606
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
(cherry picked from u-boot-usb.git
commit 62d5f9a8b9e9a395b7e8af3344a2b2e47157c8f9)
BUG=chrome-os-partner:5752
TEST=on Lumpy, use USB keyboard to enter commands on U-Boot command line
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Change-Id: I6986ebda2191caf641444fca8909b253867e873b
Reviewed-on: https://gerrit.chromium.org/gerrit/12510
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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According to EHCI specification v1.0, the controller should stabilize
the power on a port at most 20 ms after the port power bit transition.
So, we put this setting in the virtual descriptor corresponding field,
(bPwrOn2PwrGood = 10 => 10 x 2ms = 20ms), this saves about 500ms at each
controller initialization/enumeration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:6344
TEST=check USB time stamp on Lumpy before and after the patch
Change-Id: Ia09f62bdb6545387e5e7386ef9095abd53a7d192
Reviewed-on: https://gerrit.chromium.org/gerrit/12491
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
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The Winbond W25X40 is now being used in the IP02 (and possibly IP04).
Tested and working on the actual device.
(cherry picked from commit ad8e3bd65766f670007bc5ae7c19b64e69e3dceb)
Change-Id: I0e395dc6c10086a330d2a32e8f7601afe1a1792d
Reviewed-on: https://gerrit.chromium.org/gerrit/11864
Reviewed-by: Taylor Hutt <thutt@chromium.org>
Tested-by: Taylor Hutt <thutt@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi AOK
Change-Id: Ia860abf5ef3af66b3a39d4c57192455986b7a4f4
Reviewed-on: https://gerrit.chromium.org/gerrit/11704
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Ready: Doug Anderson <dianders@chromium.org>
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BUG=chromium-os:21033
TEST=run `sf erase, write` and then `sf read` on seaboard
verify the data it reads from SPI flash matches that it writes to
Change-Id: I1b04afa4b54738cd93be29b70f428bdc3e6b234f
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/11472
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=none
TEST=built Seaboard and Waluigi OK. Booted Waluigi OK.
Change-Id: I1bfbe03945d7dae44e0840349b9698fc08cef07d
Reviewed-on: https://gerrit.chromium.org/gerrit/11504
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
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The U-boot spi interface uses Software Sequencing and handles
write transactions in three distinct steps:
1) issue Write Enable op
2) issue Page Program op
3) poll Read Status Reg for completion
However in an Intel 6-series chipset the Management Engine is
also issuing a lot of transactions through the same controller
to the same chip. It is possible for an ME transaction to
occur between the U-boot issuing WREN and sending the actual
data, resulting in the host WREN being lost and the data not
actually being written to the chip.
This change intercepts WREN opcode and instead applies it as
a prefix operator for the next issued transaction, ensuring
that the two are issued back-to-back to the SPI chip.
Unfortunately this register is not writable when the SPI
contoller is locked down, so it is not always applicable.
BUG=chrome-os-partner:6690
TEST=repeated manual testing on lumpy with boot/suspend/resume
Change-Id: I75e353942fd6148a93be561ff422e37dfc6dc8c4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11625
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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BUG=chromium-os:21033
TEST=build seaboard successfully
Change-Id: Idbfbdbf0bdb1070f4a2b5f8205c1caff6ef0c811
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11471
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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BUG=chromium-os:21540
TEST=Able to talk to MMC1 on Waluigi w/ future config changes.
Specifically:
1. mmcinfo 0 - works (shows info)
2. mmcinfo 1 - works (shows info)
3. mmc rescan 1; mmc part 1 - works (shows partitions)
Change-Id: I730d3b91088f20ccf7ca20f3f31f7d59514af243
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10661
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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BUG=chromium-os:21540
TEST=Built u-boot and booted u-boot on tegra2_kaen
Change-Id: Id6f11512ea1a95bd57b600601b488ae20b34db2d
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/10808
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This change adds a board overridable function which can be used to decide
whether or not to initialize the i8042 keyboard controller. On systems where
it isn't actually connected to anything, this can save a significant amount of
boot time.
On Stumpy, this saves about 200ms on boot.
BUG=chrome-os-partner:6585
TEST=Built and booted on Stumpy. Built and booted on Alex.
Change-Id: Ibac6fd4149fd125f6461ae4e86936eb9b012edb6
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/10624
Commit-Ready: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
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On x86, the i8042 keyboard controller driver frequently waits for the keyboard
input buffer to be empty to make sure the controller has had a chance to
process the data it was given. The way the delay loop was structured, if the
controller hadn't cleared the corresponding status bit immediately, it would
wait 1ms before checking again. If the keyboard responded quickly but not
instantly, the driver would still wait a full 1ms when perhaps 1us would have
been sufficient. Because udelay is a busy wait anyway, this change decreases
the delay between checks to 1us.
Also, this change gets rid of a hardcoded 250ms delay.
On Stumpy, this saves 100-150ms during boot. Also, the total boot time I'm
measuring at ToT is a little higher than expected. I'd like to see what other
people measure.
BUG=chrome-os-partner:6585
TEST=Built and booted on Stumpy. Built and booted on Alex, and verified that
the keyboard still worked at the u-boot prompt.
Change-Id: Ic361c4e88ded8e57b4377790dd011a11a0ce385b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/10623
Commit-Ready: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
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BUG=chromium-os:21540
TEST=With future config change, saw that I could run i2c probe on
busses 0-3
Change-Id: Ibfad91a3e7360434111c7aa6d2ea45f73e9690fc
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/10366
Reviewed-by: Simon Glass <sjg@chromium.org>
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