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path: root/include/configs/MPC837XEMDS.h
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2009-07-27mpc83xx: CONFIG_83XX_GENERIC_PCI is now synonymous with CONFIG_PCI; remove ↵Kim Phillips
the former Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-16mpc83xx: MPC837XEMDS: Fixup eSDHC nodes in device treeAnton Vorontsov
fdt_fixup_esdhc() will either disable or enable eSDHC nodes, and also will fixup clock-frequency property. Plus, since DR USB and eSDHC are mutually exclusive, we should only configure the eSDHC if asked through hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-1283xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser
Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-1283xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xxPeter Tyser
Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-18rename CONFIG_CMD_ENV to CONFIG_CMD_SAVEENVMike Frysinger
The CONFIG_CMD_ENV option controls enablement of the `saveenv` command rather than a generic "env" command, or anything else related to the environment. So, let's make sure the define is named accordingly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-1683xx: Add eSDHC support on 8379 EMDS boardAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-01-23Merge branch 'next'Kim Phillips
2009-01-23NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-21mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov
MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov
With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov
Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov
This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-24mpc83xx: add h/w flash protection to board configsKim Phillips
the operating system may leave flash in a h/w locked state after writing. This allows u-boot to continue to write flash by enabling h/w unlocking by default. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-10rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHEREJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13drivers/mtd: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-06-1083xx/85xx: further localbus cleanupsAnton Vorontsov
move the BRx_* and ORx_* left behind in mpc85xx.h The same is needed for mpc8xx.h and mpc8260.h (defines are almost the same, just few differences which needs some attention though). But the bad news for mpc8xx and mpc8260 is that there are a lot of users of these defines. So this cleanup I'll leave for the "better times". Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-03PPC: Create and use CONFIG_HIGH_BATSBecky Bruce
Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-04-25mpc83xx: bump loadaddr over fdtaddr to 0x500000Kim Phillips
this seems as a good compromise between human memory, typing, and last but not least, to accommodate for current and future kernel bloat. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Dave Liu <daveliu@freescale.com>
2008-04-11mpc83xx: Fix the SATA clock setting of 837x targetsDave Liu
Currently the SATA controller clock is configured as CSB clock, usually the CSB clock is 400/333/266MHz. However, The SATA IP block is only guaranteed to operate up to 200 MHz as stated in the HW spec. The bug is reported by Joe D'Abbraccio <ljd015@freescale.com> This patch makes the SATA clock as half of CSB clock. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: enable the SATA interface on mpc837xemds boardDave Liu
Enable the first two SATA interfaces on MPC837xEMDS board, The two SATA ports are on LYNX1. (SATA0/1 on J4/5) Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: initialize serdes for MPC837xEMDS boardsDave Liu
This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc83xx: Set PCI I/O bus-address base to zero.Scott Wood
The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-03-07mpc83xx: make dtb basename file references equal those of linuxKim Phillips
the dts file basenames were updated in linux - this helps avoid inadvertently loading any old dtbs laying around. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-07837xEMDS: Improve the system performanceDave Liu
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode; 2. Raise the eTSEC emergency priority; 3. Use the highest IP blocks clock. Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-02-12Remove #undef DEBUG from MPC83xx board header filesTimur Tabi
Remove the "#undef DEBUG" line from all Freescale 83xx board header files. The inclusion of this line makes it impossible to enable debug code in other source files, because "#define DEBUG" typically needs to be defined before any header files are included. Signed-off-by: Timur Tabi <timur@freescale.com>
2008-01-10mpc83xx: Make the code more readableDave Liu
Format the code, make it more readable Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10mpc83xx: Reduce the latency of DDRDave Liu
Reduce the AL from 2 to 1 clock to improve the performance. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10mpc83xx: Remove cache config from config.hDave Liu
clean up the cache config from configs.h of board Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08mpc83xx: convert to using do_fixup_*()Kim Phillips
convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x)Kim Phillips
continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837xKim Phillips
Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08mpc83xx: Add the support of MPC837xEMDS boardDave Liu
The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
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