From ed64190f67a28e9830371d424998b8aa924be9f3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 1 Aug 2015 08:55:46 -0600 Subject: arm: Correct comments in crt0.S for the recent SPL improvements The current comments need a bit of tweaking since we now support stack and global_data relocation in SPL. Also add a reference to the README. For AArch64 this is not implemented, so leave a TODO for this. Signed-off-by: Simon Glass Reported-by: Tim Harvey --- arch/arm/lib/crt0.S | 26 ++++++++++++++++---------- arch/arm/lib/crt0_64.S | 30 ++++++++++++++++++++---------- 2 files changed, 36 insertions(+), 20 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index afd4f102dc..4c3a94af57 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -25,7 +25,8 @@ * the GD ('global data') structure, both located in some readily * available RAM (SRAM, locked cache...). In this context, VARIABLE * global data, initialized or not (BSS), are UNAVAILABLE; only - * CONSTANT initialized data are available. + * CONSTANT initialized data are available. GD should be zeroed + * before board_init_f() is called. * * 2. Call board_init_f(). This function prepares the hardware for * execution from system RAM (DRAM, DDR...) As system RAM may not @@ -34,24 +35,29 @@ * data include the relocation destination, the future stack, and * the future GD location. * - * (the following applies only to non-SPL builds) - * * 3. Set up intermediate environment where the stack and GD are the * ones allocated by board_init_f() in system RAM, but BSS and * initialized non-const data are still not available. * - * 4. Call relocate_code(). This function relocates U-Boot from its - * current location into the relocation destination computed by - * board_init_f(). + * 4a.For U-Boot proper (not SPL), call relocate_code(). This function + * relocates U-Boot from its current location into the relocation + * destination computed by board_init_f(). + * + * 4b.For SPL, board_init_f() just returns (to crt0). There is no + * code relocation in SPL. * * 5. Set up final environment for calling board_init_r(). This * environment has BSS (initialized to 0), initialized non-const * data (initialized to their intended value), and stack in system - * RAM. GD has retained values set by board_init_f(). Some CPUs - * have some work left to do at this point regarding memory, so - * call c_runtime_cpu_setup. + * RAM (for SPL moving the stack and GD into RAM is optional - see + * CONFIG_SPL_STACK_R). GD has retained values set by board_init_f(). + * + * 6. For U-Boot proper (not SPL), some CPUs have some work left to do + * at this point regarding memory, so call c_runtime_cpu_setup. + * + * 7. Branch to board_init_r(). * - * 6. Branch to board_init_r(). + * For more information see 'Board Initialisation Flow in README. */ /* diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 98a906ee11..8b34e04dad 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -27,7 +27,8 @@ * the GD ('global data') structure, both located in some readily * available RAM (SRAM, locked cache...). In this context, VARIABLE * global data, initialized or not (BSS), are UNAVAILABLE; only - * CONSTANT initialized data are available. + * CONSTANT initialized data are available. GD should be zeroed + * before board_init_f() is called. * * 2. Call board_init_f(). This function prepares the hardware for * execution from system RAM (DRAM, DDR...) As system RAM may not @@ -36,24 +37,31 @@ * data include the relocation destination, the future stack, and * the future GD location. * - * (the following applies only to non-SPL builds) - * * 3. Set up intermediate environment where the stack and GD are the * ones allocated by board_init_f() in system RAM, but BSS and * initialized non-const data are still not available. * - * 4. Call relocate_code(). This function relocates U-Boot from its - * current location into the relocation destination computed by - * board_init_f(). + * 4a.For U-Boot proper (not SPL), call relocate_code(). This function + * relocates U-Boot from its current location into the relocation + * destination computed by board_init_f(). + * + * 4b.For SPL, board_init_f() just returns (to crt0). There is no + * code relocation in SPL. * * 5. Set up final environment for calling board_init_r(). This * environment has BSS (initialized to 0), initialized non-const * data (initialized to their intended value), and stack in system - * RAM. GD has retained values set by board_init_f(). Some CPUs - * have some work left to do at this point regarding memory, so - * call c_runtime_cpu_setup. + * RAM (for SPL moving the stack and GD into RAM is optional - see + * CONFIG_SPL_STACK_R). GD has retained values set by board_init_f(). + * + * TODO: For SPL, implement stack relocation on AArch64. * - * 6. Branch to board_init_r(). + * 6. For U-Boot proper (not SPL), some CPUs have some work left to do + * at this point regarding memory, so call c_runtime_cpu_setup. + * + * 7. Branch to board_init_r(). + * + * For more information see 'Board Initialisation Flow in README. */ ENTRY(_main) @@ -106,6 +114,8 @@ relocation_return: */ bl c_runtime_cpu_setup /* still call old routine */ +/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ + /* * Clear BSS section */ -- cgit v1.2.3 From 208bd51396fb606dbdcf45b064e6b372d7dd3e81 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 6 Aug 2015 17:54:13 +0800 Subject: arm: armv8 correct value passed to __asm_dcache_all >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan Cc: York Sun Cc: Albert Aribaud --- arch/arm/cpu/armv8/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index d846236500..ab8c08917a 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -112,7 +112,7 @@ ENDPROC(__asm_flush_dcache_all) ENTRY(__asm_invalidate_dcache_all) mov x16, lr - mov x0, #0xffff + mov x0, #0x1 bl __asm_dcache_all mov lr, x16 ret -- cgit v1.2.3 From 55aa0bed9803b8a5bd3e462fd712741c2e1cff1b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:52:13 +0200 Subject: armv8/mmu: Clean up TCR programming Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm/include/asm/armv8/mmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0c928d40e7..a1c3c06539 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -103,9 +103,9 @@ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ -/* PTWs cacheable, inner/outer WBWA and non-shareable */ +/* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ + TCR_SHARED_INNER | \ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) -- cgit v1.2.3 From ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:52:14 +0200 Subject: armv8/mmu: Set bits marked RES1 in TCR For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm/cpu/armv8/cache_v8.c | 6 +++--- arch/arm/include/asm/armv8/mmu.h | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf6a0..b1ea8227cb 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -59,15 +59,15 @@ static void mmu_setup(void) el = current_el(); if (el == 1) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, + TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS, MEMORY_ATTRIBUTES); } else if (el == 2) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, + TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS, MEMORY_ATTRIBUTES); } else { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, + TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS, MEMORY_ATTRIBUTES); } /* enable the mmu */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index a1c3c06539..587ee39909 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -110,6 +110,10 @@ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#define TCR_EL1_RSVD (1 << 31) +#define TCR_EL2_RSVD (1 << 31 | 1 << 23) +#define TCR_EL3_RSVD (1 << 31 | 1 << 23) + #ifndef __ASSEMBLY__ void set_pgtable_section(u64 *page_table, u64 index, -- cgit v1.2.3 From b1964c72bdb9ca44de3a56d40927409b8cab2a76 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:52:15 +0200 Subject: armv8/gic: Fix GIC v2 initialization Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier Suggested-by: Mark Rutland Cc: Albert Aribaud Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm/lib/gic_64.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index a3e18f7713..62d0022408 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -46,11 +46,19 @@ ENTRY(gic_init_secure) ldr w9, [x0, GICD_TYPER] and w10, w9, #0x1f /* ITLinesNumber */ cbz w10, 1f /* No SPIs */ - add x11, x0, (GICD_IGROUPRn + 4) + add x11, x0, GICD_IGROUPRn mov w9, #~0 /* Config SPIs as Grp1 */ + str w9, [x11], #0x4 0: str w9, [x11], #0x4 sub w10, w10, #0x1 cbnz w10, 0b + + ldr x1, =GICC_BASE /* GICC_CTLR */ + mov w0, #3 /* EnableGrp0 | EnableGrp1 */ + str w0, [x1] + + mov w0, #1 << 7 /* allow NS access to GICC_PMR */ + str w0, [x1, #4] /* GICC_PMR */ #endif 1: ret -- cgit v1.2.3