From c798a6d9e4035d8427857bcb41cd521972e4332d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 22 Jul 2014 18:14:56 +0200 Subject: colibri vf50/61: use PLL2 as DRAM clock source On migration from 2011.11 to 2014.04 U-Boot the initialization code also switched the source of the DRAM clock to system clock. However, since Colibri VF61 runs on 500MHz system clock, we should use PLL2 as DRAM clock. This also broke suspend on resume: The system switches to 24MHz FIRC as system clock when entering suspend mode while still running from DRAM. However, DRAM seems not to work on 24MHz, which then lead to a system freeze during entering suspend mode. --- board/toradex/colibri_vf/colibri_vf.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index f7f5807dee..f079c3dcc8 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -388,23 +388,27 @@ static void clock_init(void) clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | ANADIG_PLL5_CTRL_DIV_SELECT); - clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, - ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | + ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | + ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); + clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); /* See "Typical PLL Configuration" */ pfd_clk_sel = is_colibri_vf61() ? CCM_CCSR_PLL1_PFD_CLK_SEL(1) : CCM_CCSR_PLL1_PFD_CLK_SEL(3); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | - CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | + CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, -- cgit v1.2.3