From 9e758758491b0d7a71bdf1db8cd860b599d7e657 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:19 +0000 Subject: powerpc/mpc85xx: Add T4240 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming Signed-off-by: Roy Zang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Andy Fleming --- drivers/pci/fsl_pci_init.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers/pci/fsl_pci_init.c') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 86ccbe7ee8..e8eb9d6db7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -666,10 +666,17 @@ int fsl_configure_pcie(struct fsl_pci_info *info, } #if defined(CONFIG_FSL_CORENET) +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1 + #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2 + #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3 + #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4 +#else #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 +#endif #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE @@ -749,34 +756,42 @@ int fsl_pcie_init_board(int busno) { struct fsl_pci_info pci_info; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; - u32 devdisr = in_be32(&gur->devdisr); + u32 devdisr; + u32 *addr; + +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + addr = &gur->devdisr3; +#else + addr = &gur->devdisr; +#endif + devdisr = in_be32(addr); #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info, 1); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE1); /* disable */ #endif #ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info, 2); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE3 SET_STD_PCIE_INFO(pci_info, 3); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE4 SET_STD_PCIE_INFO(pci_info, 4); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ #endif return busno; -- cgit v1.2.3