From 067716bac59716b07f1ee70d9bf6e5528289bb45 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 22 Aug 2016 08:22:17 -0400 Subject: ARM: Move SYS_CACHELINE_SIZE over to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud Cc: Marek Vasut Cc: Stefano Babic Cc: Prafulla Wadaskar Cc: Luka Perkov Cc: Stefan Roese Cc: Nagendra T S Cc: Vaibhav Hiremath Acked-by: Lokesh Vutla Cc: Steve Rae Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Stefan Agner Acked-by: Heiko Schocher Cc: Mateusz Kulikowski Cc: Peter Griffin Acked-by: Paul Kocialkowski Cc: Anatolij Gustschin Acked-by: "Pali Rohár" Cc: Adam Ford Cc: Steve Sakoman Cc: Grazvydas Ignotas Cc: Nishanth Menon Cc: Stephen Warren Cc: Robert Baldyga Cc: Minkyu Kang Cc: Thomas Weber Cc: Masahiro Yamada Cc: David Feng Cc: Alison Wang Cc: Michal Simek Cc: Simon Glass Cc: York Sun Cc: Shengzhou Liu Cc: Mingkai Hu Cc: Prabhakar Kushwaha Cc: Aneesh Bansal Cc: Saksham Jain Cc: Qianyu Gong Cc: Wang Dongsheng Cc: Alex Porosanu Cc: Hongbo Zhang Cc: tang yuantian Cc: Rajesh Bhagat Cc: Josh Wu Cc: Bo Shen Cc: Viresh Kumar Cc: Hannes Schmelzer Cc: Thomas Chou Cc: Joe Hershberger Cc: Sam Protsenko Cc: Bin Meng Cc: Christophe Ricard Cc: Anand Moon Cc: Beniamino Galvani Cc: Carlo Caione Cc: huang lin Cc: Sjoerd Simons Cc: Xu Ziyuan Cc: "jk.kernel@gmail.com" Cc: "Ariel D'Alessandro" Cc: Kever Yang Cc: Samuel Egli Cc: Chin Liang See Cc: Dinh Nguyen Cc: Hans de Goede Cc: Ian Campbell Cc: Siarhei Siamashka Cc: Boris Brezillon Cc: Andre Przywara Cc: Bernhard Nortmann Cc: Wolfgang Denk Cc: Ben Whitten Cc: Tom Warren Cc: Alexander Graf Cc: Sekhar Nori Cc: Vitaly Andrianov Cc: "Andrew F. Davis" Cc: Murali Karicheri Cc: Carlos Hernandez Cc: Ladislav Michl Cc: Ash Charles Cc: Mugunthan V N Cc: Daniel Allred Cc: Gong Qianyu Signed-off-by: Tom Rini Acked-by: Masahiro Yamada Acked-by: Chin Liang See Tested-by: Stephen Warren Acked-by: Paul Kocialkowski --- include/configs/am43xx_evm.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/configs/am43xx_evm.h') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 0467953566..518b904807 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -11,7 +11,6 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -49,7 +48,6 @@ /* Enabling L2 Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* * Since SPL did pll and ddr initialization for us, -- cgit v1.2.3