// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
 */

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		pinctrl0 = &pinctrl;
	};

#if defined(CONFIG_TFABOOT)
	firmware {
		optee {
			bootph-all;
		};
	};

	/* need PSCI for sysreset during board_f */
	psci {
		bootph-some-ram;
	};
#else
	binman: binman {
		multiple-images;

		spl-stm32 {
			filename = "u-boot-spl.stm32";
			mkimage {
				args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000";
				u-boot-spl {
					no-write-symbols;
				};
			};
		};
	};

	clocks {
		bootph-all;

		clk_hse: ck_hse {
			bootph-all;
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: ck_hsi {
			bootph-all;
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: ck_lse {
			bootph-all;
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: ck_lsi {
			bootph-all;
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_csi: ck_csi {
			bootph-all;
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		bootph-pre-ram;
		opp-650000000 {
			bootph-pre-ram;
			opp-hz = /bits/ 64 <650000000>;
			opp-microvolt = <1200000>;
			opp-supported-hw = <0x1>;
		};
		opp-1000000000 {
			bootph-pre-ram;
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1350000>;
			opp-supported-hw = <0x2>;
		};
	};

	reboot {
		bootph-all;
		compatible = "syscon-reboot";
		regmap = <&rcc>;
		offset = <0x114>;
		mask = <0x1>;
	};
#endif

	soc {
		bootph-all;

		ddr: ddr@5a003000 {
			bootph-all;

			compatible = "st,stm32mp13-ddr";

			reg = <0x5A003000 0x550
			       0x5A004000 0x234>;

			status = "okay";
		};
	};
};

&bsec {
	bootph-all;
};

&etzpc {
	bootph-all;
};

#if !defined(CONFIG_TFABOOT)
&cpu0 {
	nvmem-cells = <&part_number_otp>;
	nvmem-cell-names = "part_number";
	operating-points-v2 = <&cpu0_opp_table>;
};
#endif

&gpioa {
	bootph-all;
};

&gpiob {
	bootph-all;
};

&gpioc {
	bootph-all;
};

&gpiod {
	bootph-all;
};

&gpioe {
	bootph-all;
};

&gpiof {
	bootph-all;
};

&gpiog {
	bootph-all;
};

&gpioh {
	bootph-all;
};

&gpioi {
	bootph-all;
};

&iwdg2 {
	bootph-all;
};

&pinctrl {
	bootph-all;
};

&rcc {
	bootph-all;
};

&scmi {
	bootph-all;
};

&scmi_clk {
	bootph-all;
};

&scmi_reset {
	bootph-all;
};

&syscfg {
	bootph-all;
};

&usbphyc {
	/* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */
	bootph-all;
};