/* SPDX-License-Identifier: GPL-2.0+ */ /* * Configuration settings for the TechNexion TAO-3530 SOM * equipped on Thunder baseboard. * * Edward Lin * Tapani Utriainen * * Copyright (C) 2013 Stefan Roese */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options */ #include /* get chip and board defs */ #include /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG /* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* * Hardware drivers */ /* * NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE /* commands to include */ #define CONFIG_SYS_I2C #define CONFIG_I2C_MULTI_BUS /* * TWL4030 */ /* * Board NAND Info. */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ "mpurate=600\0" \ "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ "tv_mode=omapfb.mode=tv:ntsc\0" \ "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ "extra_options= \0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype} " \ "${extra_options}\0" \ "nandargs=setenv bootargs console=${console} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "${network_setting} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype} "\ "${extra_options}\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ "if run loaduimage; then " \ "run mmcboot; " \ "else run nandboot; " \ "fi; " \ "fi; " \ "else run nandboot; fi" /* * Miscellaneous configurable options */ /* turn on command-line edit/hist/auto */ /* defaults */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* * Physical Memory Map */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* * FLASH and environment organization */ /* **** PISMO SUPPORT *** */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) /* * USB * * Currently only EHCI is enabled, the MUSB OTG controller * is not enabled. */ /* USB EHCI */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 /* Defines for SPL */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS /* * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT */ #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13 } #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE) /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the * older x-loader implementations. And move the BSS area so that it * doesn't overlap with TEXT_BASE. */ #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #endif /* __CONFIG_H */