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|
/*
* Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8qm-cockpit-a72.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
aliases {
gpio8 = &max7322;
};
chosen {
bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
stdout-path = &lpuart2;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
status = "disabled";
};
epdev_on: fixedregulator@100 {
compatible = "regulator-fixed";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_wlreg_on>;
pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "epdev_on";
gpio = <&gpio1 13 0>;
enable-active-high;
};
};
};
&iomuxc {
pinctrl-names = "default";
imx8qm-mek {
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020
SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
>;
};
pinctrl_pciea: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
fsl,pins = <
SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
>;
};
pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
fsl,pins = <
SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
>;
};
pinctrl_wlreg_on: wlregongrp{
fsl,pins = <
SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000
>;
};
pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
fsl,pins = <
SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000
>;
};
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
};
&gpio2 {
};
&gpio3 {
status = "okay";
};
&gpio4 {
};
&gpio5 {
};
&gpio6 {
status = "okay";
};
&gpio7 {
status = "okay";
};
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
status = "disabled";
};
&usbotg3 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
/delete-property/ iommus;
status = "okay";
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
typec_ptn5110: typec@50 {
compatible = "usb,tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x51>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
src-pdos = <0x380190c8 0x3803c0c8>;
port-type = "drp";
sink-disable;
default-role = "source";
status = "okay";
};
};
&lpuart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&i2c1_lvds0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
};
};
&i2c1_lvds1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
};
};
&pciea{
ext_osc = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
epdev_on = <&epdev_on>;
status = "okay";
};
&sata {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
/delete-property/ iommus;
status = "okay";
};
&tsens {
tsens-num = <6>;
};
&thermal_zones {
pmic-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 5>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&pmic_alert0>;
cooling-device =
<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&display {
ports = <&dpu2_disp0>, <&dpu2_disp1>;
};
/delete-node/ &dpu1;
/delete-node/ &fec1;
/delete-node/ &ldb1;
/delete-node/ &isi_0;
/delete-node/ &lpuart0;
/delete-node/ &lpuart1;
/delete-node/ &lpuart3;
/delete-node/ &lpuart4;
/delete-node/ &i2c2;
/delete-node/ &i2c3;
/delete-node/ &i2c4;
/delete-node/ &i2c1_lvds0;
/delete-node/ &usdhc2;
/delete-node/ &usdhc3;
/delete-node/ &flexspi0;
/delete-node/ &dpu1_intsteer;
/delete-node/ &lvds_region1;
/delete-node/ &ldb1_phy;
/delete-node/ &hdmi;
/delete-node/ &i2c0_hdmi;
/delete-node/ &irqsteer_lvds0;
/delete-node/ &mipi_dsi1;
/delete-node/ &mipi_dsi_bridge1;
/delete-node/ &i2c0_mipi_dsi0;
/delete-node/ &lpspi0;
/delete-node/ &mlb;
/delete-node/ &pciea;
/delete-node/ &pcieb;
/delete-node/ &pinctrl_lvds0_lpi2c1;
|
