blob: 7e287db2f81c975bf6ebbeea74f1e0ab1cd967e2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
&{/aliases} {
video0 = &lcdif1;
video1 = &lcdif2;
display0 = &ldb;
};
&lcdif1 {
status = "okay";
display0: display@0 {
bits-per-pixel = <24>;
bus-width = <24>;
};
};
&lcdif2 {
#address-cells = <1>;
#size-cells = <0>;
display1: display@1 {
bits-per-pixel = <18>;
bus-width = <18>;
};
port@0 {
reg = <0>;
lcdif2_lvds0: endpoint@0 {
remote-endpoint = <&ldb_lvds0>;
};
};
};
&{/soc/bus@2000000/ldb@20e0014/lvds-channel@0} {
#address-cells = <1>;
#size-cells = <0>;
display-timings {
native-mode = <&timing1>;
timing1: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
port@0 {
reg = <0>;
ldb_lvds0: endpoint {
remote-endpoint = <&lcdif2_lvds0>;
};
};
};
ðphy1 {
vddio1: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
ðphy2 {
vddio2: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
|