arch/arm/dts/imx8mm-ab2-u-boot.dtsi


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// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2020 NXP
 */

/ {
	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	u-boot,dm-pre-reloc;
	u-boot,dm-spl;
};

&clk {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;
};

&osc_24m {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
};

&aips1 {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
};

&aips2 {
	u-boot,dm-spl;
};

&aips3 {
	u-boot,dm-spl;
};

&iomuxc {
	u-boot,dm-spl;
};

&reg_usdhc2_vmmc {
	u-boot,dm-spl;
};

&pinctrl_reg_usdhc2_vmmc {
	u-boot,dm-spl;
};

&pinctrl_uart2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc2_gpio {
	u-boot,dm-spl;
};

&pinctrl_usdhc2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc3 {
	u-boot,dm-spl;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&gpio3 {
	u-boot,dm-spl;
};

&gpio4 {
	u-boot,dm-spl;
};

&gpio5 {
	u-boot,dm-spl;
};

&uart2 {
	u-boot,dm-spl;
};

&usdhc1 {
	u-boot,dm-spl;
	assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};

&usdhc2 {
	u-boot,dm-spl;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};

&usdhc3 {
	u-boot,dm-spl;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};

&i2c1 {
	u-boot,dm-spl;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
	u-boot,dm-spl;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
	u-boot,dm-spl;
};

&pinctrl_i2c1 {
	u-boot,dm-spl;
};

&pinctrl_pmic {
	u-boot,dm-spl;
};

&flexspi {
	assigned-clock-rates = <100000000>;
	assigned-clocks = <&clk IMX8MM_CLK_QSPI>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
};